| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 2678 { ISD::FMAXNUM, MVT::f32, 2 }, in getTypeBasedIntrinsicInstrCost()
2679 { ISD::FMAXNUM, MVT::v4f32, 2 }, in getTypeBasedIntrinsicInstrCost()
2680 { ISD::FMAXNUM, MVT::v8f32, 2 }, in getTypeBasedIntrinsicInstrCost()
2681 { ISD::FMAXNUM, MVT::v16f32, 2 }, in getTypeBasedIntrinsicInstrCost()
2682 { ISD::FMAXNUM, MVT::f64, 2 }, in getTypeBasedIntrinsicInstrCost()
2683 { ISD::FMAXNUM, MVT::v2f64, 2 }, in getTypeBasedIntrinsicInstrCost()
2684 { ISD::FMAXNUM, MVT::v4f64, 2 }, in getTypeBasedIntrinsicInstrCost()
2685 { ISD::FMAXNUM, MVT::v8f64, 2 }, in getTypeBasedIntrinsicInstrCost()
2747 { ISD::FMAXNUM, MVT::v8f32, 3 }, // MAXPS + CMPUNORDPS + BLENDVPS in getTypeBasedIntrinsicInstrCost()
2748 { ISD::FMAXNUM, MVT::v4f64, 3 }, // MAXPD + CMPUNORDPD + BLENDVPD in getTypeBasedIntrinsicInstrCost()
[all …]
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| /freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/IR/ |
| D | ConstrainedOps.def | 85 DAG_FUNCTION(maxnum, 2, 0, experimental_constrained_maxnum, FMAXNUM)
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| /freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 899 FMAXNUM, enumerator
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| D | BasicTTIImpl.h | 1596 ISDs.push_back(ISD::FMAXNUM); in getTypeBasedIntrinsicInstrCost()
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| D | TargetLowering.h | 2461 case ISD::FMAXNUM: in isCommutativeBinOp()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCTargetTransformInfo.cpp | 510 case Intrinsic::maxnum: Opcode = ISD::FMAXNUM; break; in mightUseCTR()
627 Opcode = ISD::FMAXNUM; break; in mightUseCTR()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 409 case ISD::FMAXNUM: in LegalizeOp()
820 case ISD::FMAXNUM: in Expand()
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| D | SelectionDAGDumper.cpp | 186 case ISD::FMAXNUM: return "fmaxnum"; in getOperationName()
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| D | LegalizeFloatTypes.cpp | 74 case ISD::FMAXNUM: R = SoftenFloatRes_FMAXNUM(N); break; in SoftenFloatResult()
1198 case ISD::FMAXNUM: ExpandFloatRes_FMAXNUM(N, Lo, Hi); break; in ExpandFloatResult()
2256 case ISD::FMAXNUM: in PromoteFloatResult()
2621 case ISD::FMAXNUM: in SoftPromoteHalfResult()
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| D | SelectionDAGBuilder.cpp | 3312 case SPNB_RETURNS_OTHER: Opc = ISD::FMAXNUM; break; in visitSelect()
3315 if (TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT)) in visitSelect()
3316 Opc = ISD::FMAXNUM; in visitSelect()
3320 Opc = TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT.getScalarType()) ? in visitSelect()
3321 ISD::FMAXNUM : ISD::FMAXIMUM; in visitSelect()
6302 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl, in visitIntrinsicCall()
7975 if (visitBinaryFloatCall(I, ISD::FMAXNUM)) in visitCall()
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| D | LegalizeDAG.cpp | 3136 case ISD::FMAXNUM: { in ExpandNode()
3931 case ISD::FMAXNUM: in ConvertNodeToLibcall()
4667 case ISD::FMAXNUM: in PromoteNode()
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| D | LegalizeVectorTypes.cpp | 119 case ISD::FMAXNUM: in ScalarizeVectorResult()
1020 case ISD::FMAXNUM: in SplitVectorResult()
3023 case ISD::FMAXNUM: in WidenVectorResult()
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| D | SelectionDAG.cpp | 398 return ISD::FMAXNUM; in getVecReduceBaseOpcode()
4398 case ISD::FMAXNUM: { in isKnownNeverNaN()
10607 case ISD::FMAXNUM: { in getNeutralElement()
10613 if (Opcode == ISD::FMAXNUM) in getNeutralElement()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 499 setOperationAction(ISD::FMAXNUM, MVT::f32, Custom); in SITargetLowering()
501 setOperationAction(ISD::FMAXNUM, MVT::f64, Custom); in SITargetLowering()
692 setOperationAction(ISD::FMAXNUM, MVT::f16, Custom); in SITargetLowering()
701 setOperationAction(ISD::FMAXNUM, MVT::v4f16, Expand); in SITargetLowering()
757 setOperationAction(ISD::FMAXNUM, MVT::v2f16, Custom); in SITargetLowering()
761 setOperationAction(ISD::FMAXNUM, MVT::v4f16, Custom); in SITargetLowering()
844 setTargetDAGCombine(ISD::FMAXNUM); in SITargetLowering()
4593 case ISD::FMAXNUM: in LowerOperation()
6517 return DAG.getNode(ISD::FMAXNUM, DL, VT, Tmp, in LowerINTRINSIC_WO_CHAIN()
9544 case ISD::FMAXNUM: in isCanonicalized()
[all …]
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| D | AMDGPUISelLowering.cpp | 333 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal); in AMDGPUTargetLowering()
504 setOperationAction(ISD::FMAXNUM, VT, Expand); in AMDGPUTargetLowering()
639 case ISD::FMAXNUM: in fnegFoldsIntoOp()
3745 case ISD::FMAXNUM: in inverseMinMax()
3748 return ISD::FMAXNUM; in inverseMinMax()
3863 case ISD::FMAXNUM: in performFNegCombine()
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| D | AMDGPUISelDAGToDAG.cpp | 440 case ISD::FMAXNUM: in fp16SrcZerosHighBits()
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| /freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/Target/ |
| D | GenericOpcodes.td | 736 // FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two
759 // FMINNUM/FMAXNUM in the handling of signaling NaNs. If one input is a
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| D | TargetSelectionDAG.td | 466 def fmaxnum : SDNode<"ISD::FMAXNUM" , SDTFPBinOp,
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1645 ISD::FMINNUM, ISD::FMAXNUM, ISD::FSINCOS, in HexagonTargetLowering()
1765 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal); in HexagonTargetLowering()
1802 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal); in HexagonTargetLowering()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 316 setOperationAction(ISD::FMAXNUM, MVT::f16, Legal); in RISCVTargetLowering()
332 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal); in RISCVTargetLowering()
353 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal); in RISCVTargetLowering()
602 setOperationAction(ISD::FMAXNUM, VT, Legal); in RISCVTargetLowering()
811 setOperationAction(ISD::FMAXNUM, VT, Custom); in RISCVTargetLowering()
2616 case ISD::FMAXNUM: in LowerOperation()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 552 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal); in SystemZTargetLowering()
557 setOperationAction(ISD::FMAXNUM, MVT::v2f64, Legal); in SystemZTargetLowering()
562 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal); in SystemZTargetLowering()
567 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal); in SystemZTargetLowering()
572 setOperationAction(ISD::FMAXNUM, MVT::f128, Legal); in SystemZTargetLowering()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 765 setOperationAction(ISD::FMAXNUM, VT, Expand); in initActions()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 346 setOperationAction(ISD::FMAXNUM, VT, Legal); in addMVEVectorTypes()
756 setOperationAction(ISD::FMAXNUM, MVT::f16, Legal); in ARMTargetLowering()
1451 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal); in ARMTargetLowering()
1454 setOperationAction(ISD::FMAXNUM, MVT::v2f32, Legal); in ARMTargetLowering()
1456 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal); in ARMTargetLowering()
1467 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal); in ARMTargetLowering()
1507 setOperationAction(ISD::FMAXNUM, MVT::v4f16, Legal); in ARMTargetLowering()
1509 setOperationAction(ISD::FMAXNUM, MVT::v8f16, Legal); in ARMTargetLowering()
4083 ? ISD::FMINNUM : ISD::FMAXNUM; in LowerINTRINSIC_WO_CHAIN()
9938 case ISD::VECREDUCE_FMAX: BaseOpcode = ISD::FMAXNUM; break; in LowerVecReduce()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 557 ISD::FABS, ISD::FMINNUM, ISD::FMAXNUM}) { in NVPTXTargetLowering()
564 setOperationAction(ISD::FMAXNUM, MVT::f16, Promote); in NVPTXTargetLowering()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 635 setOperationAction(ISD::FMAXNUM, MVT::f16, Promote); in AArch64TargetLowering()
699 setOperationAction(ISD::FMAXNUM, Ty, Legal); in AArch64TargetLowering()
717 setOperationAction(ISD::FMAXNUM, MVT::f16, Legal); in AArch64TargetLowering()
1272 setOperationAction(ISD::FMAXNUM, VT, Custom); in AArch64TargetLowering()
1470 {ISD::FMINIMUM, ISD::FMAXIMUM, ISD::FMINNUM, ISD::FMAXNUM}) in addTypeForNEON()
1536 setOperationAction(ISD::FMAXNUM, VT, Custom); in addTypeForFixedLengthSVE()
4958 case ISD::FMAXNUM: in LowerOperation()
14362 return DAG.getNode(ISD::FMAXNUM, SDLoc(N), N->getValueType(0), in performIntrinsicCombine()
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