| /freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/IR/ |
| D | ConstrainedOps.def | 52 DAG_INSTRUCTION(FAdd, 2, 1, experimental_constrained_fadd, FADD)
100 // constrained FMA or FMUL + FADD intrinsics.
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 231 { ISD::FADD, MVT::v2f64, 2 }, // addpd in getArithmeticInstrCost()
631 { ISD::FADD, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
640 { ISD::FADD, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
817 { ISD::FADD, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ in getArithmeticInstrCost()
818 { ISD::FADD, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ in getArithmeticInstrCost()
898 { ISD::FADD, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
899 { ISD::FADD, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
900 { ISD::FADD, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
901 { ISD::FADD, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
976 { ISD::FADD, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ in getArithmeticInstrCost()
[all …]
|
| D | X86IntrinsicsInfo.h | 416 X86_INTRINSIC_DATA(avx512_add_pd_512, INTR_TYPE_2OP, ISD::FADD, X86ISD::FADD_RND),
417 X86_INTRINSIC_DATA(avx512_add_ps_512, INTR_TYPE_2OP, ISD::FADD, X86ISD::FADD_RND),
|
| /freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 377 FADD, enumerator
|
| D | TargetLowering.h | 2449 case ISD::FADD: in isCommutativeBinOp()
2735 assert((N->getOpcode() == ISD::FADD || N->getOpcode() == ISD::FSUB || in isFMADLegal()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.cpp | 4934 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, in getLimitedPrecisionExp2()
4937 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, in getLimitedPrecisionExp2()
4950 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, in getLimitedPrecisionExp2()
4953 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, in getLimitedPrecisionExp2()
4956 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, in getLimitedPrecisionExp2()
4971 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, in getLimitedPrecisionExp2()
4974 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, in getLimitedPrecisionExp2()
4977 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, in getLimitedPrecisionExp2()
4980 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, in getLimitedPrecisionExp2()
4983 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, in getLimitedPrecisionExp2()
[all …]
|
| D | LegalizeVectorOps.cpp | 374 case ISD::FADD: in LegalizeOp()
1328 DAG.getNode(ISD::FADD, DL, Node->getValueType(0), fHI, fLO)); in ExpandUINT_TO_FLOAT()
1349 TLI.isOperationLegalOrCustom(ISD::FADD, VT)) in ExpandFSUB()
|
| D | DAGCombiner.cpp | 1683 case ISD::FADD: return visitFADD(N); in visit()
13565 if (X.getOpcode() == ISD::FADD && (Aggressive || X->hasOneUse())) { in visitFMULForFMADistributiveCombine()
13640 return DAG.getNode(ISD::FADD, DL, VT, N0, N1); in visitFADD()
13644 return DAG.getNode(ISD::FADD, DL, VT, N1, N0); in visitFADD()
13677 SDValue Add = DAG.getNode(ISD::FADD, DL, VT, B, B); in visitFADD()
13683 SDValue Add = DAG.getNode(ISD::FADD, DL, VT, B, B); in visitFADD()
13709 if (N1CFP && N0.getOpcode() == ISD::FADD && in visitFADD()
13711 SDValue NewC = DAG.getNode(ISD::FADD, DL, VT, N0.getOperand(1), N1); in visitFADD()
13712 return DAG.getNode(ISD::FADD, DL, VT, N0.getOperand(0), NewC); in visitFADD()
13725 SDValue NewCFP = DAG.getNode(ISD::FADD, DL, VT, N0.getOperand(1), in visitFADD()
[all …]
|
| D | SelectionDAGBuilder.h | 690 void visitFAdd(const User &I) { visitBinary(I, ISD::FADD); } in visitFAdd()
|
| D | LegalizeFloatTypes.cpp | 76 case ISD::FADD: R = SoftenFloatRes_FADD(N); break; in SoftenFloatResult()
1200 case ISD::FADD: ExpandFloatRes_FADD(N, Lo, Hi); break; in ExpandFloatResult()
1737 Lo = DAG.getNode(ISD::FADD, dl, VT, Hi, NewLo); in ExpandFloatRes_XINT_TO_FP()
2252 case ISD::FADD: in PromoteFloatResult()
2617 case ISD::FADD: in SoftPromoteHalfResult()
|
| D | LegalizeDAG.cpp | 2413 Slow = DAG.getNode(ISD::FADD, dl, DestVT, SignCvt, SignCvt); in ExpandLegalINT_TO_FP()
2422 Node->isStrictFPOpcode() ? ISD::STRICT_FADD : ISD::FADD, DestVT)) in ExpandLegalINT_TO_FP()
2491 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg); in ExpandLegalINT_TO_FP()
3218 if (TLI.isOperationLegalOrCustom(ISD::FADD, VT) && in ExpandNode()
3222 Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1, Flags); in ExpandNode()
4116 case ISD::FADD: in ConvertNodeToLibcall()
4661 case ISD::FADD: in PromoteNode()
|
| D | SelectionDAGDumper.cpp | 254 case ISD::FADD: return "fadd"; in getOperationName()
|
| D | SelectionDAG.cpp | 375 return ISD::FADD; in getVecReduceBaseOpcode()
4335 case ISD::FADD: in isKnownNeverNaN()
5456 case ISD::FADD: in foldConstantFPMath()
5494 case ISD::FADD: in foldConstantFPMath()
5664 case ISD::FADD: in getNode()
7883 if (Opcode == ISD::FADD) in simplifyFPBinop()
9909 case ISD::FADD: in matchBinOpReduction()
10602 case ISD::FADD: in getNeutralElement()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 505 setOperationAction(ISD::FADD, VT, Expand); in AMDGPUTargetLowering()
606 setTargetDAGCombine(ISD::FADD); in AMDGPUTargetLowering()
633 case ISD::FADD: in fnegFoldsIntoOp()
2189 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add); in LowerFCEIL()
2268 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign); in LowerFRINT()
2321 return DAG.getNode(ISD::FADD, SL, VT, T, Sel); in LowerFROUND()
2346 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add); in LowerFFLOOR()
2559 return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo); in LowerINT_TO_FP64()
3787 case ISD::FADD: { in performFNegCombine()
3805 SDValue Res = DAG.getNode(ISD::FADD, SL, VT, LHS, RHS, N0->getFlags()); in performFNegCombine()
[all …]
|
| D | AMDGPUTargetTransformInfo.cpp | 629 if (OPC == ISD::FADD || OPC == ISD::FSUB) { in getArithmeticInstrCost()
644 case ISD::FADD: in getArithmeticInstrCost()
|
| D | SIISelLowering.cpp | 721 setOperationAction(ISD::FADD, MVT::v2f16, Legal); in SITargetLowering()
753 setOperationAction(ISD::FADD, MVT::v4f16, Custom); in SITargetLowering()
769 setOperationAction(ISD::FADD, MVT::v2f32, Legal); in SITargetLowering()
775 setOperationAction(ISD::FADD, VT, Custom); in SITargetLowering()
841 setTargetDAGCombine(ISD::FADD); in SITargetLowering()
4610 case ISD::FADD: in LowerOperation()
9500 case ISD::FADD: in isCanonicalized()
10139 case ISD::FADD: in performExtractVectorEltCombine()
10486 if (LHS.getOpcode() == ISD::FADD) { in performFAddCombine()
10498 if (RHS.getOpcode() == ISD::FADD) { in performFAddCombine()
[all …]
|
| D | R600ISelLowering.cpp | 743 DAG.getNode(ISD::FADD, DL, VT, in LowerTrig()
759 DAG.getNode(ISD::FADD, DL, VT, FractPart, in LowerTrig()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 504 setTargetDAGCombine(ISD::FADD); in NVPTXTargetLowering()
521 for (const auto &Op : {ISD::FADD, ISD::FMUL, ISD::FSUB, ISD::FMA}) { in NVPTXTargetLowering()
2098 SDValue AdjustedA = DAG.getNode(ISD::FADD, SL, VT, A, PointFiveWithSign); in LowerFROUND32()
2129 SDValue AdjustedA = DAG.getNode(ISD::FADD, SL, VT, AbsA, in LowerFROUND64()
4449 if (User->getOpcode() != ISD::FADD) in PerformADDCombineWithOperands()
4820 case ISD::FADD: in PerformDAGCombine()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64SchedFalkorDetails.td | 595 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(FABD|FADD|FSUB)v2f32$")>;
622 def : InstRW<[FalkorWr_2VXVY_3cyc], (instregex "^(FABD|FADD(P)?|FSUB)(v2f64|v4f32)$")>;
1126 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(FADD|FSUB)(S|D)rr$")>;
|
| D | AArch64SchedA57.td | 443 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FABD|FADD|FSUB)(v2f32|32|64|v2i32p)")>;
445 def : InstRW<[A57Write_5cyc_2V], (instregex "^(FABD|FADD|FSUB)(v4f32|v2f64|v2i64p)")>;
|
| D | AArch64TargetTransformInfo.cpp | 1395 case ISD::FADD: in getArithmeticInstrCost()
1945 case ISD::FADD: in getArithmeticReductionCostSVE()
|
| D | AArch64SchedKryoDetails.td | 639 (instregex "(FABD|FADD|FSUB|FADDP)(v4f32|v2f64)")>;
669 (instregex "(FADD|FSUB)(D|S)rr")>;
675 (instregex "(FADD|FSUB|FADDP)v2f32")>;
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| D | MicroMipsInstrFPU.td | 34 defm FADD : ADDS_MMM<"add.d", II_ADD_D, 1, fadd>,
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| D | P9InstrResources.td | 414 (instregex "FADD(S)?$"),
474 (instregex "FADD(S)?_rec$"),
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1640 ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FMA, ISD::FDIV, in HexagonTargetLowering()
1760 setOperationAction(ISD::FADD, MVT::f64, Expand); in HexagonTargetLowering()
1797 setOperationAction(ISD::FADD, MVT::f64, Legal); in HexagonTargetLowering()
|