Searched refs:ExtractVT (Results 1 – 3 of 3) sorted by relevance
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 18279 MVT ExtractVT = MVT::getVectorVT(MVT::i1, SubvecElts); in lower1BitShuffle() local
18280 SDValue Extract = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ExtractVT, in lower1BitShuffle()
40519 EVT ExtractVT = Extract->getValueType(0); in combineMinMaxReduction() local
40520 if (ExtractVT != MVT::i16 && ExtractVT != MVT::i8) in combineMinMaxReduction()
40532 if (SrcSVT != ExtractVT || (SrcVT.getSizeInBits() % 128) != 0) in combineMinMaxReduction()
40545 assert(((SrcVT == MVT::v8i16 && ExtractVT == MVT::i16) || in combineMinMaxReduction()
40546 (SrcVT == MVT::v16i8 && ExtractVT == MVT::i8)) && in combineMinMaxReduction()
40552 unsigned MaskEltsBits = ExtractVT.getSizeInBits(); in combineMinMaxReduction()
40567 if (ExtractVT == MVT::i8) { in combineMinMaxReduction()
40582 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ExtractVT, MinPos, in combineMinMaxReduction()
[all …]
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 20526 EVT ExtractVT = in visitEXTRACT_SUBVECTOR() local
20531 TLI.isOperationLegal(ISD::BUILD_VECTOR, ExtractVT))) && in visitEXTRACT_SUBVECTOR()
20532 (!LegalTypes || TLI.isTypeLegal(ExtractVT))) { in visitEXTRACT_SUBVECTOR()
20543 SDValue BuildVec = DAG.getBuildVector(ExtractVT, SDLoc(N), in visitEXTRACT_SUBVECTOR()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 15431 EVT ExtractVT = VT.getVectorElementType(); in PerformVDUPLANECombine() local
15433 if (!DCI.DAG.getTargetLoweringInfo().isTypeLegal(ExtractVT)) in PerformVDUPLANECombine()
15434 ExtractVT = MVT::i32; in PerformVDUPLANECombine()
15435 SDValue Extract = DCI.DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), ExtractVT, in PerformVDUPLANECombine()
|