Searched refs:ExecReg (Results 1 – 6 of 6) sorted by relevance
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIOptimizeExecMaskingPreRA.cpp | 40 MCRegister ExecReg; member in __anon4e7df3810111::SIOptimizeExecMaskingPreRA
141 if (CmpReg == Register(ExecReg)) { in optimizeVcndVcmpPair()
145 } else if (And->getOperand(2).getReg() != Register(ExecReg)) { in optimizeVcndVcmpPair()
192 .addReg(ExecReg) in optimizeVcndVcmpPair()
260 if (XorTermMI.getOperand(1).getReg() != Register(ExecReg)) in optimizeElseBranch()
271 I->getOperand(1).getReg() == Register(ExecReg)) in optimizeElseBranch()
284 for (MCRegUnitIterator UI(ExecReg, TRI); UI.isValid(); ++UI) { in optimizeElseBranch()
321 ExecReg = MCRegister::from(Wave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC); in runOnMachineFunction()
415 if (!(I->isFullCopy() && I->getOperand(1).getReg() == Register(ExecReg))) in runOnMachineFunction()
429 MRI->replaceRegWith(SavedExec, ExecReg); in runOnMachineFunction()
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| D | SIPreEmitPeephole.cpp | 82 const unsigned ExecReg = IsWave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in optimizeVccBranch() local
94 if (A->modifiesRegister(ExecReg, TRI)) in optimizeVccBranch()
109 if (Op1.getReg() != ExecReg && Op2.isReg() && Op2.getReg() == ExecReg) { in optimizeVccBranch()
113 if (Op1.getReg() != ExecReg) in optimizeVccBranch()
160 .addReg(ExecReg); in optimizeVccBranch()
168 if (SReg == ExecReg) { in optimizeVccBranch()
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| D | SILowerI1Copies.cpp | 55 unsigned ExecReg; member in __anon3eadb5ad0111::SILowerI1Copies
459 ExecReg = AMDGPU::EXEC_LO; in runOnMachineFunction()
467 ExecReg = AMDGPU::EXEC; in runOnMachineFunction()
828 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg).addReg(ExecReg); in buildMergeLaneMasks()
831 .addReg(ExecReg) in buildMergeLaneMasks()
846 .addReg(ExecReg); in buildMergeLaneMasks()
857 .addReg(ExecReg); in buildMergeLaneMasks()
870 .addReg(ExecReg); in buildMergeLaneMasks()
874 .addReg(CurMaskedReg ? CurMaskedReg : ExecReg); in buildMergeLaneMasks()
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| D | SILateBranchLowering.cpp | 39 Register ExecReg; member in __anon3f52b5e20111::SILateBranchLowering
136 ExecReg = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in runOnMachineFunction()
180 ExecReg) in runOnMachineFunction()
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| D | SIRegisterInfo.cpp | 106 Register ExecReg; member
123 ExecReg = AMDGPU::EXEC_LO; in SGPRSpillBuilder()
127 ExecReg = AMDGPU::EXEC; in SGPRSpillBuilder()
192 BuildMI(MBB, MI, DL, TII.get(MovOpc), SavedExecReg).addReg(ExecReg); in prepare()
193 auto I = BuildMI(MBB, MI, DL, TII.get(MovOpc), ExecReg).addImm(VGPRLanes); in prepare()
204 auto I = BuildMI(MBB, MI, DL, TII.get(NotOpc), ExecReg).addReg(ExecReg); in prepare()
227 auto I = BuildMI(MBB, MI, DL, TII.get(MovOpc), ExecReg) in restore()
238 auto I = BuildMI(MBB, MI, DL, TII.get(NotOpc), ExecReg).addReg(ExecReg); in restore()
264 BuildMI(MBB, MI, DL, TII.get(NotOpc), ExecReg).addReg(ExecReg); in readWriteTmpVGPR()
266 BuildMI(MBB, MI, DL, TII.get(NotOpc), ExecReg).addReg(ExecReg); in readWriteTmpVGPR()
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| D | AMDGPURegisterBankInfo.cpp | 730 const unsigned ExecReg = Subtarget.isWave32() ? in executeInWaterfallLoop() local
1012 .addDef(ExecReg) in executeInWaterfallLoop()
1013 .addReg(ExecReg) in executeInWaterfallLoop()
1025 .addReg(ExecReg); in executeInWaterfallLoop()
1030 .addDef(ExecReg) in executeInWaterfallLoop()
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