Searched refs:DispatchWidth (Results 1 – 10 of 10) sorted by relevance
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/MCA/Stages/ |
| D | DispatchStage.cpp | 32 : DispatchWidth(MaxDispatchWidth), AvailableEntries(MaxDispatchWidth), in DispatchStage()
34 if (!DispatchWidth) in DispatchStage()
35 DispatchWidth = Subtarget.getSchedModel().IssueWidth; in DispatchStage()
83 if (NumMicroOps > DispatchWidth) { in dispatch()
84 assert(AvailableEntries == DispatchWidth); in dispatch()
86 CarryOver = NumMicroOps - DispatchWidth; in dispatch()
131 std::min(DispatchWidth, NumMicroOps)); in dispatch()
139 AvailableEntries = DispatchWidth; in cycleStart()
143 AvailableEntries = CarryOver >= DispatchWidth ? 0 : DispatchWidth - CarryOver; in cycleStart()
144 unsigned DispatchedOpcodes = DispatchWidth - AvailableEntries; in cycleStart()
[all …]
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| /freebsd-12-stable/contrib/llvm-project/llvm/tools/llvm-mca/Views/ |
| D | SummaryView.cpp | 27 : SM(Model), Source(S), DispatchWidth(Width ? Width : Model.IssueWidth), in SummaryView()
74 TempStream << "\nDispatch Width: " << DV.DispatchWidth; in printView()
91 DV.DispatchWidth = DispatchWidth; in collectData()
95 DV.BlockRThroughput = computeBlockRThroughput(SM, DispatchWidth, NumMicroOps, in collectData()
106 {"DispatchWidth", DV.DispatchWidth}, in toJSON()
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| D | SummaryView.h | 43 const unsigned DispatchWidth; variable
54 unsigned DispatchWidth; member
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| /freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/MCA/ |
| D | Context.h | 38 DispatchWidth(DW), RegisterFileSize(RFS), LoadQueueSize(LQS), in MicroOpQueueSize()
43 unsigned DispatchWidth; member
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| D | Support.h | 109 double computeBlockRThroughput(const MCSchedModel &SM, unsigned DispatchWidth,
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/MCA/ |
| D | Support.cpp | 82 double computeBlockRThroughput(const MCSchedModel &SM, unsigned DispatchWidth, in computeBlockRThroughput() argument
88 double Max = static_cast<double>(NumMicroOps) / DispatchWidth; in computeBlockRThroughput()
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| D | Context.cpp | 49 std::make_unique<DispatchStage>(STI, MRI, Opts.DispatchWidth, *RCU, *PRF); in createDefaultPipeline()
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| /freebsd-12-stable/contrib/llvm-project/llvm/tools/llvm-mca/ |
| D | PipelinePrinter.cpp | 69 if (PO.DispatchWidth) in getJSONSimulationParameters()
70 SimParameters.try_emplace("-dispatch", PO.DispatchWidth); in getJSONSimulationParameters()
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| D | llvm-mca.cpp | 120 DispatchWidth("dispatch", cl::desc("Override the processor dispatch width"), variable
509 mca::PipelineOptions PO(MicroOpQueue, DecoderThroughput, DispatchWidth, in main()
622 std::make_unique<mca::SummaryView>(SM, Insts, DispatchWidth)); in main()
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| /freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/MCA/Stages/ |
| D | DispatchStage.h | 50 unsigned DispatchWidth; variable
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