Searched refs:DPLL (Results 1 – 6 of 6) sorted by relevance
15 #define DPLL 3 macro
97 /* derived from 600MHz DPLL */199 /* derived from 600MHz DPLL */235 /* derived from 600MHz DPLL */247 /* derived from 600MHz DPLL */262 /* derived from 600MHz DPLL */
216 * Fix the emac parent clock is DPLL instead of APLL.
1055 reg = DPLL(pipe); in assert_pll()1455 reg = DPLL(pipe); in intel_enable_pll()1492 reg = DPLL(pipe); in intel_disable_pll()4379 I915_WRITE(DPLL(pipe), dpll); in vlv_update_pll()4380 POSTING_READ(DPLL(pipe)); in vlv_update_pll()4411 I915_WRITE(DPLL(pipe), dpll); in vlv_update_pll()4412 POSTING_READ(DPLL(pipe)); in vlv_update_pll()4413 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) in vlv_update_pll()4421 I915_WRITE(DPLL(pipe), dpll); in vlv_update_pll()4424 POSTING_READ(DPLL(pipe)); in vlv_update_pll()[all …]
258 int dpll_reg = DPLL(pipe); in intel_dvo_mode_set()
929 #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B) macro