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Searched refs:DMA0_REGISTER_OFFSET (Results 1 – 4 of 4) sorted by relevance

/freebsd-12-stable/sys/dev/drm2/radeon/
Dni.c673 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); in cayman_gpu_init()
1265 rb_cntl = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in cayman_dma_stop()
1267 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, rb_cntl); in cayman_dma_stop()
1303 reg_offset = DMA0_REGISTER_OFFSET; in cayman_dma_resume()
1462 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in cayman_gpu_soft_reset_dma()
1464 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); in cayman_gpu_soft_reset_dma()
1545 dma_status_reg = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET); in cayman_dma_is_lockup()
1667 DMA_RB_RPTR + DMA0_REGISTER_OFFSET, in cayman_startup()
1668 DMA_RB_WPTR + DMA0_REGISTER_OFFSET, in cayman_startup()
Dsi.c1716 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); in si_gpu_init()
2248 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in si_gpu_soft_reset_dma()
2250 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); in si_gpu_soft_reset_dma()
3311 tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_disable_interrupt_state()
3312 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, tmp); in si_disable_interrupt_state()
3455 dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_irq_set()
3539 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, dma_cntl); in si_irq_set()
4223 DMA_RB_RPTR + DMA0_REGISTER_OFFSET, in si_startup()
4224 DMA_RB_WPTR + DMA0_REGISTER_OFFSET, in si_startup()
Dnid.h628 #define DMA0_REGISTER_OFFSET 0x0 /* not a register */ macro
Dsid.h1009 #define DMA0_REGISTER_OFFSET 0x0 /* not a register */ macro