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Searched refs:CSR_READ_4 (Results 1 – 25 of 90) sorted by relevance

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/freebsd-12-stable/sys/arm/amlogic/aml8726/
Daml8726_rtc.c125 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], reg) macro
135 CSR_WRITE_4(sc, AML_RTC_0_REG, (CSR_READ_4(sc, AML_RTC_0_REG) & in aml8726_rtc_start_transfer()
143 if ( (CSR_READ_4(sc, AML_RTC_1_REG) & AML_RTC_SRDY) ) in aml8726_rtc_start_transfer()
151 CSR_WRITE_4(sc, AML_RTC_0_REG, (CSR_READ_4(sc, AML_RTC_0_REG) | in aml8726_rtc_start_transfer()
163 CSR_WRITE_4(sc, AML_RTC_0_REG, (CSR_READ_4(sc, AML_RTC_0_REG) | in aml8726_rtc_sclk_pulse()
170 CSR_WRITE_4(sc, AML_RTC_0_REG, (CSR_READ_4(sc, AML_RTC_0_REG) & in aml8726_rtc_sclk_pulse()
181 CSR_WRITE_4(sc, AML_RTC_0_REG, (CSR_READ_4(sc, AML_RTC_0_REG) | in aml8726_rtc_send_bit()
184 CSR_WRITE_4(sc, AML_RTC_0_REG, (CSR_READ_4(sc, AML_RTC_0_REG) & in aml8726_rtc_send_bit()
200 (CSR_READ_4(sc, AML_RTC_0_REG) & ~AML_RTC_SEN)); in aml8726_rtc_send_addr()
226 data |= (CSR_READ_4(sc, AML_RTC_1_REG) & AML_RTC_SDO) ? 1 : 0; in aml8726_rtc_recv_data()
[all …]
Daml8726_i2c.c86 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], reg) macro
193 (CSR_READ_4(sc, AML_I2C_CTRL_REG) | AML_I2C_MANUAL_SDA_O | in aml8726_iic_reset()
209 return (CSR_READ_4(sc, AML_I2C_CTRL_REG) & AML_I2C_MANUAL_SCL_I); in aml8726_iic_getscl()
217 return (CSR_READ_4(sc, AML_I2C_CTRL_REG) & AML_I2C_MANUAL_SDA_I); in aml8726_iic_getsda()
227 CSR_WRITE_4(sc, AML_I2C_CTRL_REG, ((CSR_READ_4(sc, AML_I2C_CTRL_REG) & in aml8726_iic_setscl()
241 CSR_WRITE_4(sc, AML_I2C_CTRL_REG, ((CSR_READ_4(sc, AML_I2C_CTRL_REG) & in aml8726_iic_setsda()
Daml8726_timer.c130 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], reg) macro
138 return CSR_READ_4(sc, AML_TIMER_E_REG); in aml8726_get_timecount()
153 (CSR_READ_4(sc, AML_TIMER_MUX_REG) | in aml8726_hardclock()
197 ((CSR_READ_4(sc, AML_TIMER_MUX_REG) & ~AML_TIMER_A_PERIODIC) | in aml8726_timer_start()
214 (CSR_READ_4(sc, AML_TIMER_MUX_REG) & ~AML_TIMER_A_EN)); in aml8726_timer_stop()
257 ((CSR_READ_4(sc, AML_TIMER_MUX_REG) & in aml8726_timer_attach()
266 (CSR_READ_4(sc, AML_TIMER_MUX_REG) | AML_TIMER_E_EN)); in aml8726_timer_attach()
Daml8726_gpio.c87 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[reg], 0) macro
223 if ((CSR_READ_4(sc, AML_GPIO_OE_N_REG) & mask) == 0) { in aml8726_gpio_pin_getflags()
248 (CSR_READ_4(sc, AML_GPIO_OE_N_REG) & ~mask)); in aml8726_gpio_pin_setflags()
252 (CSR_READ_4(sc, AML_GPIO_OE_N_REG) | mask)); in aml8726_gpio_pin_setflags()
281 ((CSR_READ_4(sc, AML_GPIO_OUT_REG) & ~mask) | (value << pin))); in aml8726_gpio_pin_set()
298 *value = (CSR_READ_4(sc, AML_GPIO_IN_REG) & mask) ? 1 : 0; in aml8726_gpio_pin_get()
324 CSR_READ_4(sc, AML_GPIO_OUT_REG) ^ mask); in aml8726_gpio_pin_toggle()
Daml8726_usb_phy-m6.c100 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], reg) macro
227 value = CSR_READ_4(sc, AML_USB_PHY_CFG_REG); in aml8726_usb_phy_attach()
256 value = CSR_READ_4(sc, AML_USB_PHY_CTRL_REG); in aml8726_usb_phy_attach()
293 value = CSR_READ_4(sc, AML_USB_PHY_CTRL_REG); in aml8726_usb_phy_attach()
302 value = CSR_READ_4(sc, AML_USB_PHY_ADP_BC_REG); in aml8726_usb_phy_attach()
312 value = CSR_READ_4(sc, AML_USB_PHY_ADP_BC_REG); in aml8726_usb_phy_attach()
377 value = CSR_READ_4(sc, AML_USB_PHY_CTRL_REG); in aml8726_usb_phy_detach()
Daml8726_usb_phy-m3.c104 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], reg) macro
244 value = CSR_READ_4(sc, AML_USB_PHY_CFG_REG); in aml8726_usb_phy_attach()
329 value = CSR_READ_4(sc, AML_USB_PHY_CFG_REG); in aml8726_usb_phy_attach()
338 value = CSR_READ_4(sc, AML_USB_PHY_MISC_A_REG); in aml8726_usb_phy_attach()
347 value = CSR_READ_4(sc, AML_USB_PHY_MISC_B_REG); in aml8726_usb_phy_attach()
387 value = CSR_READ_4(sc, AML_USB_PHY_CFG_REG); in aml8726_usb_phy_detach()
Daml8726_pic.c111 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], reg) macro
227 value = CSR_READ_4(aml8726_pic_sc, AML_PIC_STAT_REG(irq)); in arm_get_next_irq()
252 mask = CSR_READ_4(aml8726_pic_sc, AML_PIC_MASK_REG(nb)); in arm_mask_irq()
271 mask = CSR_READ_4(aml8726_pic_sc, AML_PIC_MASK_REG(nb)); in arm_unmask_irq()
Daml8726_rng.c67 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], reg) macro
75 rn[0] = CSR_READ_4(sc, AML_RNG_0_REG); in aml8726_rng_harvest()
76 rn[1] = CSR_READ_4(sc, AML_RNG_1_REG); in aml8726_rng_harvest()
Daml8726_sdxc-m8.c152 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], reg) macro
231 pdmar = CSR_READ_4(sc, AML_SDXC_PDMA_REG); in aml8726_sdxc_engage_dma()
255 sr = CSR_READ_4(sc, AML_SDXC_STATUS_REG); in aml8726_sdxc_engage_dma()
278 pdmar = CSR_READ_4(sc, AML_SDXC_PDMA_REG); in aml8726_sdxc_disengage_dma()
296 sr = CSR_READ_4(sc, AML_SDXC_STATUS_REG); in aml8726_sdxc_disengage_dma()
359 ctlr = CSR_READ_4(sc, AML_SDXC_CNTRL_REG); in aml8726_sdxc_start_command()
530 while ((CSR_READ_4(sc, AML_SDXC_STATUS_REG) & in aml8726_sdxc_timeout()
545 sr = CSR_READ_4(sc, AML_SDXC_STATUS_REG); in aml8726_sdxc_busy_check()
577 isr = CSR_READ_4(sc, AML_SDXC_IRQ_STATUS_REG); in aml8726_sdxc_intr()
578 sndr = CSR_READ_4(sc, AML_SDXC_SEND_REG); in aml8726_sdxc_intr()
[all …]
Daml8726_wdt.c100 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], reg) macro
128 (CSR_READ_4(sc, AML_WDT_CTRL_REG) & in aml8726_wdt_watchdog()
149 (CSR_READ_4(sc, AML_WDT_CTRL_REG) & ~(AML_WDT_CTRL_IRQ_EN | in aml8726_wdt_intr()
240 (CSR_READ_4(sc, AML_WDT_CTRL_REG) & ~(AML_WDT_CTRL_IRQ_EN | in aml8726_wdt_attach()
/freebsd-12-stable/sys/mips/ingenic/
Djz4780_clock.c500 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], (reg)) macro
579 *val = CSR_READ_4(sc, addr); in jz4780_clock_read_4()
591 val = CSR_READ_4(sc, addr); in jz4780_clock_modify_4()
687 reg = CSR_READ_4(sc, JZ_OPCR); in jz4780_ohci_enable()
718 reg = CSR_READ_4(sc, JZ_USBPCR); in jz4780_ehci_enable()
723 reg = CSR_READ_4(sc, JZ_OPCR); in jz4780_ehci_enable()
728 reg = CSR_READ_4(sc, JZ_USBPCR1); in jz4780_ehci_enable()
733 reg = CSR_READ_4(sc, JZ_USBPCR1); in jz4780_ehci_enable()
738 reg = CSR_READ_4(sc, JZ_USBPCR1); in jz4780_ehci_enable()
743 reg = CSR_READ_4(sc, JZ_USBPCR); in jz4780_ehci_enable()
[all …]
Djz4780_efuse.c75 #define CSR_READ_4(sc, reg) \ macro
104 while ((CSR_READ_4(sc, JZ_EFUSTATE) & JZ_EFUSE_RD_DONE) == 0) in jz4780_efuse_read_chunk()
111 abuf = CSR_READ_4(sc, JZ_EFUDATA0 + i); in jz4780_efuse_read_chunk()
118 abuf = CSR_READ_4(sc, JZ_EFUDATA0 + i); in jz4780_efuse_read_chunk()
Djz4780_gpio.c110 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], (reg)) macro
240 val = CSR_READ_4(sc, JZ_GPIO_INT); in jz4780_gpio_pin_probe()
243 val = CSR_READ_4(sc, JZ_GPIO_PAT1); in jz4780_gpio_pin_probe()
249 val = CSR_READ_4(sc, JZ_GPIO_PAT0); in jz4780_gpio_pin_probe()
260 val = CSR_READ_4(sc, JZ_GPIO_MASK); in jz4780_gpio_pin_probe()
263 val = CSR_READ_4(sc, JZ_GPIO_PAT1); in jz4780_gpio_pin_probe()
269 val = CSR_READ_4(sc, JZ_GPIO_DPULL); in jz4780_gpio_pin_probe()
277 val = CSR_READ_4(sc, JZ_GPIO_DPULL); in jz4780_gpio_pin_probe()
281 val = ((CSR_READ_4(sc, JZ_GPIO_PAT1) & mask) >> pin) << 1; in jz4780_gpio_pin_probe()
282 val = val | ((CSR_READ_4(sc, JZ_GPIO_PAT1) & mask) >> pin); in jz4780_gpio_pin_probe()
[all …]
/freebsd-12-stable/sys/dev/bge/
Dif_bge.c676 CSR_READ_4(sc, off); in bge_writembx()
1018 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) in bge_nvram_getbyte()
1026 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); in bge_nvram_getbyte()
1033 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { in bge_nvram_getbyte()
1045 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); in bge_nvram_getbyte()
1054 CSR_READ_4(sc, BGE_NVRAM_SWARB); in bge_nvram_getbyte()
1110 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) in bge_eeprom_getbyte()
1120 byte = CSR_READ_4(sc, BGE_EE_DATA); in bge_eeprom_getbyte()
1171 val = CSR_READ_4(sc, BGE_MI_COMM); in bge_miibus_readreg()
1174 val = CSR_READ_4(sc, BGE_MI_COMM); in bge_miibus_readreg()
[all …]
/freebsd-12-stable/sys/dev/et/
Dif_et.c442 val = CSR_READ_4(sc, ET_MII_IND); in et_miibus_readreg()
456 val = CSR_READ_4(sc, ET_MII_STAT); in et_miibus_readreg()
487 val = CSR_READ_4(sc, ET_MII_IND); in et_miibus_writereg()
542 ctrl = CSR_READ_4(sc, ET_MAC_CTRL); in et_miibus_statchg()
544 cfg1 = CSR_READ_4(sc, ET_MAC_CFG1); in et_miibus_statchg()
547 cfg2 = CSR_READ_4(sc, ET_MAC_CFG2); in et_miibus_statchg()
591 cfg1 = CSR_READ_4(sc, ET_MAC_CFG1); in et_miibus_statchg()
664 CSR_WRITE_4(sc, ET_MAC_CFG1, CSR_READ_4(sc, ET_MAC_CFG1) & ~( in et_stop()
1193 status = CSR_READ_4(sc, ET_INTR_STATUS); in et_intr()
1488 if ((CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) == 0) { in et_stop_rxdma()
[all …]
/freebsd-12-stable/sys/dev/alc/
Dif_alc.c306 v = CSR_READ_4(sc, ALC_MDIO); in alc_mii_readreg_813x()
333 v = CSR_READ_4(sc, ALC_MDIO); in alc_mii_readreg_816x()
371 v = CSR_READ_4(sc, ALC_MDIO); in alc_mii_writereg_813x()
397 v = CSR_READ_4(sc, ALC_MDIO); in alc_mii_writereg_816x()
448 reg = CSR_READ_4(sc, ALC_MAC_CFG); in alc_miibus_statchg()
492 v = CSR_READ_4(sc, ALC_MDIO); in alc_miiext_readreg()
523 v = CSR_READ_4(sc, ALC_MDIO); in alc_miiext_writereg()
706 opt = CSR_READ_4(sc, ALC_OPT_CFG); in alc_get_macaddr_813x()
707 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && in alc_get_macaddr_813x()
708 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { in alc_get_macaddr_813x()
[all …]
/freebsd-12-stable/sys/dev/dc/
Ddcphy.c77 CSR_READ_4(sc, reg) | x)
81 CSR_READ_4(sc, reg) & ~x)
210 mode = CSR_READ_4(dc_sc, DC_NETCFG); in dcphy_service()
265 reg = CSR_READ_4(dc_sc, DC_10BTSTAT); in dcphy_service()
311 tstat = CSR_READ_4(dc_sc, DC_10BTSTAT); in dcphy_status()
315 if (CSR_READ_4(dc_sc, DC_10BTCTRL) & DC_TCTL_AUTONEGENBL) { in dcphy_status()
368 if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_SPEEDSEL) in dcphy_status()
372 if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_FULLDUPLEX) in dcphy_status()
/freebsd-12-stable/sys/dev/nge/
Dif_nge.c250 CSR_READ_4(sc, reg) | (x))
254 CSR_READ_4(sc, reg) & ~(x))
257 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x))
260 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x))
268 CSR_READ_4(sc, NGE_CSR); in nge_delay()
352 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT) in nge_eeprom_getword()
392 val = CSR_READ_4(sc, NGE_MEAR); in nge_mii_bitbang_read()
432 reg = CSR_READ_4(sc, NGE_TBI_BMSR); in nge_miibus_readreg()
458 return (CSR_READ_4(sc, reg)); in nge_miibus_readreg()
592 reg = CSR_READ_4(sc, NGE_CFG); in nge_miibus_statchg()
[all …]
/freebsd-12-stable/sys/dev/bfe/
Dif_bfe.c675 val = CSR_READ_4(sc, BFE_TX_CTRL); in bfe_miibus_statchg()
681 flow = CSR_READ_4(sc, BFE_RXCONF); in bfe_miibus_statchg()
691 flow = CSR_READ_4(sc, BFE_MAC_FLOW); in bfe_miibus_statchg()
870 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; in bfe_pci_setup()
872 val = CSR_READ_4(sc, BFE_SBINTVEC); in bfe_pci_setup()
876 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); in bfe_pci_setup()
892 CSR_READ_4(sc, reg); in bfe_clear_stats()
894 CSR_READ_4(sc, reg); in bfe_clear_stats()
918 CSR_READ_4(sc, BFE_IMASK); in bfe_chip_halt()
939 val = CSR_READ_4(sc, BFE_SBTMSLOW) & in bfe_chip_reset()
[all …]
/freebsd-12-stable/sys/dev/jme/
Dif_jme.c233 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0) in jme_miibus_readreg()
265 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0) in jme_miibus_writereg()
361 reg = CSR_READ_4(sc, JME_SMBCSR); in jme_eeprom_read_byte()
376 reg = CSR_READ_4(sc, JME_SMBINTF); in jme_eeprom_read_byte()
386 reg = CSR_READ_4(sc, JME_SMBINTF); in jme_eeprom_read_byte()
494 par0 = CSR_READ_4(sc, JME_PAR0); in jme_reg_macaddr()
495 par1 = CSR_READ_4(sc, JME_PAR1); in jme_reg_macaddr()
713 reg = CSR_READ_4(sc, JME_CHIPMODE); in jme_attach()
756 reg = CSR_READ_4(sc, JME_SMBCSR); in jme_attach()
772 sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) & in jme_attach()
[all …]
/freebsd-12-stable/sys/dev/sis/
Dif_sis.c122 #define CSR_READ_4(sc, reg) bus_read_4(sc->sis_res[0], reg) macro
198 CSR_READ_4(sc, reg) | (x))
202 CSR_READ_4(sc, reg) & ~(x))
205 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x)
208 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x)
231 CSR_READ_4(sc, SIS_CSR); in sis_delay()
315 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) in sis_eeprom_getword()
417 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); in sis_read_mac()
418 csrsave = CSR_READ_4(sc, SIS_CSR); in sis_read_mac()
448 val = CSR_READ_4(sc, SIS_EECTL); in sis_mii_bitbang_read()
[all …]
/freebsd-12-stable/sys/dev/bwi/
Dbwimac.c200 return CSR_READ_4(sc, BWI_MOBJ_DATA); in bwi_memobj_read_4()
249 CSR_READ_4(mac->mac_sc, BWI_STATE_HI); /* dummy read */ in bwi_mac_lateattach()
464 state_lo = CSR_READ_4(sc, BWI_STATE_LO); in bwi_mac_reset()
470 CSR_READ_4(sc, BWI_STATE_LO); in bwi_mac_reset()
476 CSR_READ_4(sc, BWI_STATE_LO); in bwi_mac_reset()
481 status = CSR_READ_4(sc, BWI_MAC_STATUS); in bwi_mac_reset()
571 val = CSR_READ_4(sc, BWI_MAC_STATUS); in bwi_mac_test()
578 val = CSR_READ_4(sc, BWI_MAC_INTR_STATUS); in bwi_mac_test()
720 CSR_READ_4(sc, BWI_MAC_STATUS); /* dummy read */ in bwi_mac_dummy_xmit()
1056 intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS); in bwi_mac_fw_load()
[all …]
/freebsd-12-stable/sys/dev/stge/
Dif_stge.c519 if (CSR_READ_4(sc, STGE_AsicCtrl) & AC_PhyMedia) in stge_attach()
1000 CSR_READ_4(sc, STGE_AsicCtrl) | AC_TxReset); in stge_setwol()
1058 if ((CSR_READ_4(sc, STGE_DMACtrl) & DMAC_TxDMAInProg) == 0) in stge_dma_wait()
1391 v = ac = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; in stge_link_task()
1397 ac = CSR_READ_4(sc, STGE_AsicCtrl); in stge_link_task()
1402 if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0) in stge_link_task()
1418 txstat = CSR_READ_4(sc, STGE_TxStatus); in stge_tx_error()
1440 (CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK) | in stge_tx_error()
1876 CSR_READ_4(sc,STGE_OctetRcvOk); in stge_stats_update()
1878 if_inc_counter(ifp, IFCOUNTER_IPACKETS, CSR_READ_4(sc, STGE_FramesRcvdOk)); in stge_stats_update()
[all …]
/freebsd-12-stable/sys/dev/altera/atse/
Dif_atse.c182 #define CSR_READ_4(sc, reg) \ macro
407 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); in atse_stop_locked()
413 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); in atse_stop_locked()
456 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); in atse_rxfilter_locked()
756 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); in atse_reset()
762 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); in atse_reset()
798 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); in atse_reset()
836 val4 = CSR_READ_4(sc, TX_CMD_STAT); in atse_reset()
840 val4 = CSR_READ_4(sc, RX_CMD_STAT); in atse_reset()
846 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); in atse_reset()
[all …]
/freebsd-12-stable/sys/dev/ale/
Dif_ale.c218 v = CSR_READ_4(sc, ALE_MDIO); in ale_miibus_readreg()
245 v = CSR_READ_4(sc, ALE_MDIO); in ale_miibus_writereg()
295 reg = CSR_READ_4(sc, ALE_MAC_CFG); in ale_miibus_statchg()
368 reg = CSR_READ_4(sc, ALE_SPI_CTRL); in ale_get_macaddr()
379 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | in ale_get_macaddr()
383 reg = CSR_READ_4(sc, ALE_TWSI_CTRL); in ale_get_macaddr()
396 ea[0] = CSR_READ_4(sc, ALE_PAR0); in ale_get_macaddr()
397 ea[1] = CSR_READ_4(sc, ALE_PAR1); in ale_get_macaddr()
497 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) { in ale_attach()
523 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >> in ale_attach()
[all …]

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