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Searched refs:CSR_BARRIER (Results 1 – 23 of 23) sorted by relevance

/freebsd-12-stable/sys/arm/amlogic/aml8726/
Daml8726_usb_phy-m3.c105 #define CSR_BARRIER(sc, reg) bus_barrier((sc)->res[0], reg, 4, \ macro
259 CSR_BARRIER(sc, AML_USB_PHY_CFG_REG); in aml8726_usb_phy_attach()
268 CSR_BARRIER(sc, AML_USB_PHY_CFG_REG); in aml8726_usb_phy_attach()
275 CSR_BARRIER(sc, AML_USB_PHY_CFG_REG); in aml8726_usb_phy_attach()
282 CSR_BARRIER(sc, AML_USB_PHY_CFG_REG); in aml8726_usb_phy_attach()
289 CSR_BARRIER(sc, AML_USB_PHY_CFG_REG); in aml8726_usb_phy_attach()
296 CSR_BARRIER(sc, AML_USB_PHY_CFG_REG); in aml8726_usb_phy_attach()
303 CSR_BARRIER(sc, AML_USB_PHY_CFG_REG); in aml8726_usb_phy_attach()
310 CSR_BARRIER(sc, AML_USB_PHY_CFG_REG); in aml8726_usb_phy_attach()
322 CSR_BARRIER(sc, AML_USB_PHY_CFG_REG); in aml8726_usb_phy_attach()
[all …]
Daml8726_sdxc-m8.c153 #define CSR_BARRIER(sc, reg) bus_barrier((sc)->res[0], reg, 4, \ macro
206 CSR_BARRIER(sc, AML_SDXC_SOFT_RESET_REG); in aml8726_sdxc_soft_reset()
238 CSR_BARRIER(sc, AML_SDXC_PDMA_REG); in aml8726_sdxc_engage_dma()
245 CSR_BARRIER(sc, AML_SDXC_PDMA_REG); in aml8726_sdxc_engage_dma()
249 CSR_BARRIER(sc, AML_SDXC_PDMA_REG); in aml8726_sdxc_engage_dma()
283 CSR_BARRIER(sc, AML_SDXC_PDMA_REG); in aml8726_sdxc_disengage_dma()
290 CSR_BARRIER(sc, AML_SDXC_PDMA_REG); in aml8726_sdxc_disengage_dma()
308 CSR_BARRIER(sc, AML_SDXC_PDMA_REG); in aml8726_sdxc_disengage_dma()
434 CSR_BARRIER(sc, AML_SDXC_SEND_REG); in aml8726_sdxc_start_command()
451 CSR_BARRIER(sc, AML_SDXC_IRQ_STATUS_REG); in aml8726_sdxc_finish_command()
[all …]
Daml8726_usb_phy-m6.c101 #define CSR_BARRIER(sc, reg) bus_barrier((sc)->res[0], reg, 4, \ macro
250 CSR_BARRIER(sc, AML_USB_PHY_CFG_REG); in aml8726_usb_phy_attach()
274 CSR_BARRIER(sc, AML_USB_PHY_CTRL_REG); in aml8726_usb_phy_attach()
286 CSR_BARRIER(sc, AML_USB_PHY_CTRL_REG); in aml8726_usb_phy_attach()
308 CSR_BARRIER(sc, AML_USB_PHY_ADP_BC_REG); in aml8726_usb_phy_attach()
383 CSR_BARRIER(sc, AML_USB_PHY_CTRL_REG); in aml8726_usb_phy_detach()
Daml8726_pic.c112 #define CSR_BARRIER(sc, reg) bus_barrier((sc)->res[0], reg, 4, \ macro
127 CSR_BARRIER(aml8726_pic_sc, AML_PIC_STAT_CLR_REG(nb)); in aml8726_pic_eoi()
256 CSR_BARRIER(aml8726_pic_sc, AML_PIC_MASK_REG(nb)); in arm_mask_irq()
275 CSR_BARRIER(aml8726_pic_sc, AML_PIC_MASK_REG(nb)); in arm_unmask_irq()
Daml8726_clkmsr.c107 #define CSR_BARRIER(sc, reg) bus_barrier((sc)->res[0], reg, 4, \ macro
125 CSR_BARRIER(sc, AML_CLKMSR_0_REG); in aml8726_clkmsr_clock_frequency()
133 CSR_BARRIER(sc, AML_CLKMSR_0_REG); in aml8726_clkmsr_clock_frequency()
141 CSR_BARRIER(sc, AML_CLKMSR_0_REG); in aml8726_clkmsr_clock_frequency()
Daml8726_rtc.c126 #define CSR_BARRIER(sc, reg) bus_barrier((sc)->res[0], reg, 4, \ macro
138 CSR_BARRIER(sc, AML_RTC_0_REG); in aml8726_rtc_start_transfer()
166 CSR_BARRIER(sc, AML_RTC_0_REG); in aml8726_rtc_sclk_pulse()
173 CSR_BARRIER(sc, AML_RTC_0_REG); in aml8726_rtc_sclk_pulse()
282 CSR_BARRIER(sc, AML_RTC_0_REG); in aml8726_rtc_initialize()
Daml8726_wdt.c101 #define CSR_BARRIER(sc, reg) bus_barrier((sc)->res[0], reg, 4, \ macro
152 CSR_BARRIER(sc, AML_WDT_CTRL_REG); in aml8726_wdt_intr()
Daml8726_mmc.c101 #define CSR_BARRIER(sc, reg) bus_barrier((sc)->res[0], reg, 4, \ macro
210 CSR_BARRIER(sc, AML_MMC_IRQ_CONFIG_REG); in aml8726_mmc_soft_reset()
347 CSR_BARRIER(sc, AML_MMC_CMD_SEND_REG); in aml8726_mmc_start_command()
364 CSR_BARRIER(sc, AML_MMC_IRQ_STATUS_REG); in aml8726_mmc_finish_command()
477 CSR_BARRIER(sc, AML_MMC_IRQ_STATUS_REG); in aml8726_mmc_intr()
/freebsd-12-stable/sys/dev/tl/
Dif_tl.c378 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
381 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
391 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
394 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
404 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
407 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
418 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
421 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
432 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
435 CSR_BARRIER(sc, TL_DIO_ADDR, 2,
[all …]
Dif_tlreg.h474 #define CSR_BARRIER(sc, reg, length, flags) \ macro
/freebsd-12-stable/sys/dev/xl/
Dif_xlreg.h668 #define CSR_BARRIER(sc, reg, length, flags) \ macro
672 CSR_BARRIER(sc, XL_COMMAND, 2, \
675 CSR_BARRIER(sc, XL_COMMAND, 2, \
Dif_xl.c394 CSR_BARRIER(sc, XL_W4_PHY_MGMT, 2, in xl_mii_bitbang_read()
412 CSR_BARRIER(sc, XL_W4_PHY_MGMT, 2, in xl_mii_bitbang_write()
/freebsd-12-stable/sys/dev/bm/
Dif_bmreg.h171 #define CSR_BARRIER(sc, reg, length, flags) \ macro
Dif_bm.c175 CSR_BARRIER(sc, BM_MII_CSR, 2, in bm_mii_bitbang_write()
191 CSR_BARRIER(sc, BM_MII_CSR, 2, in bm_mii_bitbang_read()
/freebsd-12-stable/sys/dev/wb/
Dif_wbreg.h383 #define CSR_BARRIER(sc, reg, length, flags) \ macro
Dif_wb.c358 CSR_BARRIER(sc, WB_SIO, 4, in wb_mii_bitbang_read()
375 CSR_BARRIER(sc, WB_SIO, 4, in wb_mii_bitbang_write()
/freebsd-12-stable/sys/dev/ste/
Dif_stereg.h497 #define CSR_BARRIER(sc, reg, length, flags) \ macro
Dif_ste.c216 CSR_BARRIER(sc, STE_PHYCTL, 1, in ste_mii_bitbang_read()
233 CSR_BARRIER(sc, STE_PHYCTL, 1, in ste_mii_bitbang_write()
/freebsd-12-stable/sys/dev/stge/
Dif_stgereg.h104 #define CSR_BARRIER(_sc, reg, length, flags) \ macro
Dif_stge.c260 CSR_BARRIER(sc, STGE_PhyCtrl, 1, in stge_mii_bitbang_read()
278 CSR_BARRIER(sc, STGE_PhyCtrl, 1, in stge_mii_bitbang_write()
/freebsd-12-stable/sys/dev/sis/
Dif_sis.c126 #define CSR_BARRIER(sc, reg, length, flags) \ macro
449 CSR_BARRIER(sc, SIS_EECTL, 4, in sis_mii_bitbang_read()
465 CSR_BARRIER(sc, SIS_EECTL, 4, in sis_mii_bitbang_write()
/freebsd-12-stable/sys/dev/rl/
Dif_rlreg.h962 #define CSR_BARRIER(sc, reg, length, flags) \ macro
Dif_rl.c370 CSR_BARRIER(sc, RL_MII, 1, in rl_mii_bitbang_read()
387 CSR_BARRIER(sc, RL_MII, 1, in rl_mii_bitbang_write()