Searched refs:CP_RB0_BASE (Results 1 – 4 of 4) sorted by relevance
444 #define CP_RB0_BASE 0xC100 macro
671 #define CP_RB0_BASE 0xC100 macro
1118 CP_RB0_BASE, in cayman_cp_resume()
2082 WREG32(CP_RB0_BASE, ring->gpu_addr >> 8); in si_cp_resume()