| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| D | SparcInstrInfo.td | 193 def CCOp : Operand<i32>;
272 // Note that these values must be kept in sync with the CCOp::CondCode enum
816 def CC : F2_3<0b001, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond),
820 def CCA : F2_3<0b001, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond),
824 def CCNT : F2_3<0b001, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond),
828 def CCANT : F2_3<0b001, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond),
851 def BCOND : BranchSP<(ins brtarget:$imm22, CCOp:$cond),
854 def BCONDA : BranchSPA<(ins brtarget:$imm22, CCOp:$cond),
875 def CC : F2_3<0b101, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond,
878 def CCA : F2_3<0b101, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond,
[all …]
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| D | SparcInstr64Bit.td | 317 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
322 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
330 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
335 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
340 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| D | LanaiInstrInfo.td | 231 def CCOp : Operand<i32> {
685 def BRCC : InstBR<(outs), (ins BrTarget:$addr, CCOp:$DDDI),
768 def SCC : InstSCC<(outs GPR:$Rs1), (ins CCOp:$DDDI),
776 (ins GPR:$Rs1, GPR:$Rs2, CCOp:$DDDI),
788 def BRIND_CC : InstRR<0b101, (outs), (ins GPR:$Rs1, CCOp:$DDDI),
796 def BRIND_CCA : InstRR<0b101, (outs), (ins GPR:$Rs1, GPR:$Rs2, CCOp:$DDDI),
808 def BRR : InstBRR<(outs), (ins i16imm:$imm16, CCOp:$DDDI),
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| D | LanaiISelLowering.cpp | 1424 SDValue CCOp; in combineSelectAndUse() local
1426 if (!isConditionalZeroOrAllOnes(Slct.getNode(), AllOnes, CCOp, SwapSelectOps, in combineSelectAndUse()
1438 return DAG.getNode(ISD::SELECT, SDLoc(N), VT, CCOp, TrueVal, FalseVal); in combineSelectAndUse()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/VE/ |
| D | VEInstrInfo.td | 405 def CCOpAsmOperand : AsmOperandClass { let Name = "CCOp"; }
406 def CCOp : Operand<i32>, ImmLeaf<i32, [{
487 // Note that these values must be kept in sync with the CCOp::CondCode enum
723 def rr : RR<opc, (outs I64:$sx), (ins CCOp:$cfw, RC:$sy, I64:$sz, I64:$sd),
727 (ins CCOp:$cfw, simm7:$sy, I64:$sz, I64:$sd),
731 (ins CCOp:$cfw, RC:$sy, mimm:$sz, I64:$sd),
735 (ins CCOp:$cfw, simm7:$sy, mimm:$sz, I64:$sd),
835 defm r : BCtgm<opcStr, "$comp, ", opc, (ins CCOp:$cond, RC:$comp)>;
837 defm i : BCtgm<opcStr, "$comp, ", opc, (ins CCOp:$cond, immOp:$comp)>;
862 defm rr : BCRbpfm<opcStr, "$sy, $sz, ", opc, (ins CCOp:$cf, RC:$sy, RC:$sz)>;
[all …]
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| D | VEInstrVec.td | 33 (ins CCOp:$cf, V64:$vz, I32:$vl),
36 (ins CCOp:$cf, V64:$vz, VM512:$vm, I32:$vl),
39 (ins CCOp:$cf, V64:$vz, I32:$vl),
42 (ins CCOp:$cf, V64:$vz, VM512:$vm, I32:$vl),
739 defm v : RVMKlm<opcStr#"$vy", ", $vz", opc, RCM, (ins CCOp:$vy, RC:$vz)>;
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/VE/AsmParser/ |
| D | VEAsmParser.cpp | 187 struct CCOp { struct in __anonabffdf8e0211::VEOperand
205 struct CCOp CC;
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARC/ |
| D | ARCInstrInfo.td | 21 def CCOp : PredicateOperand<i32, (ops i32imm), (ops)>;
352 (outs GPR32:$b), (ins u6:$c, CCOp:$cc, GPR32:$b2),
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructionSelector.cpp | 1812 const MachineOperand &CCOp = I.getOperand(1); in selectG_SELECT() local
1813 Register CCReg = CCOp.getReg(); in selectG_SELECT()
1824 MRI->setRegClass(CCReg, TRI.getConstrainedRegClassForOperand(CCOp, *MRI)); in selectG_SELECT()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 3625 ISD::CondCode CCOp = cast<CondCodeSDNode>(CC)->get(); in ExpandNode() local
3627 if (TLI.isCondCodeLegalOrCustom(CCOp, Tmp1.getSimpleValueType())) { in ExpandNode()
3645 ISD::CondCode InvCC = ISD::getSetCCInverse(CCOp, Tmp1.getValueType()); in ExpandNode()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 2594 ISD::CondCode CC, SDValue CCOp, in emitConditionalComparison() argument
2624 return DAG.getNode(Opcode, DL, MVT_CC, LHS, RHS, NZCVOp, Condition, CCOp); in emitConditionalComparison()
2704 AArch64CC::CondCode &OutCC, bool Negate, SDValue CCOp, in emitConjunctionRec() argument
2727 if (!CCOp.getNode()) in emitConjunctionRec()
2730 ExtraCmp = emitConditionalComparison(LHS, RHS, CC, CCOp, Predicate, in emitConjunctionRec()
2732 CCOp = ExtraCmp; in emitConjunctionRec()
2738 if (!CCOp) in emitConjunctionRec()
2741 return emitConditionalComparison(LHS, RHS, CC, CCOp, Predicate, OutCC, DL, in emitConjunctionRec()
2802 SDValue CmpR = emitConjunctionRec(DAG, RHS, RHSCC, NegateR, CCOp, Predicate); in emitConjunctionRec()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 776 struct CCOp { struct in __anon46f2ecb80111::ARMOperand
899 struct CCOp CC;
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 12144 SDValue CCOp; in combineSelectAndUse() local
12146 if (!isConditionalZeroOrAllOnes(Slct.getNode(), AllOnes, CCOp, SwapSelectOps, in combineSelectAndUse()
12159 CCOp, TrueVal, FalseVal); in combineSelectAndUse()
|