| /freebsd-12-stable/contrib/binutils/opcodes/ |
| D | i386-tbl.h | 18 Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
26 Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
38 BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
46 BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
53 { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
61 { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
93 { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
97 { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
101 { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
105 { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S,
[all …]
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| D | i386-reg.tbl | 34 bx, Reg16|BaseIndex, 0, 3
36 bp, Reg16|BaseIndex, 0, 5
37 si, Reg16|BaseIndex, 0, 6
38 di, Reg16|BaseIndex, 0, 7
48 eax, Reg32|BaseIndex|Acc, 0, 0
49 ecx, Reg32|BaseIndex, 0, 1
50 edx, Reg32|BaseIndex, 0, 2
51 ebx, Reg32|BaseIndex, 0, 3
53 ebp, Reg32|BaseIndex, 0, 5
54 esi, Reg32|BaseIndex, 0, 6
[all …]
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| D | i386-opc.tbl | 8 …Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Dis…
12 …odrm|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Dis…
20 mov, 2, 0x8c, None, 0, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { SReg2, BaseIndex…
22 …386, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { SReg3, BaseIndex|Disp8|Disp16|Dis…
24 mov, 2, 0x8e, None, 0, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|…
26 mov, 2, 0x8e, None, Cpu386, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|D…
40 …, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Dis…
41 …, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Dis…
42 … Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|BaseIndex|Disp8|Disp16|Dis…
43 …64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64, { Reg8|BaseIndex|Disp8|Disp16|Dis…
[all …]
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| D | i386-opc.h | 159 #define BaseIndex 0x800 macro
200 #define AnyMem (Disp8|Disp16|Disp32|Disp32S|BaseIndex) /* General memory */
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| D | VirtRegMap.cpp | 391 SlotIndex BaseIndex = LIS->getInstructionIndex(MI); in readsUndefSubreg() local
394 assert(LI.liveAt(BaseIndex) && in readsUndefSubreg()
401 if ((SR.LaneMask & UseMask).any() && SR.liveAt(BaseIndex)) in readsUndefSubreg()
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| D | CodeGenPrepare.cpp | 5959 Value *BaseIndex = ConstantInt::get(IntPtrTy, BaseOffset); in splitLargeGEPOffsets() local
5964 NewBaseBuilder.CreateGEP(I8Ty, NewBaseGEP, BaseIndex, "splitgep"); in splitLargeGEPOffsets()
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| /freebsd-12-stable/contrib/binutils/gas/config/ |
| D | tc-i386.c | 1452 { BaseIndex, "BaseIndex" },
2471 if (!disp && (i.types[op] & BaseIndex)) in optimize_disp()
2522 && (((given) & (BaseIndex | JumpAbsolute)) \ in match_template()
2523 == ((overlap) & (BaseIndex | JumpAbsolute)))) in match_template()
3587 else if (i.base_reg->reg_type == BaseIndex) in build_modrm_byte()
4797 if ((i.types[this_operand] & BaseIndex) != 0 in i386_displacement()
4956 && (i.base_reg->reg_type != BaseIndex in i386_index_check()
4959 && ((i.index_reg->reg_type & (RegXX | BaseIndex)) in i386_index_check()
4960 != (RegXX | BaseIndex)))) in i386_index_check()
4969 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex)) in i386_index_check()
[all …]
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| D | SLPVectorizer.cpp | 413 unsigned BaseIndex = 0) { in getSameOpcode() argument
416 return InstructionsState(VL[BaseIndex], nullptr, nullptr); in getSameOpcode()
418 bool IsCastOp = isa<CastInst>(VL[BaseIndex]); in getSameOpcode()
419 bool IsBinOp = isa<BinaryOperator>(VL[BaseIndex]); in getSameOpcode()
420 unsigned Opcode = cast<Instruction>(VL[BaseIndex])->getOpcode(); in getSameOpcode()
422 unsigned AltIndex = BaseIndex; in getSameOpcode()
438 Type *Ty0 = cast<Instruction>(VL[BaseIndex])->getOperand(0)->getType(); in getSameOpcode()
454 return InstructionsState(VL[BaseIndex], nullptr, nullptr); in getSameOpcode()
457 return InstructionsState(VL[BaseIndex], cast<Instruction>(VL[BaseIndex]), in getSameOpcode()
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| /freebsd-12-stable/contrib/llvm-project/clang/lib/AST/ |
| D | MicrosoftMangle.cpp | 1780 unsigned BaseIndex = 0; in mangleTemplateArgValue() local
1782 mangleTemplateArgValue(B.getType(), V.getStructBase(BaseIndex++)); in mangleTemplateArgValue()
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| D | ExprConstant.cpp | 2376 unsigned BaseIndex = 0; in CheckEvaluationResult() local
2379 Value.getStructBase(BaseIndex), Kind, in CheckEvaluationResult()
2382 ++BaseIndex; in CheckEvaluationResult()
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| /freebsd-12-stable/contrib/binutils/include/opcode/ |
| D | ChangeLog-9103 | 1533 (i386_regtab): Add BaseIndex modifier to valid 16 bit base/index
1538 * i386.h (i386_regtab): Remove BaseIndex modifier from esp.
1560 (i386_regtab): Add BaseIndex to 32 bit regs reg_type.
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/IR/ |
| D | Verifier.cpp | 4930 const uint64_t BaseIndex = cast<ConstantInt>(Base)->getZExtValue(); in visitIntrinsicCall() local
4935 Assert(BaseIndex < Opt->Inputs.size(), in visitIntrinsicCall()
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| /freebsd-12-stable/contrib/binutils/gas/ |
| D | ChangeLog-0001 | 3750 (Imm8, Imm8S, Imm16, Imm32, Imm1, BaseIndex, Disp8, Disp16, Disp32,
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