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Searched refs:AllocateReg (Results 1 – 17 of 17) sorted by relevance

/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
DSystemZCallingConv.h121 Reg = State.AllocateReg(SystemZ::ELFArgGPRs); in CC_SystemZ_I128Indirect()
123 Reg = State.AllocateReg(SystemZ::XPLINK64ArgGPRs); in CC_SystemZ_I128Indirect()
147 State.AllocateReg(SystemZ::XPLINK64ArgGPRs); in CC_XPLINK64_Shadow_Reg()
151 State.AllocateReg(SystemZ::XPLINK64ArgGPRs); in CC_XPLINK64_Shadow_Reg()
152 State.AllocateReg(SystemZ::XPLINK64ArgGPRs); in CC_XPLINK64_Shadow_Reg()
159 State.AllocateReg(SystemZ::XPLINK64ArgFPRs[I + 1]); in CC_XPLINK64_Shadow_Reg()
182 State.AllocateReg(SystemZ::R1D); in CC_XPLINK64_Allocate128BitVararg()
184 bool AllocGPR2 = State.AllocateReg(SystemZ::R2D); in CC_XPLINK64_Allocate128BitVararg()
185 bool AllocGPR3 = State.AllocateReg(SystemZ::R3D); in CC_XPLINK64_Allocate128BitVararg()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
DPPCCallingConv.cpp49 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignArgRegs()
74 State.AllocateReg(ArgRegs[RegNum + i]); in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
98 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
118 unsigned Reg = State.AllocateReg(HiRegList); in CC_PPC32_SPE_CustomSplitFP64()
127 unsigned T = State.AllocateReg(LoRegList[i]); in CC_PPC32_SPE_CustomSplitFP64()
147 unsigned Reg = State.AllocateReg(HiRegList, LoRegList); in CC_PPC32_SPE_RetF64()
DPPCISelLowering.cpp6569 if (unsigned Reg = State.AllocateReg(IsPPC64 ? GPR_64 : GPR_32)) in CC_AIX()
6596 if (unsigned Reg = State.AllocateReg(IsPPC64 ? GPR_64 : GPR_32)) in CC_AIX()
6611 unsigned FReg = State.AllocateReg(FPR); in CC_AIX()
6617 if (unsigned Reg = State.AllocateReg(IsPPC64 ? GPR_64 : GPR_32)) { in CC_AIX()
6657 if (unsigned VReg = State.AllocateReg(VR)) { in CC_AIX()
6678 unsigned Reg = State.AllocateReg(GPRs); in CC_AIX()
6690 if (unsigned VReg = State.AllocateReg(VR)) { in CC_AIX()
6694 State.AllocateReg(GPRs); in CC_AIX()
6719 const unsigned FirstReg = State.AllocateReg(PPC::R9); in CC_AIX()
6720 const unsigned SecondReg = State.AllocateReg(PPC::R10); in CC_AIX()
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/
DARMCallingConv.cpp27 if (unsigned Reg = State.AllocateReg(RegList)) in f64AssignAPCS()
41 if (unsigned Reg = State.AllocateReg(RegList)) in f64AssignAPCS()
70 unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList); in f64AssignAAPCS()
74 Reg = State.AllocateReg(GPRArgRegs); in f64AssignAAPCS()
92 unsigned T = State.AllocateReg(LoRegList[i]); in f64AssignAAPCS()
119 unsigned Reg = State.AllocateReg(HiRegList, LoRegList); in f64RetAssign()
207 State.AllocateReg(RegList[RegIdx++]); in CC_ARM_AAPCS_Custom_Aggregate()
253 It.convertToReg(State.AllocateReg(RegList[RegIdx++])); in CC_ARM_AAPCS_Custom_Aggregate()
266 State.AllocateReg(Reg); in CC_ARM_AAPCS_Custom_Aggregate()
291 unsigned Reg = State.AllocateReg(RegList); in CustomAssignInRegList()
DARMISelLowering.cpp2802 unsigned Reg = State->AllocateReg(GPRArgRegs); in HandleByVal()
2809 Reg = State->AllocateReg(GPRArgRegs); in HandleByVal()
2822 while (State->AllocateReg(GPRArgRegs)) in HandleByVal()
2839 State->AllocateReg(GPRArgRegs); in HandleByVal()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/
DX86CallingConv.cpp53 unsigned Reg = State.AllocateReg(AvailableRegs[I]); in CC_X86_32_RegCall_Assign2Regs()
104 unsigned AssigedReg = State.AllocateReg(Reg); in CC_X86_VectorCallAssignRegister()
149 (void)State.AllocateReg(CC_X86_VectorCallGetSSEs(ValVT)); in CC_X86_64_VectorCall()
157 (void)State.AllocateReg(CC_X86_64_VectorCallGetGPRs()); in CC_X86_64_VectorCall()
160 if (unsigned Reg = State.AllocateReg(CC_X86_VectorCallGetSSEs(ValVT))) { in CC_X86_64_VectorCall()
211 if (unsigned Reg = State.AllocateReg(CC_X86_VectorCallGetSSEs(ValVT))) { in CC_X86_32_VectorCall()
261 if (unsigned Reg = State.AllocateReg(RegList)) { in CC_X86_32_MCUInReg()
282 It.convertToReg(State.AllocateReg(RegList[FirstFree++])); in CC_X86_32_MCUInReg()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/M68k/
DM68kCallingConv.h65 IsPtr ? State.AllocateReg(AddrRegList) : State.AllocateReg(DataRegList); in CC_M68k_Any_AssignToReg()
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
DCallingConvLower.h351 MCRegister AllocateReg(MCPhysReg Reg) { in AllocateReg() function
359 MCRegister AllocateReg(MCPhysReg Reg, MCPhysReg ShadowReg) { in AllocateReg() function
370 MCPhysReg AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg() function
411 MCRegister AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) { in AllocateReg() function
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
DAMDGPUCallLowering.cpp451 CCInfo.AllocateReg(PrivateSegmentBufferReg); in allocateHSAUserSGPRs()
457 CCInfo.AllocateReg(DispatchPtrReg); in allocateHSAUserSGPRs()
463 CCInfo.AllocateReg(QueuePtrReg); in allocateHSAUserSGPRs()
474 CCInfo.AllocateReg(InputPtrReg); in allocateHSAUserSGPRs()
480 CCInfo.AllocateReg(DispatchIDReg); in allocateHSAUserSGPRs()
486 CCInfo.AllocateReg(FlatScratchInitReg); in allocateHSAUserSGPRs()
605 CCInfo.AllocateReg(ImplicitBufferPtrReg); in lowerFormalArguments()
678 CCInfo.AllocateReg(AMDGPU::VGPR0); in lowerFormalArguments()
679 CCInfo.AllocateReg(AMDGPU::VGPR1); in lowerFormalArguments()
734 CCInfo.AllocateReg(Info->getScratchRSrcReg()); in lowerFormalArguments()
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DSIISelLowering.cpp1874 CCInfo.AllocateReg(Reg); in allocateSpecialEntryInputVGPRs()
1889 CCInfo.AllocateReg(Reg); in allocateSpecialEntryInputVGPRs()
1903 CCInfo.AllocateReg(Reg); in allocateSpecialEntryInputVGPRs()
1929 Reg = CCInfo.AllocateReg(Reg); in allocateVGPR32Input()
1947 Reg = CCInfo.AllocateReg(Reg); in allocateSGPR32InputImpl()
1961 Reg = CCInfo.AllocateReg(Reg); in allocateFixedSGPRInputImpl()
2009 Register Reg = CCInfo.AllocateReg(AMDGPU::VGPR31); in allocateSpecialInputVGPRsFixed()
2062 CCInfo.AllocateReg(ImplicitBufferPtrReg); in allocateHSAUserSGPRs()
2069 CCInfo.AllocateReg(PrivateSegmentBufferReg); in allocateHSAUserSGPRs()
2075 CCInfo.AllocateReg(DispatchPtrReg); in allocateHSAUserSGPRs()
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
DAArch64CallingConvention.cpp65 State.AllocateReg(ZRegList[I]); in finishStackBlock()
192 State.AllocateReg(Reg); in CC_AArch64_Custom_Block()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/
DMipsISelLowering.cpp2910 Reg = State.AllocateReg(FloatVectorIntRegs); in CC_MipsO32()
2912 State.AllocateReg(Mips::A1); in CC_MipsO32()
2914 State.AllocateReg(Mips::A3); in CC_MipsO32()
2918 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
2922 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
2926 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
2933 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
2935 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
2940 MCRegister HiReg = State.AllocateReg(IntRegs); in CC_MipsO32()
2949 Reg = State.AllocateReg(F32Regs); in CC_MipsO32()
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
DRISCVISelLowering.cpp7017 if (Register Reg = State.AllocateReg(ArgGPRs)) { in CC_RISCVAssign2XLen()
7035 if (Register Reg = State.AllocateReg(ArgGPRs)) { in CC_RISCVAssign2XLen()
7058 return State.AllocateReg(RISCV::V0); in allocateRVVReg()
7059 return State.AllocateReg(ArgVRs); in allocateRVVReg()
7062 return State.AllocateReg(ArgVRM2s); in allocateRVVReg()
7064 return State.AllocateReg(ArgVRM4s); in allocateRVVReg()
7066 return State.AllocateReg(ArgVRM8s); in allocateRVVReg()
7140 State.AllocateReg(ArgGPRs); in CC_RISCV()
7159 Register Reg = State.AllocateReg(ArgGPRs); in CC_RISCV()
7167 if (!State.AllocateReg(ArgGPRs)) in CC_RISCV()
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AVR/
DAVRISelLowering.cpp1068 Reg = CCInfo.AllocateReg(RegList8[RegIdx]); in analyzeArguments()
1070 Reg = CCInfo.AllocateReg(RegList16[RegIdx]); in analyzeArguments()
1121 Reg = CCInfo.AllocateReg(RegList8[RegIdx]); in analyzeReturnValues()
1123 Reg = CCInfo.AllocateReg(RegList16[RegIdx]); in analyzeReturnValues()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp529 unsigned Reg = State.AllocateReg(RegList); in AnalyzeArguments()
537 unsigned Reg = State.AllocateReg(RegList); in AnalyzeArguments()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp62 if (Register Reg = State.AllocateReg(RegList)) { in CC_Sparc_Assign_Split_64()
72 if (Register Reg = State.AllocateReg(RegList)) in CC_Sparc_Assign_Split_64()
89 if (Register Reg = State.AllocateReg(RegList)) in CC_Sparc_Assign_Ret_Split_64()
95 if (Register Reg = State.AllocateReg(RegList)) in CC_Sparc_Assign_Ret_Split_64()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp152 State.AllocateReg(ArgRegs[RegNum]); in CC_SkipOdd()