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Searched refs:AR_PHY_BASE (Results 1 – 13 of 13) sorted by relevance

/freebsd-12-stable/sys/dev/otus/
Dif_otusreg.h124 #define AR_PHY_BASE 0x1c5800 macro
125 #define AR_PHY(reg) (AR_PHY_BASE + (reg) * 4)
126 #define AR_PHY_TURBO (AR_PHY_BASE + 0x0004)
127 #define AR_PHY_RF_CTL3 (AR_PHY_BASE + 0x0028)
128 #define AR_PHY_RF_CTL4 (AR_PHY_BASE + 0x0034)
129 #define AR_PHY_SETTLING (AR_PHY_BASE + 0x0044)
130 #define AR_PHY_RXGAIN (AR_PHY_BASE + 0x0048)
131 #define AR_PHY_DESIRED_SZ (AR_PHY_BASE + 0x0050)
132 #define AR_PHY_FIND_SIG (AR_PHY_BASE + 0x0058)
133 #define AR_PHY_AGC_CTL1 (AR_PHY_BASE + 0x005c)
[all …]
/freebsd-12-stable/sys/dev/ath/ath_hal/ar5211/
Dar5211_attach.c195 OS_REG_WRITE(ah, (AR_PHY_BASE + (0x34 << 2)), 0x00001c16); in ar5211GetRadioRev()
197 OS_REG_WRITE(ah, (AR_PHY_BASE + (0x20 << 2)), 0x00010000); in ar5211GetRadioRev()
198 val = (OS_REG_READ(ah, AR_PHY_BASE + (256 << 2)) >> 24) & 0xff; in ar5211GetRadioRev()
288 OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000007); in ar5211Attach()
290 OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000047); in ar5211Attach()
321 OS_REG_WRITE(ah, AR_PHY_BASE, 0x00004007); in ar5211Attach()
326 OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000007); in ar5211Attach()
392 uint32_t regAddr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) }; in ar5211ChipTest()
Dar5211phy.h29 #define AR_PHY_BASE 0x9800 /* PHY registers base address */ macro
30 #define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2))
Dar5211_reset.c286 OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000007); in ar5211Reset()
288 OS_REG_WRITE(ah, AR_PHY_BASE, 0x00000047); in ar5211Reset()
1242 OS_REG_WRITE(ah, AR_PHY_BASE + (90 << 2), in ar5211SetBoardValues()
1245 OS_REG_WRITE(ah, AR_PHY_BASE + (17 << 2), in ar5211SetBoardValues()
1246 (OS_REG_READ(ah, AR_PHY_BASE + (17 << 2)) & 0xFFFFC07F) | in ar5211SetBoardValues()
1248 OS_REG_WRITE(ah, AR_PHY_BASE + (18 << 2), in ar5211SetBoardValues()
1249 (OS_REG_READ(ah, AR_PHY_BASE + (18 << 2)) & 0xFFFC0FFF) | in ar5211SetBoardValues()
1251 OS_REG_WRITE(ah, AR_PHY_BASE + (20 << 2), in ar5211SetBoardValues()
1252 (OS_REG_READ(ah, AR_PHY_BASE + (20 << 2)) & 0xFFFF0000) | in ar5211SetBoardValues()
1255 OS_REG_WRITE(ah, AR_PHY_BASE + (13 << 2), in ar5211SetBoardValues()
[all …]
Dar5211_misc.c181 OS_REG_SET_BIT(ah, AR_PHY_BASE, 0x00002000); in ar5211EnableRfKill()
/freebsd-12-stable/sys/dev/ath/ath_hal/ar5210/
Dar5210phy.h29 #define AR_PHY_BASE 0x9800 /* PHY register base */ macro
30 #define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2))
Dar5210_attach.c247 OS_REG_WRITE(ah, (AR_PHY_BASE + (0x34 << 2)), 0x00001c16); in ar5210Attach()
249 OS_REG_WRITE(ah, (AR_PHY_BASE + (0x20 << 2)), 0x00010000); in ar5210Attach()
250 revid = (OS_REG_READ(ah, AR_PHY_BASE + (256 << 2)) >> 28) & 0xf; in ar5210Attach()
Dar5210_misc.c387 nf = (OS_REG_READ(ah, AR_PHY_BASE + (25 << 2)) >> 19) & 0x1ff; in ar5210GetRandomSeed()
/freebsd-12-stable/sys/dev/ath/ath_hal/ar5212/
Dar5212phy.h25 #define AR_PHY_BASE 0x9800 /* base address of phy regs */ macro
26 #define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2))
Dar5212_attach.c606 uint32_t regAddr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) }; in ar5212ChipTest()
/freebsd-12-stable/tools/tools/ath/athdecode/
Dmain.c402 } else if (AR_PHY_BASE <= r->reg) { in oprw()
404 (r->reg - AR_PHY_BASE) >> 2, r->reg); in oprw()
/freebsd-12-stable/sys/contrib/dev/ath/ath_hal/ar9300/
Dar9300phy.h34 #define AR_PHY_BASE offsetof(struct bb_reg_map, bb_chn_reg_map) /* base address of phy reg… macro
35 #define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2))
/freebsd-12-stable/sys/dev/ath/ath_hal/ar5416/
Dar5416_reset.c2319 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset; in ar5416WritePdadcValues()