| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64ExternalSymbolizer.cpp | 108 MI.getOpcode() == AArch64::ADR) { in tryAddingSymbolicOperand()
117 } else if (MI.getOpcode() == AArch64::ADR) { in tryAddingSymbolicOperand()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64SchedPredExynos.td | 125 [ADR, ADRP,
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| D | AArch64MacroFusion.cpp | 225 case AArch64::ADR: in isAddressLdStPair()
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| D | AArch64ISelLowering.h | 62 ADR, // ADR enumerator
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| D | AArch64AsmPrinter.cpp | 913 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::ADR) in LowerJumpTableDest()
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| D | AArch64SchedCyclone.td | 140 // ADR,ADRP
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| D | AArch64SchedTSV110.td | 382 def : InstRW<[TSV110Wr_1cyc_1ALUAB], (instrs ADR, ADRP)>;
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| D | AArch64SchedExynosM3.td | 507 def : InstRW<[M3WriteZ0], (instrs ADR, ADRP)>;
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| D | AArch64SchedExynosM5.td | 651 def : InstRW<[M5WriteZ0], (instrs ADR, ADRP)>;
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| D | AArch64SchedExynosM4.td | 604 def : InstRW<[M4WriteZ0], (instrs ADR, ADRP)>;
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| D | AArch64InstrInfo.td | 410 def AArch64adr : SDNode<"AArch64ISD::ADR", SDTIntUnaryOp, []>;
2213 def ADR : ADRI<0, "adr", adrlabel,
2222 def : Pat<(AArch64adr tconstpool:$cp), (ADR tconstpool:$cp)>;
2223 def : Pat<(AArch64adr tblockaddress:$cp), (ADR tblockaddress:$cp)>;
2224 def : Pat<(AArch64adr texternalsym:$sym), (ADR texternalsym:$sym)>;
2225 def : Pat<(AArch64adr tjumptable:$sym), (ADR tjumptable:$sym)>;
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| D | AArch64SchedKryoDetails.td | 351 (instregex "ADR.*")>;
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| D | LoopRerollPass.cpp | 907 const auto *ADR = dyn_cast<SCEVAddRecExpr>(SE->getSCEV(DRS.BaseInst)); in validateRootSet() local
908 if (!ADR) in validateRootSet()
913 const SCEV *StepSCEV = SE->getMinusSCEV(SE->getSCEV(DRS.Roots[0]), ADR); in validateRootSet()
917 if (ADR->getStepRecurrence(*SE) != SE->getMulExpr(StepSCEV, ScaleSCEV)) in validateRootSet()
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| /freebsd-12-stable/sys/contrib/edk2/Include/Protocol/ |
| D | DevicePath.h | 285 UINT32 ADR; member
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| /freebsd-12-stable/contrib/binutils/gas/doc/ |
| D | c-arm.texi | 672 @cindex @code{ADR reg,<label>} pseudo op, ARM
673 @item ADR
682 the ADR instruction, then an error will be generated. This instruction
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| /freebsd-12-stable/lib/libefivar/ |
| D | efivar-dp-format.c | 597 UefiDevicePathLibCatPrint (Str, "AcpiAdr(0x%x", AcpiAdr->ADR); in DevPathToTextAcpiAdr()
598 Addr = &AcpiAdr->ADR + 1; in DevPathToTextAcpiAdr()
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| D | efivar-dp-parse.c | 1081 (&AcpiAdr->ADR)[Index] = (UINT32) Strtoi (DisplayDeviceStr); in DevPathFromTextAcpiAdr()
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrHFP.td | 134 def ADR : BinaryRR<"adr", 0x2A, null_frag, FP64, FP64>;
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64MCCodeEmitter.cpp | 251 MCFixupKind Kind = MI.getOpcode() == AArch64::ADR in getAdrLabelOpValue()
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| /freebsd-12-stable/contrib/file/magic/Magdir/ |
| D | hp | 208 >8 leshort 0x2911 (ADR)
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMAsmPrinter.cpp | 1328 : ARM::ADR)) in emitInstruction()
1344 : ARM::ADR)) in emitInstruction()
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| D | ARMScheduleSwift.td | 129 // ADC,ADD,NEG,RSB,RSC,SBC,SUB,ADR
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| D | ARMScheduleR52.td | 326 (instregex "ADR", "MOVsi", "MVNS?s?i", "t2MOVS?si")>;
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| D | ARMScheduleA57.td | 171 // ADD{S}, ADC{S}, ADR, AND{S}, BIC{S}, CMN, CMP, EOR{S}, ORN{S}, ORR{S},
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| D | ARMInstrThumb.td | 133 // ADR instruction labels.
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