| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVMergeBaseOffset.cpp | 43 bool detectLuiAddiGlobal(MachineInstr &LUI, MachineInstr *&ADDI);
90 if (LoADDI->getOpcode() != RISCV::ADDI || in INITIALIZE_PASS()
147 if (OffsetTail.getOpcode() == RISCV::ADDI) { in matchLargeOffset()
190 case RISCV::ADDI: { in detectAndFoldOffset()
|
| D | RISCVRegisterInfo.cpp | 209 if (MI.getOpcode() == RISCV::ADDI && !Offset.getScalable()) { in eliminateFrameIndex()
233 BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), ScratchReg) in eliminateFrameIndex()
247 if (MI.getOpcode() == RISCV::ADDI && !Offset.getFixed()) { in eliminateFrameIndex()
262 BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), VL) in eliminateFrameIndex()
|
| D | RISCVExpandPseudoInsts.cpp | 202 RISCV::ADDI); in expandLoadLocalAddress()
217 SecondOpcode = RISCV::ADDI; in expandLoadAddress()
238 RISCV::ADDI); in expandLoadTLSGDAddress()
|
| D | RISCVInstrInfo.td | 346 // Check if (add r, imm) can be optimized to (ADDI (ADDI r, imm0), imm1),
491 // ADDI isn't always rematerializable, but isReMaterializable will be used as
494 def ADDI : ALU_ri<0b000, "addi">;
659 def : InstAlias<"nop", (ADDI X0, X0, 0)>;
686 def : InstAlias<"mv $rd, $rs", (ADDI GPR:$rd, GPR:$rs, 0)>;
802 (ADDI GPR:$rd, GPR:$rs1, simm12:$imm12)>;
899 def : PatGprSimm12<add, ADDI>;
941 (ADDI (XLenVT AddrFI:$Rs), simm12:$imm12)>;
943 (ADDI (XLenVT AddrFI:$Rs), simm12:$imm12)>;
957 (SLTIU (ADDI GPR:$rs1, (NegImm simm12_plus1:$imm12)), 1)>;
[all …]
|
| D | RISCVFrameLowering.cpp | 72 BuildMI(MBB, MI, DL, TII->get(RISCV::ADDI)) in emitSCSPrologue()
122 BuildMI(MBB, MI, DL, TII->get(RISCV::ADDI)) in emitSCSEpilogue()
268 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DestReg) in adjustReg()
526 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), BPReg) in emitPrologue()
|
| D | RISCVInstrInfoC.td | 760 def : CompressPat<(ADDI GPRC:$rd, SP:$rs1, uimm10_lsb00nonzero:$imm),
806 def : CompressPat<(ADDI X0, X0, 0), (C_NOP)>;
807 def : CompressPat<(ADDI GPRNoX0:$rs1, GPRNoX0:$rs1, simm6nonzero:$imm),
822 def : CompressPat<(ADDI GPRNoX0:$rd, X0, simm6:$imm),
824 def : CompressPat<(ADDI X2, X2, simm10_lsb0000nonzero:$imm),
910 def : CompressPat<(ADDI GPRNoX0:$rs1, GPRNoX0:$rs2, 0),
|
| D | RISCVInstrInfo.cpp | 57 return MCInstBuilder(RISCV::ADDI) in getNop()
126 BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg) in copyPhysReg()
819 case RISCV::ADDI: in isAsCheapAsAMove()
836 case RISCV::ADDI: in isCopyInstrImpl()
1520 BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), N) in getVLENFactoredAmount()
|
| D | RISCVExpandAtomicPseudoInsts.cpp | 305 BuildMI(LoopMBB, DL, TII->get(RISCV::ADDI), ScratchReg) in doMaskedAtomicBinOpExpansion()
444 BuildMI(LoopHeadMBB, DL, TII->get(RISCV::ADDI), Scratch1Reg) in expandAtomicMinMaxOp()
|
| D | RISCVISelDAGToDAG.cpp | 470 ReplaceNode(Node, CurDAG->getMachineNode(RISCV::ADDI, DL, VT, TFI, Imm)); in Select()
1660 if (!Base.isMachineOpcode() || Base.getMachineOpcode() != RISCV::ADDI) in doPeepholeLoadStoreADDI()
|
| D | RISCVInstrInfoB.td | 895 (CMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>;
897 (CMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>;
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/ |
| D | RISCVMatInt.cpp | 28 case RISCV::ADDI: in getInstSeqCost()
71 unsigned AddiOpc = (IsRV64 && Hi20) ? RISCV::ADDIW : RISCV::ADDI; in generateInstSeqImpl()
119 Res.push_back(RISCVMatInt::Inst(RISCV::ADDI, Lo12)); in generateInstSeqImpl()
|
| /freebsd-12-stable/contrib/llvm-project/lld/ELF/Arch/ |
| D | RISCV.cpp | 46 ADDI = 0x13, enumerator
197 write32le(buf + 12, itype(ADDI, X_T1, X_T1, -target->pltHeaderSize - 12)); in writePltHeader()
198 write32le(buf + 16, itype(ADDI, X_T0, X_T2, lo12(offset))); in writePltHeader()
214 write32le(buf + 12, itype(ADDI, 0, 0, 0)); in writePlt()
|
| D | PPC64.cpp | 62 ADDI = 14 enumerator
853 return ADDI; in getPPCDFormOp()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCMacroFusion.def | 35 FUSION_OP_SET(ADDI, ADDI8, ADDItocL), \
|
| D | PPCMachineScheduler.cpp | 25 return Cand.SU->getInstr()->getOpcode() == PPC::ADDI || in isADDIInstr()
|
| D | PPCRegisterInfo.cpp | 107 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; in PPCRegisterInfo()
676 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) in lowerDynamicAlloc()
729 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), FramePointer) in prepareDynamicAlloca()
1573 if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) && in needsFrameBaseReg()
1603 unsigned ADDriOpc = TM.isPPC64() ? PPC::ADDI8 : PPC::ADDI; in materializeFrameBaseRegister()
|
| D | PPCExpandISEL.cpp | 447 TII->get(isISEL8(*MI) ? PPC::ADDI8 : PPC::ADDI)) in populateBlocks()
|
| D | PPCAsmPrinter.cpp | 788 MCInstBuilder(PPC::ADDI).addReg(PICR).addReg(PICR).addExpr(DeltaLo)); in emitInstruction()
1207 MCInstBuilder(IsPPC64 ? PPC::ADDI8 : PPC::ADDI) in emitInstruction()
1258 MCInstBuilder(IsPPC64 ? PPC::ADDI8 : PPC::ADDI) in emitInstruction()
1322 MCInstBuilder(IsPPC64 ? PPC::ADDI8 : PPC::ADDI) in emitInstruction()
1734 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::ADDI) in emitFunctionBodyStart()
|
| D | PPCFrameLowering.cpp | 1089 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), BPReg) in emitPrologue()
1421 BuildMI(ProbeLoopBodyMBB, DL, TII.get(isPPC64 ? PPC::ADDI8 : PPC::ADDI), in inlineStackProbe()
1586 : PPC::ADDI ); in emitEpilogue()
2532 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI; in eliminateCallFramePseudoInstr()
|
| D | PPCInstrInfo.cpp | 3248 DefMI->getOpcode() == PPC::ADDI || in getForwardingDefMI()
3268 Opc == PPC::CMPLDI || Opc == PPC::ADDI || Opc == PPC::ADDI8 || in getForwardingDefMI()
3301 case PPC::ADDI: in getForwardingDefMI()
3549 if (Opc != PPC::ADDI && Opc != PPC::ADDI8) in isADDIInstrEligibleForFolding()
3866 III.ImmOpcode = Opc == PPC::ADD4 ? PPC::ADDI : PPC::ADDI8; in instrHasImmForm()
4350 if (Opc != PPC::ADDItocL && Opc != PPC::ADDI && Opc != PPC::ADDI8) in isDefMIElgibleForForwarding()
4550 case PPC::ADDI: in simplifyToLI()
|
| D | PPCFastISel.cpp | 1312 Opc = PPC::ADDI; in SelectBinaryIntOp()
1329 Opc = PPC::ADDI; in SelectBinaryIntOp()
2428 if (MachineInstOpcode == PPC::ADDI) in fastEmitInst_ri()
|
| D | PPCMIPeephole.cpp | 959 if (LiMI->getOpcode() == PPC::ADDI || LiMI->getOpcode() == PPC::ADDI8) in simplifyCode()
967 LiMI->setDesc(TII->get(LiMI->getOpcode() == PPC::LI ? PPC::ADDI in simplifyCode()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/ |
| D | RISCVAsmParser.cpp | 2275 RISCV::ADDI, IDLoc, Out); in emitLoadLocalAddress()
2297 SecondOpcode = RISCV::ADDI; in emitLoadAddress()
2329 RISCV::ADDI, IDLoc, Out); in emitLoadTLSGDAddress()
2551 emitToStreamer(Out, MCInstBuilder(RISCV::ADDI) in processInstruction()
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AVR/ |
| D | AVRDevices.td | 55 // The device supports `ADDI Rd, K`, `SUBI Rd, K`.
|
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/AsmParser/ |
| D | PPCAsmParser.cpp | 830 TmpInst.setOpcode(PPC::ADDI); in ProcessInstruction()
|