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Searched refs:v8i64 (Results 1 – 22 of 22) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
HDX86TargetTransformInfo.cpp306 { ISD::SRA, MVT::v8i64, 1 }, in getArithmeticInstrCost()
489 { ISD::MUL, MVT::v8i64, 1 } in getArithmeticInstrCost()
529 { ISD::SHL, MVT::v8i64, 1 }, in getArithmeticInstrCost()
530 { ISD::SRL, MVT::v8i64, 1 }, in getArithmeticInstrCost()
534 { ISD::SRA, MVT::v8i64, 1 }, in getArithmeticInstrCost()
541 { ISD::MUL, MVT::v8i64, 8 }, // 3*pmuludq/3*shift/2*add in getArithmeticInstrCost()
1035 {TTI::SK_Broadcast, MVT::v8i64, 1}, // vpbroadcastq in getShuffleCost()
1040 {TTI::SK_Reverse, MVT::v8i64, 1}, // vpermq in getShuffleCost()
1049 {TTI::SK_PermuteSingleSrc, MVT::v8i64, 1}, // vpermq in getShuffleCost()
1059 {TTI::SK_PermuteTwoSrc, MVT::v8i64, 1}, // vpermt2q in getShuffleCost()
[all …]
HDX86InstrVecCompiler.td84 defm : subvector_subreg_lowering<VR128, v2i64, VR512, v8i64, sub_xmm>;
95 defm : subvector_subreg_lowering<VR256, v4i64, VR512, v8i64, sub_ymm>;
133 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v8i64, v2i64, v16i32, sub_xmm>;
140 defm : subvec_zero_lowering<"DQA64Z256", VR256X, v8i64, v4i64, v16i32, sub_ymm>;
149 defm : subvec_zero_lowering<"DQA", VR128, v8i64, v2i64, v16i32, sub_xmm>;
156 defm : subvec_zero_lowering<"DQAY", VR256, v8i64, v4i64, v16i32, sub_ymm>;
HDX86CallingConv.td120 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
150 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
195 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
248 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
303 CCIfType<[v16f32, v8f64, v16i32, v8i64],
557 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
577 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
624 CCIfType<[v64i8, v32i16, v16i32, v16f32, v8f64, v8i64], CCPassIndirect<i64>>,
689 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
747 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
[all …]
HDX86InstrAVX512.td419 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
436 (v8i64 immAllOnesV),
437 (v8i64 immAllZerosV)))]>;
920 def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 2))),
922 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm)),
949 def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 2))),
951 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm)),
1397 def : Pat<(v8i64 (X86VBroadcast (v2i64 (X86vzload64 addr:$src)))),
1496 def : Pat<(v8i64 (X86SubVBroadcast (v4i64 VR256X:$src))),
1497 (VINSERTI64x4Zrr (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm),
[all …]
HDX86InstrFragmentsSIMD.td810 def loadv8i64 : PatFrag<(ops node:$ptr), (v8i64 (load node:$ptr))>;
869 (v8i64 (alignedload node:$ptr))>;
938 return Mgt->getIndex().getValueType() == MVT::v8i64;
973 return Sc->getIndex().getValueType() == MVT::v8i64;
1001 def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>;
HDX86ISelLowering.cpp1215 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom); in X86TargetLowering()
1217 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom); in X86TargetLowering()
1448 addRegisterClass(MVT::v8i64, &X86::VR512RegClass); in X86TargetLowering()
1454 setLoadExtAction(ExtType, MVT::v8i64, MVT::v8i8, Legal); in X86TargetLowering()
1455 setLoadExtAction(ExtType, MVT::v8i64, MVT::v8i16, Legal); in X86TargetLowering()
1456 setLoadExtAction(ExtType, MVT::v8i64, MVT::v8i32, Legal); in X86TargetLowering()
1495 setTruncStoreAction(MVT::v8i64, MVT::v8i8, Legal); in X86TargetLowering()
1496 setTruncStoreAction(MVT::v8i64, MVT::v8i16, Legal); in X86TargetLowering()
1497 setTruncStoreAction(MVT::v8i64, MVT::v8i32, Legal); in X86TargetLowering()
1515 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom); in X86TargetLowering()
[all …]
HDX86RegisterInfo.td577 def VR512 : RegisterClass<"X86", [v16f32, v8f64, v64i8, v32i16, v16i32, v8i64],
581 def VR512_0_15 : RegisterClass<"X86", [v16f32, v8f64, v64i8, v32i16, v16i32, v8i64],
HDX86ISelDAGToDAG.cpp4043 case MVT::v8i64: in getVPTESTMOpc()
4061 case MVT::v8i64: in getVPTESTMOpc()
4090 case MVT::v8i64: in getVPTESTMOpc()
4120 case MVT::v8i64: in getVPTESTMOpc()
4138 case MVT::v8i64: in getVPTESTMOpc()
4167 case MVT::v8i64: in getVPTESTMOpc()
HDX86FastISel.cpp454 case MVT::v8i64: in X86FastEmitLoad()
626 case MVT::v8i64: in X86FastEmitStore()
HDX86InstrCompiler.td587 defm _VR512 : CMOVrr_PSEUDO<VR512, v8i64>;
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Support/
HDMachineValueType.h110 v8i64 = 60, // 8 x i64 enumerator
370 SimpleTy == MVT::v16i32 || SimpleTy == MVT::v8i64); in is512BitVector()
498 case v8i64: in getVectorElementType()
602 case v8i64: in getVectorNumElements()
794 case v8i64: in getSizeInBits()
977 if (NumElements == 8) return MVT::v8i64; in getVectorVT()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
HDAArch64TargetTransformInfo.cpp316 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, in getCastInstrCost()
317 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, in getCastInstrCost()
318 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 }, in getCastInstrCost()
319 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 6 }, in getCastInstrCost()
613 { ISD::SELECT, MVT::v8i1, MVT::v8i64, 8 * AmortizationCost }, in getCmpSelInstrCost()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
HDARMTargetTransformInfo.cpp231 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, in getCastInstrCost()
232 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, in getCastInstrCost()
233 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 }, in getCastInstrCost()
234 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 6 }, in getCastInstrCost()
455 { ISD::SELECT, MVT::v8i1, MVT::v8i64, 50 }, in getCmpSelInstrCost()
HDARMRegisterInfo.td547 def QQQQPR : RegisterClass<"ARM", [v8i64], 256, (add Tuples2QQ)> {
HDARMISelDAGToDAG.cpp2267 SDValue RegSeq = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0); in SelectVST()
2393 SuperReg = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0); in SelectVLDSTLane()
HDARMISelLowering.cpp1536 case MVT::v8i64: in findRepresentativeClass()
1737 if (VT == MVT::v8i64) in getRegClassFor()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
HDValueTypes.cpp205 case MVT::v8i64: return VectorType::get(Type::getInt64Ty(Context), 8); in getTypeForEVT()
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
HDValueTypes.td85 def v8i64 : ValueType<512, 60>; // 8 x i64 vector value
/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/
HDCodeGenTarget.cpp125 case MVT::v8i64: return "MVT::v8i64"; in getEnumName()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
HDHexagonISelDAGToDAG.cpp111 case MVT::v8i64: in SelectIndexedLoad()
501 case MVT::v8i64: in SelectIndexedStore()
HDHexagonInstrInfo.cpp2663 case MVT::v8i64: in isValidAutoIncImm()
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/IR/
HDIntrinsics.td268 def llvm_v8i64_ty : LLVMType<v8i64>; // 8 x i64