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Searched refs:v64i8 (Results 1 – 23 of 23) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
HDHexagonCallingConv.td85 CCIfType<[v16i32,v32i16,v64i8],
91 CCIfType<[v16i32,v32i16,v64i8],
117 CCIfType<[v16i32,v32i16,v64i8],
HDHexagonIntrinsics.td288 def : Pat <(v512i1 (bitconvert (v64i8 HvxVR:$src1))),
289 (v512i1 (V6_vandvrt (v64i8 HvxVR:$src1), (A2_tfrsi 0x01010101)))>,
300 def : Pat <(v64i8 (bitconvert (v512i1 HvxQR:$src1))),
301 (v64i8 (V6_vandqrt (v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>,
HDHexagonIntrinsicsV60.td34 def : Pat <(v512i1 (bitconvert (v64i8 HvxVR:$src1))),
35 (v512i1 (V6_vandvrt(v64i8 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
43 def : Pat <(v64i8 (bitconvert (v512i1 HvxQR:$src1))),
44 (v64i8 (V6_vandqrt(v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
HDHexagonRegisterInfo.td288 [v64i8, v128i8, v64i8]>;
HDHexagonISelLoweringHVX.cpp16 static const MVT LegalV64[] = { MVT::v64i8, MVT::v32i16, MVT::v16i32 };
25 addRegisterClass(MVT::v64i8, &Hexagon::HvxVRRegClass); in initializeHVXLowering()
61 MVT ByteV = Use64b ? MVT::v64i8 : MVT::v128i8; in initializeHVXLowering()
201 for (MVT T: {MVT::v64i8, MVT::v64i16, MVT::v32i8, MVT::v32i16, MVT::v32i32}) in initializeHVXLowering()
HDHexagonISelDAGToDAG.cpp108 case MVT::v64i8: in SelectIndexedLoad()
498 case MVT::v64i8: in SelectIndexedStore()
HDHexagonPatternsHVX.td359 def: Pat<(VecI16 (sext_inreg HVI16:$Vs, v64i8)),
HDHexagonInstrInfo.cpp2660 case MVT::v64i8: in isValidAutoIncImm()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
HDX86TargetTransformInfo.cpp291 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand. in getArithmeticInstrCost()
292 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand. in getArithmeticInstrCost()
293 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb. in getArithmeticInstrCost()
350 { ISD::SDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence in getArithmeticInstrCost()
351 { ISD::SREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence in getArithmeticInstrCost()
352 { ISD::UDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence in getArithmeticInstrCost()
353 { ISD::UREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence in getArithmeticInstrCost()
510 { ISD::SHL, MVT::v64i8, 11 }, // vpblendvb sequence. in getArithmeticInstrCost()
511 { ISD::SRL, MVT::v64i8, 11 }, // vpblendvb sequence. in getArithmeticInstrCost()
512 { ISD::SRA, MVT::v64i8, 24 }, // vpblendvb sequence. in getArithmeticInstrCost()
[all …]
HDX86CallingConv.td120 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
150 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
195 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
231 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
248 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
539 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
557 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
577 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
624 CCIfType<[v64i8, v32i16, v16i32, v16f32, v8f64, v8i64], CCPassIndirect<i64>>,
689 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
[all …]
HDX86InstrVecCompiler.td87 defm : subvector_subreg_lowering<VR128, v16i8, VR512, v64i8, sub_xmm>;
98 defm : subvector_subreg_lowering<VR256, v32i8, VR512, v64i8, sub_ymm>;
136 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v64i8, v16i8, v16i32, sub_xmm>;
143 defm : subvec_zero_lowering<"DQA64Z256", VR256X, v64i8, v32i8, v16i32, sub_ymm>;
152 defm : subvec_zero_lowering<"DQA", VR128, v64i8, v16i8, v16i32, sub_xmm>;
159 defm : subvec_zero_lowering<"DQAY", VR256, v64i8, v32i8, v16i32, sub_ymm>;
HDX86InstrFragmentsSIMD.td813 def loadv64i8 : PatFrag<(ops node:$ptr), (v64i8 (load node:$ptr))>;
875 (v64i8 (alignedload node:$ptr))>;
998 def bc_v64i8 : PatFrag<(ops node:$in), (v64i8 (bitconvert node:$in))>;
HDX86RegisterInfo.td577 def VR512 : RegisterClass<"X86", [v16f32, v8f64, v64i8, v32i16, v16i32, v8i64],
581 def VR512_0_15 : RegisterClass<"X86", [v16f32, v8f64, v64i8, v32i16, v16i32, v8i64],
HDX86ISelLowering.cpp1542 for (auto VT : {MVT::v16i32, MVT::v8i64, MVT::v64i8}) { in X86TargetLowering()
1629 setOperationAction(ISD::BITCAST, MVT::v64i8, Custom); in X86TargetLowering()
1769 addRegisterClass(MVT::v64i8, &X86::VR512RegClass); in X86TargetLowering()
1772 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom); in X86TargetLowering()
1773 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom); in X86TargetLowering()
1774 setOperationAction(ISD::ANY_EXTEND, MVT::v64i8, Custom); in X86TargetLowering()
1777 setOperationAction(ISD::MUL, MVT::v64i8, Custom); in X86TargetLowering()
1780 setOperationAction(ISD::MULHS, MVT::v64i8, Custom); in X86TargetLowering()
1781 setOperationAction(ISD::MULHU, MVT::v64i8, Custom); in X86TargetLowering()
1783 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i8, Custom); in X86TargetLowering()
[all …]
HDX86InstrAVX512.td417 def : Pat<(v64i8 immAllZerosV), (AVX512_512_SET0)>;
940 def : Pat<(v16i8 (extract_subvector (v64i8 VR512:$src), (iPTR 16))),
942 (v32i8 (EXTRACT_SUBREG (v64i8 VR512:$src), sub_ymm)),
969 def : Pat<(v16i8 (extract_subvector (v64i8 VR512:$src), (iPTR 16))),
971 (v32i8 (EXTRACT_SUBREG (v64i8 VR512:$src), sub_ymm)),
1485 def : Pat<(v64i8 (X86SubVBroadcast (loadv32i8 addr:$src))),
1505 def : Pat<(v64i8 (X86SubVBroadcast (v32i8 VR256X:$src))),
1506 (VINSERTI64x4Zrr (INSERT_SUBREG (v64i8 (IMPLICIT_DEF)), VR256X:$src, sub_ymm),
1515 def : Pat<(v64i8 (X86SubVBroadcast (loadv16i8 addr:$src))),
3741 def : Pat<(alignedstore (v64i8 VR512:$src), addr:$dst),
[all …]
HDX86ISelDAGToDAG.cpp4037 case MVT::v64i8: in getVPTESTMOpc()
4084 case MVT::v64i8: in getVPTESTMOpc()
4114 case MVT::v64i8: in getVPTESTMOpc()
4161 case MVT::v64i8: in getVPTESTMOpc()
HDX86FastISel.cpp457 case MVT::v64i8: in X86FastEmitLoad()
629 case MVT::v64i8: in X86FastEmitStore()
HDX86InstrCompiler.td646 def : Pat<(v64i8 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)),
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Support/
HDMachineValueType.h78 v64i8 = 31, // 64 x i8 enumerator
369 SimpleTy == MVT::v64i8 || SimpleTy == MVT::v32i16 || in is512BitVector()
451 case v64i8: in getVectorElementType()
569 case v64i8: in getVectorNumElements()
791 case v64i8: in getSizeInBits()
942 if (NumElements == 64) return MVT::v64i8; in getVectorVT()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
HDValueTypes.cpp176 case MVT::v64i8: return VectorType::get(Type::getInt8Ty(Context), 64); in getTypeForEVT()
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
HDValueTypes.td53 def v64i8 : ValueType<512, 31>; // 64 x i8 vector value
/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/
HDCodeGenTarget.cpp96 case MVT::v64i8: return "MVT::v64i8"; in getEnumName()
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/IR/
HDIntrinsics.td244 def llvm_v64i8_ty : LLVMType<v64i8>; // 64 x i8