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Searched refs:v2f32 (Results 1 – 25 of 43) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
HDAArch64TargetTransformInfo.cpp326 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, in getCastInstrCost()
329 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, in getCastInstrCost()
334 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, in getCastInstrCost()
335 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 }, in getCastInstrCost()
336 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 }, in getCastInstrCost()
337 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, in getCastInstrCost()
338 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 }, in getCastInstrCost()
339 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 }, in getCastInstrCost()
367 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f32, 1 }, in getCastInstrCost()
370 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 }, in getCastInstrCost()
[all …]
HDAArch64CallingConvention.td31 CCIfType<[v2f32], CCBitConvertToType<v2i32>>,
36 CCIfBigEndian<CCIfType<[v2i32, v2f32, v4i16, v4f16, v8i8],
109 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],
118 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16],
127 CCIfType<[v2f32], CCBitConvertToType<v2i32>>,
135 CCIfBigEndian<CCIfType<[v2i32, v2f32, v4i16, v4f16, v8i8],
151 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],
188 CCIfType<[v2f32], CCBitConvertToType<v2i32>>,
226 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],
242 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16],
[all …]
HDAArch64ISelDAGToDAG.cpp1841 if ((VT != MVT::v2f64 || NarrowVT != MVT::v2f32) && in tryHighFPExt()
3194 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) { in Select()
3221 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) { in Select()
3248 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) { in Select()
3275 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) { in Select()
3302 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) { in Select()
3329 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) { in Select()
3356 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) { in Select()
3383 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) { in Select()
3410 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) { in Select()
[all …]
HDAArch64InstrInfo.td811 def : Pat<(v2f32 (int_aarch64_neon_vcadd_rot90 (v2f32 V64:$Rn), (v2f32 V64:$Rm))),
812 (FCADDv2f32 (v2f32 V64:$Rn), (v2f32 V64:$Rm), (i32 0))>;
813 def : Pat<(v2f32 (int_aarch64_neon_vcadd_rot270 (v2f32 V64:$Rn), (v2f32 V64:$Rm))),
814 (FCADDv2f32 (v2f32 V64:$Rn), (v2f32 V64:$Rm), (i32 1))>;
2101 defm : ScalToVecROLoadPat<ro32, load, f32, v2f32, LDRSroW, LDRSroX, ssub>;
2135 defm : VecROLoadPat<ro64, v2f32, LDRDroW, LDRDroX>;
2274 def : Pat<(v2f32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
2458 def : Pat<(v2f32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
2797 defm : VecROStorePat<ro64, v2f32, FPR64, STRDroW, STRDroX>;
2888 def : Pat<(store (v2f32 FPR64:$Rt),
[all …]
HDAArch64SchedA57.td421 // D form - v2f32
429 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FABD|FADD|FSUB)(v2f32|32|64|v2i32p)")>;
434 def : InstRW<[A57Write_5cyc_1V], (instregex "^FADDP(v2f32|32|64|v2i32)")>;
439 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FACGE|FACGT|FCMEQ|FCMGE|FCMGT|FCMLE|FCMLT)(v2f32|32|…
446 def : InstRW<[A57Write_5cyc_1V], (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v2f32|v1i32|v2i32|v1i6…
466 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FMAX|FMIN)(NM)?(v2f32)")>;
470 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FMAX|FMIN)(NM)?P(v2f32|v2i32)")>;
477 def : InstRW<[A57Write_5cyc_1V], (instregex "^FMULX?(v2f32|v1i32|v2i32|v1i64|32|64)")>;
486 def : InstRW<[A57WriteFPVMAD, A57ReadFPVMA5], (instregex "^FML[AS](v2f32|v1i32|v2i32|v1i64)")>;
490 def : InstRW<[A57Write_5cyc_1V], (instregex "^FRINT[AIMNPXZ](v2f32)")>;
[all …]
HDAArch64SchedFalkorDetails.td586 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(FABS|FNEG)v2f32$")>;
588 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^(F(MAX|MIN)(NM)?P?|FAC(GE|GT))(v2f32|v2i32p)$")>;
590 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^FCM(EQ|GE|GT)(32|64|v2f32|v2i32)$")>;
592 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^FRINT(A|I|M|N|P|X|Z)v2f32$")>;
595 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(FABD|FADD|FSUB)v2f32$")>;
596 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^FADDP(v2i32p|v2i64p|v2f32)$")>;
598 def : InstRW<[FalkorWr_1VXVY_4cyc], (instregex "^FCVT(N|M|P|Z|A)(S|U)(v1i32|v1i64|v2f32)$")>;
603 … (instregex "^(FMUL|FMULX)(v2f32|(v1i32_indexed|v2i32_indexed))$")>;
648 … (instregex "^FML(A|S)(v2f32|(v1i32_indexed|v2i32_indexed))$")>;
1159 def : InstRW<[FalkorWr_1VXVY_4cyc], (instregex "^(S|U)CVTF(v1i32|v2i32|v1i64|v2f32|d|s)(_shift)?"…
HDAArch64InstrFormats.td5263 def v2f32 : BaseSIMDThreeSameVector<0, U, {S,0b01}, {0b11,opc}, V64,
5265 [(set (v2f32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
5285 def v2f32 : BaseSIMDThreeSameVector<0, U, {S,0b01}, {0b11,opc}, V64,
5287 [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
5308 def v2f32 : BaseSIMDThreeSameVectorTied<0, U, {S,0b01}, {0b11,opc}, V64,
5310 [(set (v2f32 V64:$dst),
5311 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
5443 v2f32, v4f16, OpNode>;
5704 def v2f32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, 0b00, V64,
5706 [(set (v2f32 V64:$Rd), (OpNode (v2f32 V64:$Rn)))]>;
[all …]
HDAArch64SchedKryoDetails.td147 (instregex "(S|U)CVTF(v1i32|v2i32|v1i64|v2f32|d|s)(_shift)?")>;
621 (instregex "(F(MAX|MIN)(NM)?P?|FAC(GE|GT)|FCM(EQ|GE|GT))(v2f32|v2i32p)")>;
633 (instregex "FABD(32|64|v2f32)")>;
651 (instregex "F(ABS|NEG)v2f32")>;
675 (instregex "(FADD|FSUB|FADDP)v2f32")>;
735 (instregex "FCVT((A|N|M|P)(S|U)|Z(S|U)_Int)(v1i32|v1i64|v2f32)$")>;
747 (instregex "FCVTX?N(v2f32|v4f32|v2i32|v4i16|v4i32|v8i16)$")>;
771 (instregex "FCVTZ(S|U)(v2f32|v1i32|v1i64|v2i32(_shift)?)$")>;
969 (instregex "FRINT(A|I|M|N|P|X|Z)v2f32")>;
HDAArch64GenRegisterBankInfo.def249 // - v2f32 to v2f64
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
HDARMCallingConv.td33 CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
59 CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
74 CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
94 CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
111 CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
168 CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
185 CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
211 CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
233 CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
HDARMInstrNEON.td1087 def : Pat<(vector_insert (v2f32 DPR:$src),
1100 def : Pat<(insert_subvector undef, (v2f32 DPR:$src), (i32 0)),
1388 def : Pat<(v2f32 (ARMvdup (f32 (load addrmode6dup:$addr)))),
2146 def : Pat<(store (extractelt (v2f32 DPR:$src), imm:$lane), addrmode6:$addr),
3331 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
3334 [(set DPR:$Vd, (v2i32 (ARMvcmpz (v2f32 DPR:$Vm), fc)))]> {
4256 v2f32, v2f32, fadd, 1>;
4319 v2f32, v2f32, fmul, 1>;
4329 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
4331 v2f32, fmul>;
[all …]
HDARMTargetTransformInfo.cpp162 { ISD::FP_EXTEND, MVT::v2f32, 2 }, in getCastInstrCost()
246 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, in getCastInstrCost()
247 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, in getCastInstrCost()
248 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 }, in getCastInstrCost()
249 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 }, in getCastInstrCost()
250 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, in getCastInstrCost()
251 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, in getCastInstrCost()
582 {ISD::VECTOR_SHUFFLE, MVT::v2f32, 1}, in getShuffleCost()
604 {ISD::VECTOR_SHUFFLE, MVT::v2f32, 1}, in getShuffleCost()
627 {ISD::VECTOR_SHUFFLE, MVT::v2f32, 1}, in getShuffleCost()
HDARMRegisterInfo.td404 def DPR : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32, v4f16], 64,
425 def DPR_VFP2 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32, v4f16], 64,
432 def DPR_8 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32, v4f16], 64,
HDARMISelLowering.cpp758 addDRTypeForNEON(MVT::v2f32); in ARMTargetLowering()
834 setOperationAction(ISD::FSQRT, MVT::v2f32, Expand); in ARMTargetLowering()
835 setOperationAction(ISD::FSIN, MVT::v2f32, Expand); in ARMTargetLowering()
836 setOperationAction(ISD::FCOS, MVT::v2f32, Expand); in ARMTargetLowering()
837 setOperationAction(ISD::FPOW, MVT::v2f32, Expand); in ARMTargetLowering()
838 setOperationAction(ISD::FLOG, MVT::v2f32, Expand); in ARMTargetLowering()
839 setOperationAction(ISD::FLOG2, MVT::v2f32, Expand); in ARMTargetLowering()
840 setOperationAction(ISD::FLOG10, MVT::v2f32, Expand); in ARMTargetLowering()
841 setOperationAction(ISD::FEXP, MVT::v2f32, Expand); in ARMTargetLowering()
842 setOperationAction(ISD::FEXP2, MVT::v2f32, Expand); in ARMTargetLowering()
[all …]
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Support/
HDMachineValueType.h126 v2f32 = 71, // 2 x f32 enumerator
345 SimpleTy == MVT::v2f32 || SimpleTy == MVT::v1f64); in is64BitVector()
518 case v2f32: in getVectorElementType()
642 case v2f32: in getVectorNumElements()
743 case v2f32: in getSizeInBits()
994 if (NumElements == 2) return MVT::v2f32; in getVectorVT()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
HDSIInstructions.td841 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
844 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
994 def : BitConvert <v2i32, v2f32, VReg_64>;
995 def : BitConvert <v2f32, v2i32, VReg_64>;
998 def : BitConvert <i64, v2f32, VReg_64>;
999 def : BitConvert <v2f32, i64, VReg_64>;
1000 def : BitConvert <f64, v2f32, VReg_64>;
1001 def : BitConvert <v2f32, f64, VReg_64>;
1013 def : BitConvert <v2f32, v4f16, VReg_64>;
1014 def : BitConvert <v4f16, v2f32, VReg_64>;
[all …]
HDR600RegisterInfo.td248 def R600_Reg64 : RegisterClass<"AMDGPU", [v2f32, v2i32, i64, f64], 64,
251 def R600_Reg64Vertical : RegisterClass<"AMDGPU", [v2f32, v2i32], 64,
HDSIRegisterInfo.td462 def SGPR_64 : RegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, v4i16, v4f16], 32,
480 def SReg_64_XEXEC : RegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, i1, v4i16, v4f16], 32,
486 def SReg_64 : RegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, i1, v4i16, v4f16], 32,
598 def VReg_64 : RegisterClass<"AMDGPU", [i64, f64, v2i32, v2f32, v4f16, v4i16, p0, p1, p4], 32,
654 def AReg_64 : RegisterClass<"AMDGPU", [i64, f64, v2i32, v2f32, v4f16, v4i16], 32,
HDR600Instructions.td1706 def : ExtractVerticalPat <R600_EXTRACT_ELT_V2, v2f32, f32>;
1717 def : InsertVerticalPat <R600_INSERT_ELT_V2, v2f32, f32>;
1770 def : Extract_Element <f32, v2f32, 0, sub0>;
1771 def : Extract_Element <f32, v2f32, 1, sub1>;
1773 def : Insert_Element <f32, v2f32, 0, sub0>;
1774 def : Insert_Element <f32, v2f32, 1, sub1>;
1786 def : BitConvert <v2f32, v2i32, R600_Reg64>;
1787 def : BitConvert <v2i32, v2f32, R600_Reg64>;
HDBUFInstructions.td783 "buffer_load_format_xy", v2f32
795 "buffer_store_format_xy", v2f32
1023 "buffer_atomic_fcmpswap", VReg_64, v2f32, null_frag
1214 defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format, v2f32, "BUFFER_LOAD_FORMAT_XY">;
1241 defm : MUBUF_LoadIntrinsicPat<SIbuffer_load, v2f32, "BUFFER_LOAD_DWORDX2">;
1296 defm : MUBUF_StoreIntrinsicPat<SIbuffer_store_format, v2f32, "BUFFER_STORE_FORMAT_XY">;
1323 defm : MUBUF_StoreIntrinsicPat<SIbuffer_store, v2f32, "BUFFER_STORE_DWORDX2">;
1736 defm : MTBUF_LoadIntrinsicPat<SItbuffer_load, v2f32, "TBUFFER_LOAD_FORMAT_XY">;
1798 defm : MTBUF_StoreIntrinsicPat<SItbuffer_store, v2f32, "TBUFFER_STORE_FORMAT_XY">;
HDAMDGPUCallingConv.td121 CCIfType<[i64, f64, v2i32, v2f32], CCAssignToStack<8, 4>>,
HDAMDGPUISelLowering.cpp73 setOperationAction(ISD::LOAD, MVT::v2f32, Promote); in AMDGPUTargetLowering()
74 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32); in AMDGPUTargetLowering()
153 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, MVT::v2f16, Expand); in AMDGPUTargetLowering()
161 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f32, Expand); in AMDGPUTargetLowering()
173 setOperationAction(ISD::STORE, MVT::v2f32, Promote); in AMDGPUTargetLowering()
174 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32); in AMDGPUTargetLowering()
217 setTruncStoreAction(MVT::v2f32, MVT::v2f16, Expand); in AMDGPUTargetLowering()
227 setTruncStoreAction(MVT::v2f64, MVT::v2f32, Expand); in AMDGPUTargetLowering()
286 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom); in AMDGPUTargetLowering()
399 MVT::v2f32, MVT::v3f32, MVT::v4f32, MVT::v5f32 in AMDGPUTargetLowering()
[all …]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
HDSystemZRegisterInfo.td126 [i64, f64, v8i8, v4i16, v2i32, v2f32], 64,
249 defm VR64 : SystemZRegClass<"VR64", [f64, v8i8, v4i16, v2i32, v2f32], 64,
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/IR/
HDIntrinsicsAMDGPU.td1025 [llvm_any_ty], // overloaded for types f32/i32, v2f32/v2i32, v4f32/v4i32
1041 [llvm_any_ty, // vdata(VGPR), overloaded for types f32/i32, v2f32/v2i32, v4f32/v4i32
1060 [llvm_any_ty], // overloaded for types f32/i32, v2f32/v2i32, v4f32/v4i32
1074 [llvm_any_ty, // vdata(VGPR), overloaded for types f32/i32, v2f32/v2i32, v4f32/v4i32
1087 [llvm_any_ty], // overloaded for types f32/i32, v2f32/v2i32, v4f32/v4i32
1102 [llvm_any_ty, // vdata(VGPR), overloaded for types f32/i32, v2f32/v2i32, v4f32/v4i32
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
HDX86TargetTransformInfo.cpp1303 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, in getCastInstrCost()
1310 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, in getCastInstrCost()
1317 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 1 }, in getCastInstrCost()
1324 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 1 }, in getCastInstrCost()
1380 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 }, in getCastInstrCost()
1387 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 5 }, in getCastInstrCost()
1398 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 }, in getCastInstrCost()

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