| /freebsd-11-stable/sys/sparc64/sparc64/ |
| HD | zeus.c | 56 stxa(AA_DMMU_TSB_PEXT_REG, ASI_DMMU, 0); in zeus_init() 57 stxa(AA_IMMU_TSB_PEXT_REG, ASI_IMMU, 0); in zeus_init() 60 stxa(AA_DMMU_TSB_SEXT_REG, ASI_DMMU, 0); in zeus_init() 66 stxa(AA_DMMU_TSB_NEXT_REG, ASI_DMMU, 0); in zeus_init() 67 stxa(AA_IMMU_TSB_NEXT_REG, ASI_IMMU, 0); in zeus_init() 78 stxa(AA_MCNTL, ASI_MCNTL, val); in zeus_init() 90 stxa(0, ASI_LSU_CTL_REG, lsu | LSU_IC | LSU_DC); in zeus_cache_enable() 131 stxa(TLB_DEMAP_ALL, ASI_DMMU_DEMAP, 0); in zeus_tlb_flush_nonlocked() 132 stxa(TLB_DEMAP_ALL, ASI_IMMU_DEMAP, 0); in zeus_tlb_flush_nonlocked()
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| HD | cheetah.c | 67 stxa(AA_DMMU_TSB_PEXT_REG, ASI_DMMU, 0); in cheetah_init() 68 stxa(AA_IMMU_TSB_PEXT_REG, ASI_IMMU, 0); in cheetah_init() 71 stxa(AA_DMMU_TSB_SEXT_REG, ASI_DMMU, 0); in cheetah_init() 77 stxa(AA_DMMU_TSB_NEXT_REG, ASI_DMMU, 0); in cheetah_init() 78 stxa(AA_IMMU_TSB_NEXT_REG, ASI_IMMU, 0); in cheetah_init() 95 stxa(TLB_DEMAP_ALL, ASI_DMMU_DEMAP, 0); in cheetah_init() 104 stxa(AA_DMMU_PCXR, ASI_DMMU, val); in cheetah_init() 107 stxa(AA_DMMU_SCXR, ASI_DMMU, val); in cheetah_init() 148 stxa(0, ASI_LSU_CTL_REG, lsu | LSU_IC | LSU_DC); in cheetah_cache_enable() 176 stxa(0, ASI_LSU_CTL_REG, lsu & ~(LSU_IC)); in cheetah_cache_flush() [all …]
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| HD | mp_locore.S | 88 stxa %g0, [%l0] ASI_IMMU_DEMAP 109 stxa %l5, [%g0 + AA_IMMU_TAR] %asi 110 stxa %l6, [%l4] ASI_ITLB_DATA_ACCESS_REG 126 stxa %l4, [%g0 + AA_DMMU_TAR] %asi 127 stxa %l5, [%g0] ASI_DTLB_DATA_IN_REG 151 stxa %l4, [%g0 + AA_IMMU_TAR] %asi 152 stxa %l5, [%l0] ASI_ITLB_DATA_ACCESS_REG 158 stxa %l4, [%g0 + AA_IMMU_TAR] %asi 159 stxa %l5, [%g0] ASI_ITLB_DATA_IN_REG 254 stxa %l4, [%g0 + AA_DMMU_TAR] %asi [all …]
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| HD | mp_machdep.c | 591 stxa(AA_SDB_INTR_D0, ASI_SDB_INTR_W, d0); in spitfire_ipi_single() 592 stxa(AA_SDB_INTR_D1, ASI_SDB_INTR_W, d1); in spitfire_ipi_single() 593 stxa(AA_SDB_INTR_D2, ASI_SDB_INTR_W, d2); in spitfire_ipi_single() 595 stxa(AA_INTR_SEND | (mid << IDC_ITID_SHIFT), in spitfire_ipi_single() 639 stxa(AA_SDB_INTR_D0, ASI_SDB_INTR_W, d0); in cheetah_ipi_single() 640 stxa(AA_SDB_INTR_D1, ASI_SDB_INTR_W, d1); in cheetah_ipi_single() 641 stxa(AA_SDB_INTR_D2, ASI_SDB_INTR_W, d2); in cheetah_ipi_single() 643 stxa(AA_INTR_SEND | (mid << IDC_ITID_SHIFT), in cheetah_ipi_single() 681 stxa(AA_SDB_INTR_D0, ASI_SDB_INTR_W, d0); in cheetah_ipi_selected() 682 stxa(AA_SDB_INTR_D1, ASI_SDB_INTR_W, d1); in cheetah_ipi_selected() [all …]
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| HD | tlb.c | 85 stxa(TLB_DEMAP_PRIMARY | TLB_DEMAP_CONTEXT, ASI_DMMU_DEMAP, 0); in tlb_context_demap() 86 stxa(TLB_DEMAP_PRIMARY | TLB_DEMAP_CONTEXT, ASI_IMMU_DEMAP, 0); in tlb_context_demap() 111 stxa(TLB_DEMAP_VA(va) | flags, ASI_DMMU_DEMAP, 0); in tlb_page_demap() 112 stxa(TLB_DEMAP_VA(va) | flags, ASI_IMMU_DEMAP, 0); in tlb_page_demap() 139 stxa(TLB_DEMAP_VA(va) | flags, ASI_DMMU_DEMAP, 0); in tlb_range_demap() 140 stxa(TLB_DEMAP_VA(va) | flags, ASI_IMMU_DEMAP, 0); in tlb_range_demap()
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| HD | mp_exception.S | 83 stxa %g1, [%g2] ASI_DCACHE_TAG 123 stxa %g1, [%g2] ASI_ICACHE_TAG 152 1: stxa %g0, [%g1] ASI_DCACHE_INVALIDATE 212 stxa %g0, [%g2] ASI_DMMU_DEMAP 213 stxa %g0, [%g2] ASI_IMMU_DEMAP 249 stxa %g0, [%g4] ASI_DMMU_DEMAP 250 stxa %g0, [%g4] ASI_IMMU_DEMAP 279 stxa %g0, [%g1] ASI_DMMU_DEMAP 280 stxa %g0, [%g1] ASI_IMMU_DEMAP
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| HD | exception.S | 299 stxa %g0, [%g0 + AA_DMMU_SFSR] %asi 512 stxa %g0, [%g0 + AA_IMMU_SFSR] %asi 524 stxa %g0, [%g0 + AA_DMMU_SFSR] %asi 535 stxa %g0, [%g0 + AA_DMMU_SFSR] %asi 678 stxa %g1, [%g0 + AA_IMMU_TAR] %asi 679 stxa %g7, [%g0] ASI_ITLB_DATA_IN_REG 721 stxa %g1, [%g0 + AA_IMMU_TAR] %asi 722 stxa %g2, [%g0] ASI_ITLB_DATA_IN_REG 732 stxa %g1, [%g0 + AA_IMMU_TAR] %asi 836 stxa %g1, [%g0 + AA_DMMU_TAR] %asi [all …]
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| HD | interrupt.S | 78 stxa %g0, [%g0] ASI_INTR_RECEIVE 173 stxa %g0, [%g0] ASI_INTR_RECEIVE
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| HD | swtch.S | 277 stxa %i4, [%i5] ASI_DMMU 279 stxa %i4, [%i5] ASI_IMMU 286 stxa %i3, [%i5] ASI_DMMU
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| HD | pmap.c | 726 stxa(AA_DMMU_TAR, ASI_DMMU, TLB_TAR_VA(va) | in pmap_map_tsb() 740 stxa(AA_DMMU_SCXR, ASI_DMMU, (ldxa(AA_DMMU_SCXR, ASI_DMMU) & in pmap_set_kctx() 781 stxa((vm_paddr_t)tp + offsetof(struct tte, tte_vpn), in pmap_bootstrap_set_tte() 783 stxa((vm_paddr_t)tp + offsetof(struct tte, tte_data), in pmap_bootstrap_set_tte() 2001 stxa(TLB_DEMAP_VA(addr) | TLB_DEMAP_NUCLEUS | TLB_DEMAP_PAGE, ASI_DMMU_DEMAP, 0); in pmap_quick_remove_page() 2002 stxa(TLB_DEMAP_VA(addr) | TLB_DEMAP_NUCLEUS | TLB_DEMAP_PAGE, ASI_IMMU_DEMAP, 0); in pmap_quick_remove_page() 2334 stxa(AA_DMMU_TSB, ASI_DMMU, pm->pm_tsb); in pmap_activate() 2335 stxa(AA_IMMU_TSB, ASI_IMMU, pm->pm_tsb); in pmap_activate() 2336 stxa(AA_DMMU_PCXR, ASI_DMMU, (ldxa(AA_DMMU_PCXR, ASI_DMMU) & in pmap_activate()
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| HD | machdep.c | 446 stxa(TLB_DEMAP_VA(va) | TLB_DEMAP_PRIMARY | TLB_DEMAP_PAGE, in sparc64_init() 448 stxa(TLB_DEMAP_VA(va) | TLB_DEMAP_PRIMARY | TLB_DEMAP_PAGE, in sparc64_init()
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| HD | support.S | 485 stxa %o1, [%o0] ASI_AIUP 896 stxa %g0, [%l3] ASI_DMMU
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| /freebsd-11-stable/stand/sparc64/loader/ |
| HD | main.c | 222 stxa(AA_DMMU_PWPR, ASI_DMMU, pa & (((2UL << 38) - 1) << 3)); in watch_phys_set_mask() 226 stxa(0, ASI_LSU_CTL_REG, lsucr); in watch_phys_set_mask() 248 stxa(AA_DMMU_VWPR, ASI_DMMU, va & (((2UL << 41) - 1) << 3)); in watch_virt_set_mask() 252 stxa(0, ASI_LSU_CTL_REG, lsucr); in watch_virt_set_mask() 494 stxa(TLB_DEMAP_VA(TLB_TAR_VA(tag)) | TLB_DEMAP_PRIMARY | in itlb_relocate_locked0_sun4u() 506 stxa(AA_IMMU_TAR, ASI_IMMU, tag); in itlb_relocate_locked0_sun4u() 507 stxa(TLB_DAR_SLOT(tlb_locked, i), ASI_ITLB_DATA_ACCESS_REG, in itlb_relocate_locked0_sun4u()
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| /freebsd-11-stable/sys/sparc64/include/ |
| HD | cpufunc.h | 130 STNC_GEN(u_long, stxa); 139 #define stxa(va, asi, val) ST_GENERIC(va, asi, val, stxa) macro
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