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Searched refs:isKill (Results 1 – 25 of 131) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/
HDAVRExpandPseudoInsts.cpp148 bool DstIsKill = MI.getOperand(1).isKill(); in expandArith()
149 bool SrcIsKill = MI.getOperand(2).isKill(); in expandArith()
181 bool DstIsKill = MI.getOperand(1).isKill(); in expandLogic()
182 bool SrcIsKill = MI.getOperand(2).isKill(); in expandLogic()
227 bool SrcIsKill = MI.getOperand(1).isKill(); in expandLogicImm()
279 bool SrcIsKill = MI.getOperand(1).isKill(); in expand()
331 bool SrcIsKill = MI.getOperand(1).isKill(); in expand()
394 bool DstIsKill = MI.getOperand(1).isKill(); in expand()
424 bool DstIsKill = MI.getOperand(0).isKill(); in expand()
425 bool SrcIsKill = MI.getOperand(1).isKill(); in expand()
[all …]
HDAVRRelaxMemOperations.cpp112 .addReg(Src.getReg(), getKillRegState(Src.isKill())); in relax()
116 .addReg(Ptr.getReg(), getKillRegState(Ptr.isKill())); in relax()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
HDTwoAddressInstructionPass.cpp266 if (!UseMO.isKill()) in sink3AddrInstruction()
308 if (MO.isKill() || (LIS && isPlainlyKilled(&OtherMI, MOReg, LIS))) { in sink3AddrInstruction()
920 if (MOReg != Reg && (MO.isKill() || in rescheduleMIBelowKill()
972 bool isKill = in rescheduleMIBelowKill() local
973 MO.isKill() || (LIS && isPlainlyKilled(&OtherMI, MOReg, LIS)); in rescheduleMIBelowKill()
974 if (MOReg != Reg && ((isKill && regOverlapsSet(Uses, MOReg, TRI)) || in rescheduleMIBelowKill()
978 if (MOReg == Reg && !isKill) in rescheduleMIBelowKill()
1101 bool isKill = MO.isKill() || (LIS && isPlainlyKilled(KillMI, MOReg, LIS)); in rescheduleKillAboveMI() local
1102 if (MOReg == Reg && !isKill) in rescheduleKillAboveMI()
1105 if (isKill && MOReg != Reg) in rescheduleKillAboveMI()
[all …]
HDMachineInstrBundle.cpp164 if (MO.isKill()) in finalizeBundle()
173 if (MO.isKill()) in finalizeBundle()
223 bool isKill = KilledUseSet.count(Reg); in finalizeBundle() local
225 MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) | in finalizeBundle()
341 if (MO.isKill()) in AnalyzePhysRegInBundle()
HDExpandPostRAPseudos.cpp121 MI->getOperand(2).isKill()); in LowerSubregToReg()
167 DstMO.getReg(), SrcMO.getReg(), SrcMO.isKill()); in LowerCopy()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
HDPPCVSXFMAMutate.cpp192 if (LIS->getInterval(Reg2).Query(FMAIdx).isKill() in processBlock()
196 } else if (LIS->getInterval(Reg3).Query(FMAIdx).isKill() in processBlock()
225 bool AddRegKill = AddendMI->getOperand(1).isKill(); in processBlock()
226 bool KilledProdRegKill = MI.getOperand(KilledProdOp).isKill(); in processBlock()
227 bool OtherProdRegKill = MI.getOperand(OtherProdOp).isKill(); in processBlock()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
HDMipsInstrInfo.h114 unsigned SrcReg, bool isKill, int FrameIndex, in storeRegToStackSlot() argument
117 storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0); in storeRegToStackSlot()
130 unsigned SrcReg, bool isKill, int FrameIndex,
HDMipsSEFrameLowering.cpp193 .addReg(Src, getKillRegState(I->getOperand(0).isKill())); in expandStoreCCond()
235 unsigned SrcKill = getKillRegState(I->getOperand(0).isKill()); in expandStoreACC()
267 unsigned SrcKill = getKillRegState(I->getOperand(1).isKill()); in expandCopyACC()
326 TII.storeRegToStack(MBB, I, LoReg, I->getOperand(1).isKill(), FI, RC, in expandBuildPairF64()
328 TII.storeRegToStack(MBB, I, HiReg, I->getOperand(2).isKill(), FI, RC, in expandBuildPairF64()
390 TII.storeRegToStack(MBB, I, SrcReg, Op1.isKill(), FI, RC, &RegInfo, 0); in expandExtractElementF64()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
HDSparcInstrInfo.cpp396 unsigned SrcReg, bool isKill, int FI, in storeRegToStackSlot() argument
411 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
414 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
417 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
420 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
423 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
428 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
HDSparcInstrInfo.h89 unsigned SrcReg, bool isKill, int FrameIndex,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/XCore/
HDXCoreRegisterInfo.cpp77 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertFPImmInst()
113 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertFPConstInst()
147 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertSPImmInst()
190 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertSPConstInst()
HDXCoreInstrInfo.h71 unsigned SrcReg, bool isKill, int FrameIndex,
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
HDMachineOperand.h388 bool isKill() const { in isKill() function
754 bool isKill = false, bool isDead = false,
780 bool isKill = false, bool isDead = false,
787 assert(!(isKill && isDef) && "Kill flag on def");
791 Op.IsDeadOrKill = isKill | isDead;
HDMachineInstr.h1083 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
1245 int findRegisterUseOperandIdx(Register Reg, bool isKill = false,
1250 MachineOperand *findRegisterUseOperand(Register Reg, bool isKill = false,
1252 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
1257 Register Reg, bool isKill = false,
1260 findRegisterUseOperand(Reg, isKill, TRI);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
HDMSP430InstrInfo.cpp38 unsigned SrcReg, bool isKill, int FrameIdx, in storeRegToStackSlot() argument
54 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
58 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
HDMSP430InstrInfo.h44 unsigned SrcReg, bool isKill,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
HDThumb1InstrInfo.cpp79 unsigned SrcReg, bool isKill, int FI, in storeRegToStackSlot() argument
97 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
HDThumb1InstrInfo.h45 unsigned SrcReg, bool isKill, int FrameIndex,
HDThumb1FrameLowering.cpp855 bool isKill = !MRI.isLiveIn(Reg); in spillCalleeSavedRegisters() local
856 if (isKill && !MRI.isReserved(Reg)) in spillCalleeSavedRegisters()
859 MIB.addReg(Reg, getKillRegState(isKill)); in spillCalleeSavedRegisters()
899 bool isKill = !MRI.isLiveIn(*HiRegToSave); in spillCalleeSavedRegisters() local
900 if (isKill && !MRI.isReserved(*HiRegToSave)) in spillCalleeSavedRegisters()
906 .addReg(*HiRegToSave, getKillRegState(isKill)) in spillCalleeSavedRegisters()
HDThumb2InstrInfo.h47 unsigned SrcReg, bool isKill, int FrameIndex,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
HDX86InstrBuilder.h158 unsigned Reg, bool isKill, int Offset) { in addRegOffset() argument
159 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); in addRegOffset()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
HDHexagonCopyToCombine.cpp240 if (!Op.isReg() || Op.getReg() != RegNotKilled || !Op.isKill()) in removeKillInfo()
762 unsigned LoRegKillFlag = getKillRegState(LoOperand.isKill()); in emitCombineIR()
809 unsigned HiRegKillFlag = getKillRegState(HiOperand.isKill()); in emitCombineRI()
858 unsigned LoRegKillFlag = getKillRegState(LoOperand.isKill()); in emitCombineRR()
859 unsigned HiRegKillFlag = getKillRegState(HiOperand.isKill()); in emitCombineRR()
HDHexagonNewValueJump.cpp660 if (!Op.isReg() || !Op.isUse() || !Op.isKill()) in runOnMachineFunction()
707 cmpInstr->getOperand(0).isKill()) in runOnMachineFunction()
710 cmpInstr->getOperand(1).isKill()) in runOnMachineFunction()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/
HDBPFInstrInfo.h40 bool isKill, int FrameIndex,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
HDAArch64SIMDInstrOpt.cpp431 unsigned Src0IsKill = getKillRegState(MI.getOperand(1).isKill()); in optimizeVectElement()
433 unsigned Src1IsKill = getKillRegState(MI.getOperand(2).isKill()); in optimizeVectElement()
439 unsigned Src2IsKill = getKillRegState(MI.getOperand(3).isKill()); in optimizeVectElement()
639 StRegKill[i] = getKillRegState(DefiningMI->getOperand(2*i+1).isKill()); in processSeqRegInst()

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