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Searched refs:isInConsecutiveRegs (Results 1 – 5 of 5) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
HDTargetCallingConv.h110 bool isInConsecutiveRegs() const { return IsInConsecutiveRegs; } in isInConsecutiveRegs() function
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
HDWebAssemblyISelLowering.cpp728 if (Out.Flags.isInConsecutiveRegs()) in LowerCall()
836 if (In.Flags.isInConsecutiveRegs()) in LowerCall()
896 if (Out.Flags.isInConsecutiveRegs()) in LowerReturn()
924 if (In.Flags.isInConsecutiveRegs()) in LowerFormalArguments()
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Target/
HDTargetCallingConv.td61 class CCIfConsecutiveRegs<CCAction A> : CCIf<"ArgFlags.isInConsecutiveRegs()", A> {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
HDPPCISelLowering.cpp3353 if (!Flags.isInConsecutiveRegs()) in CalculateStackSlotSize()
3390 if (Flags.isInConsecutiveRegs()) { in CalculateStackSlotAlignment()
4050 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize; in LowerFormalArguments_64SVR4()
6265 } else if (!Flags.isInConsecutiveRegs()) { in LowerCall_64SVR4()
6301 !isLittleEndian && !Flags.isInConsecutiveRegs()) { in LowerCall_64SVR4()
6319 Flags.isInConsecutiveRegs()) ? 4 : 8; in LowerCall_64SVR4()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
HDAArch64ISelLowering.cpp3459 !Ins[i].Flags.isInConsecutiveRegs()) in LowerFormalArguments()
4151 !Flags.isInConsecutiveRegs()) { in LowerCall()