Searched refs:imm6 (Results 1 – 12 of 12) sorted by relevance
295 uint16_t imm6 = extractBits(val, 6, 6) << 7; in relocateOne() local299 insn |= imm11 | imm4 | imm9_8 | imm10 | imm6 | imm7 | imm3_1 | imm5; in relocateOne()
122 imm3, imm4, imm5, imm6, imm16, imm20, imm32, enumerator
147 SHIFT_INST_A("ashud", 0x26, 0x48, 25, imm6, regp),157 SHIFT_INST_L("lshd", 0x25, 0x47, 25, imm6, regp),
4021 let Inst{21-19} = 0b001; // imm6 = 001xxx4025 let Inst{21-20} = 0b01; // imm6 = 01xxxx4029 let Inst{21} = 0b1; // imm6 = 1xxxxx4033 // imm6 = xxxxxx4038 let Inst{21-19} = 0b001; // imm6 = 001xxx4042 let Inst{21-20} = 0b01; // imm6 = 01xxxx4046 let Inst{21} = 0b1; // imm6 = 1xxxxx4050 // imm6 = xxxxxx4058 let Inst{21-19} = 0b001; // imm6 = 001xxx4062 let Inst{21-20} = 0b01; // imm6 = 01xxxx[all …]
310 // other shift immediates. The imm6 field is encoded like so:313 // 8 imm6<5:3> = '001', 8 - <imm> is encoded in imm6<2:0>314 // 16 imm6<5:4> = '01', 16 - <imm> is encoded in imm6<3:0>315 // 32 imm6<5> = '1', 32 - <imm> is encoded in imm6<4:0>316 // 64 64 - <imm> is encoded in imm6<5:0>
3428 (outs MQPR:$Qd), (ins MQPR:$Qm, imm_operand_type:$imm6),3429 "$Qd, $Qm, $imm6", vpred_r, "", pattern> {3431 bits<6> imm6;3437 let Inst{19-16} = imm6{3-0};3464 let Inst{20} = imm6{4};
1991 : I<(outs GPR64sp:$Rd), (ins GPR64sp:$Rn, simm6_32b:$imm6),1992 asm, "\t$Rd, $Rn, $imm6",1997 bits<6> imm6;2003 let Inst{10-5} = imm6;2008 : I<(outs GPR64:$Rd), (ins simm6_32b:$imm6),2009 asm, "\t$Rd, $imm6",2013 bits<6> imm6;2019 let Inst{10-5} = imm6;5697 : I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, immtype:$imm6),5698 asm, "\t$Zt, $Pg/z, [$Rn, $imm6]",[all …]
850 // {5-0} - imm6880 // {5-0} - imm6910 // {5-0} - imm6: #0, #8, #16, or #24919 // {5-0} - imm6: #0 or #8949 // {5-0} - imm6: #0 or #122473 isSub, 0, GPR64sp, asm_inst, "\t$Rd, $Rn, $imm6, $imm4",2474 (ins GPR64sp:$Rn, uimm6s16:$imm6, imm0_15:$imm4),2475 (set GPR64sp:$Rd, (OpNode GPR64sp:$Rn, imm0_63:$imm6, imm0_15:$imm4))> {2476 bits<6> imm6;2480 let Inst{21-16} = imm6;
1495 def : Pat<(int_aarch64_addg (am_indexedu6s128 GPR64sp:$Rn, uimm6s16:$imm6), imm0_15:$imm4),1496 (ADDG GPR64sp:$Rn, imm0_63:$imm6, imm0_15:$imm4)>;1539 : Pseudo<(outs GPR64sp:$Rd), (ins GPR64sp:$Rn, uimm6s16:$imm6, GPR64sp:$Rm, imm0_15:$imm4), []>,
225 // Addressing mode pattern reg+imm6
6553 unsigned imm6 = fieldFromInstruction(Insn, 16, 6); in DecodeMVEVCVTt1fp() local6559 if (!Check(S, DecodeVCVTImmOperand(Inst, imm6, Address, Decoder))) in DecodeMVEVCVTt1fp()
2851 uint32_t imm6 = Bits32(opcode, 21, 16); in EmulateB() local2856 (S << 20) | (J2 << 19) | (J1 << 18) | (imm6 << 12) | (imm11 << 1); in EmulateB()