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Searched refs:getSubClassWithSubReg (Results 1 – 21 of 21) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
HDX86RegisterInfo.h70 getSubClassWithSubReg(const TargetRegisterClass *RC,
HDX86RegisterInfo.cpp87 X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, in getSubClassWithSubReg() function in X86RegisterInfo
95 return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx); in getSubClassWithSubReg()
104 A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi); in getMatchingSuperRegClass()
HDX86InstructionSelector.cpp756 SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubIdx); in selectTruncOrPtrToInt()
1219 SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubIdx); in emitExtractSubreg()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
HDAArch64RegisterInfo.h60 getSubClassWithSubReg(const TargetRegisterClass *RC,
HDAArch64RegisterInfo.cpp103 AArch64RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, in getSubClassWithSubReg() function in AArch64RegisterInfo
112 return AArch64GenRegisterInfo::getSubClassWithSubReg(RC, Idx); in getSubClassWithSubReg()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
HDInstrEmitter.cpp452 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx); in ConstrainForSubReg()
465 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT, isDivergent), SubIdx); in ConstrainForSubReg()
571 SRC = TRI->getSubClassWithSubReg(SRC, SubIdx); in EmitSubregNode()
HDFastISel.cpp2251 MRI.constrainRegClass(Op0, TRI.getSubClassWithSubReg(RC, Idx)); in fastEmitInst_extractsubreg()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
HDSIFormMemoryClauses.cpp167 if (TRI->getSubClassWithSubReg(RC, Idx) != RC) in forAllLanes()
HDSIInstrInfo.h827 assert(RI.getRegSizeInBits(*RI.getSubClassWithSubReg( in getOpSize()
HDAMDGPUInstructionSelector.cpp619 Src0RC = TRI.getSubClassWithSubReg(Src0RC, SubReg); in selectG_INSERT()
1282 SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubRegIdx); in selectG_TRUNC()
HDAMDGPUISelDAGToDAG.cpp601 return Subtarget->getRegisterInfo()->getSubClassWithSubReg(SuperRC, in getOperandRegClass()
HDSIInstrInfo.cpp4290 const TargetRegisterClass *OpRC = RI.getSubClassWithSubReg( in legalizeGenericOperand()
/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/
HDCodeGenRegisters.h380 getSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx) const { in getSubClassWithSubReg() function
HDCodeGenRegisters.cpp1002 CodeGenRegisterClass *BiggestSuperRegRC = getSubClassWithSubReg(SubIdx); in getMatchingSubClassWithSubRegs()
1537 if (RegClass.getSubClassWithSubReg(&SubRegIndex) == nullptr) in computeSubRegLaneMasks()
2230 if (RC->getSubClassWithSubReg(&SubIdx) != RC) in inferMatchingSuperRegClass()
HDCodeGenTarget.cpp311 CodeGenRegisterClass *SubClassWithSubReg = RC.getSubClassWithSubReg(SubIdx); in getSuperRegForSubReg()
HDRegisterInfoEmitter.cpp1475 if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(&Idx)) in runTargetDesc()
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
HDTargetRegisterInfo.h552 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const { in getSubClassWithSubReg() function
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
HDPeepholeOptimizer.cpp475 DstRC = TRI->getSubClassWithSubReg(DstRC, SubIdx); in INITIALIZE_PASS_DEPENDENCY()
485 TRI->getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != nullptr; in INITIALIZE_PASS_DEPENDENCY()
HDSplitKit.cpp564 if (TRI.getSubClassWithSubReg(RC, Idx) != RC) in buildCopy()
HDMachineInstr.cpp911 CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx); in getRegClassConstraintEffect()
HDMachineVerifier.cpp1772 TRI->getSubClassWithSubReg(RC, SubIdx); in visitMachineOperand()