| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| HD | SDNodeDbgValue.h | 121 unsigned getOrder() const { return Order; } in getOrder() function 161 unsigned getOrder() const { return Order; } in getOrder() function
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| HD | ScheduleDAGSDNodes.cpp | 745 unsigned DVOrder = DV->getOrder(); in ProcessSDDbgValues() 943 return LHS->getOrder() < RHS->getOrder(); in EmitSchedule() 956 if ((*DI)->getOrder() < LastOrder || (*DI)->getOrder() >= Order) in EmitSchedule() 982 assert((*DI)->getOrder() >= LastOrder && in EmitSchedule() 1004 (*DLI)->getOrder() >= LastOrder && (*DLI)->getOrder() < Order; in EmitSchedule()
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| HD | SelectionDAGDumper.cpp | 773 OS << " DbgVal(Order=" << getOrder() << ')'; in print()
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| HD | SelectionDAG.cpp | 8208 std::max(ToNode->getIROrder(), Dbg->getOrder())); in transferDbgValues() 8248 DV->isIndirect(), DV->getDebugLoc(), DV->getOrder()); in salvageDebugInfo()
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| /freebsd-11-stable/stand/ficl/ |
| HD | search.c | 110 static void getOrder(FICL_VM *pVM) in getOrder() function 371 dictAppendWord(dp, "get-order", getOrder, FW_DEFAULT); in ficlCompileSearch()
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| HD | AllocationOrder.cpp | 36 Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); in AllocationOrder()
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| HD | AllocationOrder.h | 49 ArrayRef<MCPhysReg> getOrder() const { return Order; } in getOrder() function
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| HD | RegAllocBase.cpp | 137 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front()); in allocatePhysRegs()
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| HD | BreakFalseDeps.cpp | 144 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC); in pickBestRegisterForUndef()
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| HD | RegAllocFast.cpp | 716 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in allocVirtReg() 763 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in allocVirtRegUndef()
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| HD | RegAllocGreedy.cpp | 1032 for (auto PhysReg : Order.getOrder()) { in getCheapestEvicteeWeight() 1118 unsigned OrderLimit = Order.getOrder().size(); in tryEvict() 1137 if (TRI->getCostPerUse(Order.getOrder().back()) >= CostPerUseLimit) { in tryEvict() 1550 for (auto PhysReg : Order.getOrder()) { in splitCanCauseLocalSpill()
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| HD | CriticalAntiDepBreaker.cpp | 407 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC); in findSuitableFreeRegister()
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| HD | AggressiveAntiDepBreaker.cpp | 632 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC); in FindSuitableFreeRegisters()
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| /freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| HD | RegisterClassInfo.h | 96 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder() function
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| HD | SIPreAllocateWWMRegs.cpp | 107 for (unsigned PhysReg : RegClassInfo.getOrder(MRI->getRegClass(Reg))) { in processDef()
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| /freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/ |
| HD | RegisterInfoEmitter.cpp | 1038 ArrayRef<Record*> Order = RC.getOrder(); in runMCDesc() 1079 << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits), " in runMCDesc() 1222 ArrayRef<Record*> Order = RC.getOrder(); in runTargetDesc() 1372 ArrayRef<Record*> Elems = RC.getOrder(oi); in runTargetDesc() 1385 if (RC.getOrder(oi).empty()) in runTargetDesc()
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| HD | CodeGenRegisters.h | 426 ArrayRef<Record*> getOrder(unsigned No = 0) const {
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| HD | AsmMatcherEmitter.cpp | 1226 RegisterSet(RC.getOrder().begin(), RC.getOrder().end())); in buildRegisterClasses() 1302 ClassInfo *CI = RegisterSetClasses[RegisterSet(RC.getOrder().begin(), in buildRegisterClasses() 1303 RC.getOrder().end())]; in buildRegisterClasses()
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| HD | AArch64A57FPLoadBalancing.cpp | 519 auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID)); in scavengeRegister()
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| /freebsd-11-stable/contrib/llvm-project/clang/lib/CodeGen/ |
| HD | CGOpenMPRuntime.h | 478 unsigned getOrder() const { return Order; } in getOrder() function
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| HD | CGOpenMPRuntime.cpp | 4129 GetMDInt(Line), GetMDInt(E.getOrder())}; in createOffloadEntriesAndInfoMetadata() 4143 OrderedEntries[E.getOrder()] = std::make_tuple(&E, Loc, ParentName); in createOffloadEntriesAndInfoMetadata() 4144 ParentFunctions[E.getOrder()] = ParentName; in createOffloadEntriesAndInfoMetadata() 4168 GetMDInt(E.getFlags()), GetMDInt(E.getOrder())}; in createOffloadEntriesAndInfoMetadata() 4171 OrderedEntries[E.getOrder()] = in createOffloadEntriesAndInfoMetadata() 4188 StringRef FnName = ParentFunctions[CE->getOrder()]; in createOffloadEntriesAndInfoMetadata()
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| HD | CGAtomic.cpp | 815 llvm::Value *Order = EmitScalarExpr(E->getOrder()); in EmitAtomicExpr()
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| /freebsd-11-stable/contrib/llvm-project/clang/lib/AST/ |
| HD | StmtPrinter.cpp | 1644 PrintExpr(Node->getOrder()); in VisitAtomicExpr()
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| HD | ARMLoadStoreOptimizer.cpp | 587 for (unsigned Reg : RegClassInfo.getOrder(&RegClass)) in findFreeReg()
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| /freebsd-11-stable/contrib/llvm-project/clang/include/clang/AST/ |
| HD | Expr.h | 5890 Expr *getOrder() const { in getOrder() function
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