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Searched refs:getNode (Results 1 – 25 of 184) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
HDDAGCombiner.cpp797 AddToWorklist(Op.getNode()); in deleteAndRecombine()
826 !TLI.isConstTrueVal(N.getOperand(2).getNode()) || in isSetCCEquivalent()
827 !TLI.isConstFalseVal(N.getOperand(3).getNode())) in isSetCCEquivalent()
845 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) in isOneUseSetCC()
854 return N.getNode(); in isConstantFPBuildVectorOrConstantFP()
855 if (ISD::isBuildVectorOfConstantFPSDNodes(N.getNode())) in isConstantFPBuildVectorOrConstantFP()
856 return N.getNode(); in isConstantFPBuildVectorOrConstantFP()
886 ISD::isBuildVectorOfConstantFPSDNodes(V.getNode()); in isAnyConstantBuildVector()
969 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); in reassociateOpsCommutative()
975 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, N0.getOperand(0), N1); in reassociateOpsCommutative()
[all …]
HDLegalizeIntegerTypes.cpp204 if (Res.getNode()) in PromoteIntegerResult()
217 return DAG.getNode(ISD::AssertSext, SDLoc(N), in PromoteIntRes_AssertSext()
224 return DAG.getNode(ISD::AssertZext, SDLoc(N), in PromoteIntRes_AssertZext()
313 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp)); in PromoteIntRes_BITCAST()
317 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp)); in PromoteIntRes_BITCAST()
321 return DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, GetPromotedFloat(InOp)); in PromoteIntRes_BITCAST()
330 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, in PromoteIntRes_BITCAST()
345 InOp = DAG.getNode(ISD::ANY_EXTEND, dl, in PromoteIntRes_BITCAST()
349 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp); in PromoteIntRes_BITCAST()
359 DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp)); in PromoteIntRes_BITCAST()
[all …]
HDLegalizeDAG.cpp225 UpdatedNodes->insert(New.getNode()); in ReplaceNode()
226 ReplacedNode(Old.getNode()); in ReplaceNode()
237 UpdatedNodes->insert(New[i].getNode()); in ReplaceNode()
248 UpdatedNodes->insert(New.getNode()); in ReplaceNodeWithValue()
249 ReplacedNode(Old.getNode()); in ReplaceNodeWithValue()
380 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); in PerformInsertVectorEltInMemory()
406 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, in ExpandINSERT_VECTOR_ELT()
477 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); in OptimizeFloatStore()
496 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) { in LegalizeStoreOps()
530 Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value); in LegalizeStoreOps()
[all …]
HDResourcePriorityQueue.cpp74 const SDNode *ScegN = PredSU->getNode(); in numberRCValPredInSU()
112 const SDNode *ScegN = SuccSU->getNode(); in numberRCValSuccInSU()
131 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in numberRCValSuccInSU()
240 if (!SU || !SU->getNode()) in isResourceAvailable()
245 if (SU->getNode()->getGluedNode()) in isResourceAvailable()
250 if (SU->getNode()->isMachineOpcode()) in isResourceAvailable()
251 switch (SU->getNode()->getMachineOpcode()) { in isResourceAvailable()
254 SU->getNode()->getMachineOpcode()))) in isResourceAvailable()
285 if (!isResourceAvailable(SU) || SU->getNode()->getGluedNode()) { in reserveResources()
290 if (SU->getNode() && SU->getNode()->isMachineOpcode()) { in reserveResources()
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HDLegalizeVectorTypes.cpp175 if (R.getNode()) in ScalarizeVectorResult()
182 return DAG.getNode(N->getOpcode(), SDLoc(N), in ScalarizeVecRes_BinOp()
190 return DAG.getNode(N->getOpcode(), SDLoc(N), in ScalarizeVecRes_TernaryOp()
198 return DAG.getNode(N->getOpcode(), SDLoc(N), Op0.getValueType(), Op0, Op1, in ScalarizeVecRes_FIX()
224 SDValue Result = DAG.getNode(N->getOpcode(), dl, ValueVTs, Opers); in ScalarizeVecRes_StrictFPOp()
252 SDNode *ScalarNode = DAG.getNode( in ScalarizeVecRes_OverflowOp()
253 N->getOpcode(), DL, ScalarVTs, ScalarLHS, ScalarRHS).getNode(); in ScalarizeVecRes_OverflowOp()
261 SDValue OtherVal = DAG.getNode( in ScalarizeVecRes_OverflowOp()
282 return DAG.getNode(ISD::BITCAST, SDLoc(N), in ScalarizeVecRes_BITCAST()
292 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp); in ScalarizeVecRes_BUILD_VECTOR()
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HDLegalizeTypesGeneric.cpp57 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
58 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
68 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
69 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
76 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
77 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
82 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
83 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
93 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
94 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
[all …]
HDTargetLowering.cpp425 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Call.second, in softenSetCCOperands()
427 NewLHS = DAG.getNode(ShouldInvertCC ? ISD::AND : ISD::OR, dl, in softenSetCCOperands()
501 return TLO.New.getNode(); in ShrinkDemandedConstant()
522 SDValue NewOp = TLO.DAG.getNode(Opcode, DL, VT, Op.getOperand(0), NewC); in ShrinkDemandedConstant()
541 assert(Op.getNode()->getNumValues() == 1 && in ShrinkDemandedOp()
553 if (!Op.getNode()->hasOneUse()) in ShrinkDemandedOp()
568 SDValue X = DAG.getNode( in ShrinkDemandedOp()
570 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, Op.getOperand(0)), in ShrinkDemandedOp()
571 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, Op.getOperand(1))); in ShrinkDemandedOp()
573 SDValue Z = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), X); in ShrinkDemandedOp()
[all …]
HDSelectionDAGBuilder.cpp239 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); in getCopyFromParts()
240 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); in getCopyFromParts()
246 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); in getCopyFromParts()
260 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi); in getCopyFromParts()
262 DAG.getNode(ISD::SHL, DL, TotalVT, Hi, in getCopyFromParts()
265 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo); in getCopyFromParts()
266 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi); in getCopyFromParts()
273 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]); in getCopyFromParts()
274 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]); in getCopyFromParts()
277 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); in getCopyFromParts()
[all …]
HDLegalizeVectorOps.cpp256 SDNode *Node = DAG.UpdateNodeOperands(Op.getNode(), Ops); in LegalizeOp()
530 if (!Res.getNode()) in LowerOperationWrapper()
599 Operands[j] = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(j)); in Promote()
601 Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(j)); in Promote()
607 DAG.getNode(Node->getOpcode(), dl, NVT, Operands, Node->getFlags()); in Promote()
612 Res = DAG.getNode(ISD::FP_ROUND, dl, VT, Res, DAG.getIntPtrConstant(0, dl)); in Promote()
614 Res = DAG.getNode(ISD::BITCAST, dl, VT, Res); in Promote()
638 Operands[j] = DAG.getNode(Opc, dl, NVT, Node->getOperand(j)); in PromoteINT_TO_FP()
644 SDValue Res = DAG.getNode(Node->getOpcode(), dl, in PromoteINT_TO_FP()
652 DAG.getNode(Node->getOpcode(), dl, Node->getValueType(0), Operands); in PromoteINT_TO_FP()
[all …]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
HDAMDGPUISelLowering.cpp1025 return DAG.getNode(AMDGPUISD::ENDPGM, DL, MVT::Other, Chain); in LowerReturn()
1057 for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(), in addTokenForArgument()
1058 UE = DAG.getEntryNode().getNode()->use_end(); in addTokenForArgument()
1076 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains); in addTokenForArgument()
1230 SDValue Lo = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Op.getOperand(0)); in LowerCONCAT_VECTORS()
1231 SDValue Hi = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Op.getOperand(1)); in LowerCONCAT_VECTORS()
1234 return DAG.getNode(ISD::BITCAST, SL, VT, BV); in LowerCONCAT_VECTORS()
1283 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS); in combineFMinMaxLegacy()
1284 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS); in combineFMinMaxLegacy()
1302 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS); in combineFMinMaxLegacy()
[all …]
HDR600ISelLowering.cpp493 assert((!Result.getNode() || in LowerOperation()
494 Result.getNode()->getNumValues() == 2) && in LowerOperation()
519 return DAG.getNode(AMDGPUISD::R600_EXPORT, DL, Op.getValueType(), Args); in LowerOperation()
569 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs); in LowerOperation()
573 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
575 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
577 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
579 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
581 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
583 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
[all …]
HDAMDGPUHSAMetadataStreamer.cpp652 Dims.push_back(Dims.getDocument()->getNode( in getWorkGroupDimensions()
659 Version.push_back(Version.getDocument()->getNode(VersionMajor)); in emitVersion()
660 Version.push_back(Version.getDocument()->getNode(VersionMinor)); in emitVersion()
672 Printf.push_back(Printf.getDocument()->getNode( in emitPrintf()
687 Kern[".language"] = Kern.getDocument()->getNode("OpenCL C"); in emitKernelLanguage()
689 LanguageVersion.push_back(Kern.getDocument()->getNode( in emitKernelLanguage()
691 LanguageVersion.push_back(Kern.getDocument()->getNode( in emitKernelLanguage()
704 Kern[".vec_type_hint"] = Kern.getDocument()->getNode( in emitKernelAttrs()
711 Kern[".device_enqueue_symbol"] = Kern.getDocument()->getNode( in emitKernelAttrs()
795 Arg[".name"] = Arg.getDocument()->getNode(Name, /*Copy=*/true); in emitKernelArg()
[all …]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
HDHexagonISelLoweringHVX.cpp214 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, ResTy, IntOps); in getInt()
261 return DAG.getNode(ISD::CONCAT_VECTORS, dl, typeJoin(ty(Ops)), in opJoin()
298 return DAG.getNode(ISD::SHL, dl, MVT::i32, in convertToByteIndex()
314 SDValue SubIdx = DAG.getNode(ISD::AND, dl, MVT::i32, {Idx, Mask}); in getIndexInWord32()
382 if (!SplatV.getNode()) in buildHvxVectorReg()
390 assert(SplatV.getNode()); in buildHvxVectorReg()
391 auto *IdxN = dyn_cast<ConstantSDNode>(SplatV.getNode()); in buildHvxVectorReg()
394 return DAG.getNode(HexagonISD::VSPLATW, dl, VecTy, SplatV); in buildHvxVectorReg()
430 if (Vec.getNode() != nullptr && T.getNode() != Vec.getNode()) in buildHvxVectorReg()
487 SDValue N = DAG.getNode(HexagonISD::VINSERTW0, dl, VecTy, in buildHvxVectorReg()
[all …]
HDHexagonISelDAGToDAG.cpp71 int32_t Inc = cast<ConstantSDNode>(Offset.getNode())->getSExtValue(); in SelectIndexedLoad()
242 SelectStore(TS.getNode()); in StoreInstrForLoadIntrinsic()
243 StoreN = Handle.getValue().getNode(); in StoreInstrForLoadIntrinsic()
273 SDNode *C = Ch.getNode(); in tryLoadOfLoadIntrinsic()
301 if (C->getNumOperands() < 4 || Loc.getNode() != C->getOperand(3).getNode()) in tryLoadOfLoadIntrinsic()
470 int32_t Inc = cast<ConstantSDNode>(Offset.getNode())->getSExtValue(); in SelectIndexedStore()
687 SDValue R = CurDAG->getNode(N->getOpcode(), SDLoc(N), N->getValueType(0), in SelectIntrinsicWOChain()
689 ReplaceNode(N, R.getNode()); in SelectIntrinsicWOChain()
690 SelectCode(R.getNode()); in SelectIntrinsicWOChain()
798 ReplaceNode(N, E.getNode()); in SelectVAlign()
[all …]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
HDARMISelLowering.cpp1999 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerCallResult()
2002 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64); in LowerCallResult()
2003 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, in LowerCallResult()
2016 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerCallResult()
2017 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, in LowerCallResult()
2031 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val); in LowerCallResult()
2049 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()), in LowerMemOpCallTo()
2063 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, in PassF64ArgInRegs()
2072 if (!StackPtr.getNode()) in PassF64ArgInRegs()
2178 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
[all …]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/XCore/
HDXCoreISelLowering.cpp214 case ISD::SUB: return ExpandADDSUB(Op.getNode(), DAG); in LowerOperation()
255 return DAG.getNode(XCoreISD::PCRelativeWrapper, dl, MVT::i32, GA); in getGlobalAddressWrapper()
260 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, GA); in getGlobalAddressWrapper()
262 return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, GA); in getGlobalAddressWrapper()
293 GA = DAG.getNode(ISD::ADD, DL, MVT::i32, GA, Remaining); in LowerGlobalAddress()
318 return DAG.getNode(XCoreISD::PCRelativeWrapper, DL, PtrVT, Result); in LowerBlockAddress()
336 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, Res); in LowerConstantPool()
358 return DAG.getNode(XCoreISD::BR_JT, dl, MVT::Other, Chain, TargetJT, Index); in LowerBR_JT()
361 SDValue ScaledIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index, in LowerBR_JT()
363 return DAG.getNode(XCoreISD::BR_JT32, dl, MVT::Other, Chain, TargetJT, in LowerBR_JT()
[all …]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
HDAArch64ISelLowering.cpp1045 New = TLO.DAG.getNode(Op.getOpcode(), DL, VT, Op.getOperand(0), in optimizeLogicalImm()
1703 return DAG.getNode(Opcode, dl, {VT, MVT::Other}, {Chain, LHS, RHS}); in emitStrictFPComparison()
1715 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, LHS); in emitComparison()
1716 RHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, RHS); in emitComparison()
1719 return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS); in emitComparison()
1747 return DAG.getNode(Opcode, dl, DAG.getVTList(VT, MVT_CC), LHS, RHS) in emitComparison()
1816 LHS = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, LHS); in emitConditionalComparison()
1817 RHS = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, RHS); in emitConditionalComparison()
1835 return DAG.getNode(Opcode, DL, MVT_CC, LHS, RHS, NZCVOp, Condition, CCOp); in emitConditionalComparison()
1938 if (!CCOp.getNode()) in emitConjunctionRec()
[all …]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
HDSystemZSelectionDAGInfo.cpp41 return DAG.getNode(Loop, DL, MVT::Other, Chain, Dst, Src, in emitMemMem()
44 return DAG.getNode(Sequence, DL, MVT::Other, Chain, Dst, Src, in emitMemMem()
103 Dst = DAG.getNode(ISD::ADD, DL, PtrVT, Dst, in EmitTargetCodeForMemset()
108 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chain1, Chain2); in EmitTargetCodeForMemset()
116 SDValue Dst2 = DAG.getNode(ISD::ADD, DL, PtrVT, Dst, in EmitTargetCodeForMemset()
121 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chain1, Chain2); in EmitTargetCodeForMemset()
135 SDValue DstPlus1 = DAG.getNode(ISD::ADD, DL, PtrVT, Dst, in EmitTargetCodeForMemset()
158 return DAG.getNode(SystemZISD::CLC_LOOP, DL, VTs, Chain, Src1, Src2, in emitCLC()
161 return DAG.getNode(SystemZISD::CLC, DL, VTs, Chain, Src1, Src2, in emitCLC()
171 SDValue IPM = DAG.getNode(SystemZISD::IPM, DL, MVT::i32, CCReg); in addIPMSequence()
[all …]
HDSystemZISelDAGToDAG.cpp78 if (Base.getNode()) in dump()
79 Base.getNode()->dump(DAG); in dump()
85 if (Index.getNode()) in dump()
86 Index.getNode()->dump(DAG); in dump()
429 if (AM.hasIndexField() && !AM.Index.getNode()) { in expandIndex()
587 (AM.Index.getNode() && expandAddress(AM, false))) in selectAddress()
592 !shouldUseLA(AM.Base.getNode(), AM.Disp, AM.Index.getNode())) in selectAddress()
614 (SelectionDAGISel::getUninvalidatedNodeId(N.getNode()) > in insertDAGNode()
616 DAG->RepositionNode(Pos->getIterator(), N.getNode()); in insertDAGNode()
622 SelectionDAGISel::InvalidateNodeId(N.getNode()); in insertDAGNode()
[all …]
HDSystemZISelLowering.cpp1277 Value = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Value, in convertLocVTToValVT()
1280 Value = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Value, in convertLocVTToValVT()
1284 Value = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Value); in convertLocVTToValVT()
1291 Value = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Value); in convertLocVTToValVT()
1304 return DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Value); in convertValVTToLocVT()
1306 return DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Value); in convertValVTToLocVT()
1308 return DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Value); in convertValVTToLocVT()
1314 Value = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Value); in convertValVTToLocVT()
1315 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VA.getLocVT(), Value, in convertValVTToLocVT()
1400 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, in LowerFormalArguments()
[all …]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
HDLanaiISelLowering.cpp354 if (Result.getNode()) { in LowerAsmOperandForConstraint()
471 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerCCCArguments()
474 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerCCCArguments()
478 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue); in LowerCCCArguments()
520 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain); in LowerCCCArguments()
586 if (Flag.getNode()) in LowerReturn()
590 return DAG.getNode(Opc, DL, MVT::Other, in LowerReturn()
667 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg); in LowerCCCCallTo()
670 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg); in LowerCCCCallTo()
673 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg); in LowerCCCCallTo()
[all …]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
HDX86ISelDAGToDAG.cpp91 IndexReg.getNode() != nullptr || Base_Reg.getNode() != nullptr; in hasBaseOrIndexReg()
98 dyn_cast_or_null<RegisterSDNode>(Base_Reg.getNode())) in isRIPRelative()
112 if (Base_Reg.getNode()) in dump()
113 Base_Reg.getNode()->dump(DAG); in dump()
122 if (IndexReg.getNode()) in dump()
123 IndexReg.getNode()->dump(DAG); in dump()
276 else if (AM.Base_Reg.getNode()) in getAddressOperands()
291 if (AM.IndexReg.getNode()) in getAddressOperands()
321 if (AM.Segment.getNode()) in getAddressOperands()
357 User->getOperand(1).getNode() == N) { in shouldAvoidImmediateInstFormsForSize()
[all …]
HDX86ISelLowering.cpp2404 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), in getPICJumpTableRelocBase()
2586 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Dl, ValLoc, ValArg, in lowerMasksToReg()
2597 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, Dl, ValLoc, ValToCopy); in lowerMasksToReg()
2608 return DAG.getNode(ISD::ANY_EXTEND, Dl, ValLoc, ValArg); in lowerMasksToReg()
2627 Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, Dl, MVT::i32, Arg, in Passv64i1ArgInRegs()
2629 Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, Dl, MVT::i32, Arg, in Passv64i1ArgInRegs()
2681 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy); in LowerReturn()
2683 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy); in LowerReturn()
2688 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy); in LowerReturn()
2717 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); in LowerReturn()
[all …]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
HDMipsSEISelLowering.cpp419 SDValue Tmp = DAG.getNode(MipsISD::MTC1_D64, DL, MVT::f64, Op->getOperand(0)); in lowerSELECT()
420 return DAG.getNode(MipsISD::FSELECT, DL, ResTy, Tmp, Op->getOperand(1), in lowerSELECT()
516 return DAG.getNode(MipsISD::VEXTRACT_ZEXT_ELT, SDLoc(Op0), in performANDCombine()
535 BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(N.getNode()); in isVSplat()
643 if (!IfClr.getNode() && isVSplat(Op0Op1, Mask, IsLittleEndian)) { in performORCombine()
660 if (!IfClr.getNode()) { in performORCombine()
697 if (!IfClr.getNode()) in performORCombine()
700 assert(Cond.getNode() && IfSet.getNode()); in performORCombine()
711 return DAG.getNode(ISD::VSELECT, SDLoc(N), Ty, Cond, IfSet, IfClr); in performORCombine()
805 return DAG.getNode(ISD::SHL, DL, VT, X, in genConstMult()
[all …]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
HDSparcISelLowering.cpp244 SDValue Part0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, in LowerReturn_32()
247 SDValue Part1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, in LowerReturn_32()
284 if (Flag.getNode()) in LowerReturn_32()
287 return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other, RetOps); in LowerReturn_32()
325 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
328 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
331 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
340 OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal, in LowerReturn_64()
346 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, OutVals[i+1]); in LowerReturn_64()
347 OutVal = DAG.getNode(ISD::OR, DL, MVT::i64, OutVal, NV); in LowerReturn_64()
[all …]

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