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Searched refs:block_id (Results 1 – 25 of 38) sorted by relevance

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/freebsd-11-stable/sys/contrib/octeon-sdk/
HDcvmx-sriomaintx-defs.h56 static inline uint64_t CVMX_SRIOMAINTX_ASMBLY_ID(unsigned long block_id) in CVMX_SRIOMAINTX_ASMBLY_ID() argument
59 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || in CVMX_SRIOMAINTX_ASMBLY_ID()
60 … (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) in CVMX_SRIOMAINTX_ASMBLY_ID()
61 cvmx_warn("CVMX_SRIOMAINTX_ASMBLY_ID(%lu) is invalid on this chip\n", block_id); in CVMX_SRIOMAINTX_ASMBLY_ID()
65 #define CVMX_SRIOMAINTX_ASMBLY_ID(block_id) (0x0000000000000008ull) argument
68 static inline uint64_t CVMX_SRIOMAINTX_ASMBLY_INFO(unsigned long block_id) in CVMX_SRIOMAINTX_ASMBLY_INFO() argument
71 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || in CVMX_SRIOMAINTX_ASMBLY_INFO()
72 … (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) in CVMX_SRIOMAINTX_ASMBLY_INFO()
73 cvmx_warn("CVMX_SRIOMAINTX_ASMBLY_INFO(%lu) is invalid on this chip\n", block_id); in CVMX_SRIOMAINTX_ASMBLY_INFO()
77 #define CVMX_SRIOMAINTX_ASMBLY_INFO(block_id) (0x000000000000000Cull) argument
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HDcvmx-usbcx-defs.h56 static inline uint64_t CVMX_USBCX_DAINT(unsigned long block_id) in CVMX_USBCX_DAINT() argument
59 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || in CVMX_USBCX_DAINT()
60 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || in CVMX_USBCX_DAINT()
61 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || in CVMX_USBCX_DAINT()
62 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || in CVMX_USBCX_DAINT()
63 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) in CVMX_USBCX_DAINT()
64 cvmx_warn("CVMX_USBCX_DAINT(%lu) is invalid on this chip\n", block_id); in CVMX_USBCX_DAINT()
65 return CVMX_ADD_IO_SEG(0x00016F0010000818ull) + ((block_id) & 1) * 0x100000000000ull; in CVMX_USBCX_DAINT()
68 #define CVMX_USBCX_DAINT(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000818ull) + ((block_id) & 1) * 0x1… argument
71 static inline uint64_t CVMX_USBCX_DAINTMSK(unsigned long block_id) in CVMX_USBCX_DAINTMSK() argument
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HDcvmx-asxx-defs.h56 static inline uint64_t CVMX_ASXX_GMII_RX_CLK_SET(unsigned long block_id) in CVMX_ASXX_GMII_RX_CLK_SET() argument
59 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || in CVMX_ASXX_GMII_RX_CLK_SET()
60 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || in CVMX_ASXX_GMII_RX_CLK_SET()
61 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))))) in CVMX_ASXX_GMII_RX_CLK_SET()
62 cvmx_warn("CVMX_ASXX_GMII_RX_CLK_SET(%lu) is invalid on this chip\n", block_id); in CVMX_ASXX_GMII_RX_CLK_SET()
66 #define CVMX_ASXX_GMII_RX_CLK_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000180ull)) argument
69 static inline uint64_t CVMX_ASXX_GMII_RX_DAT_SET(unsigned long block_id) in CVMX_ASXX_GMII_RX_DAT_SET() argument
72 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || in CVMX_ASXX_GMII_RX_DAT_SET()
73 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || in CVMX_ASXX_GMII_RX_DAT_SET()
74 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))))) in CVMX_ASXX_GMII_RX_DAT_SET()
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HDcvmx-uahcx-defs.h56 static inline uint64_t CVMX_UAHCX_EHCI_ASYNCLISTADDR(unsigned long block_id) in CVMX_UAHCX_EHCI_ASYNCLISTADDR() argument
59 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || in CVMX_UAHCX_EHCI_ASYNCLISTADDR()
60 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || in CVMX_UAHCX_EHCI_ASYNCLISTADDR()
61 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || in CVMX_UAHCX_EHCI_ASYNCLISTADDR()
62 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || in CVMX_UAHCX_EHCI_ASYNCLISTADDR()
63 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) in CVMX_UAHCX_EHCI_ASYNCLISTADDR()
64 cvmx_warn("CVMX_UAHCX_EHCI_ASYNCLISTADDR(%lu) is invalid on this chip\n", block_id); in CVMX_UAHCX_EHCI_ASYNCLISTADDR()
68 #define CVMX_UAHCX_EHCI_ASYNCLISTADDR(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000028ull)) argument
71 static inline uint64_t CVMX_UAHCX_EHCI_CONFIGFLAG(unsigned long block_id) in CVMX_UAHCX_EHCI_CONFIGFLAG() argument
74 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || in CVMX_UAHCX_EHCI_CONFIGFLAG()
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HDcvmx-sriox-defs.h56 static inline uint64_t CVMX_SRIOX_ACC_CTRL(unsigned long block_id) in CVMX_SRIOX_ACC_CTRL() argument
59 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || in CVMX_SRIOX_ACC_CTRL()
60 … (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) in CVMX_SRIOX_ACC_CTRL()
61 cvmx_warn("CVMX_SRIOX_ACC_CTRL(%lu) is invalid on this chip\n", block_id); in CVMX_SRIOX_ACC_CTRL()
62 return CVMX_ADD_IO_SEG(0x00011800C8000148ull) + ((block_id) & 3) * 0x1000000ull; in CVMX_SRIOX_ACC_CTRL()
65 #define CVMX_SRIOX_ACC_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000148ull) + ((block_id) & 3) * … argument
68 static inline uint64_t CVMX_SRIOX_ASMBLY_ID(unsigned long block_id) in CVMX_SRIOX_ASMBLY_ID() argument
71 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || in CVMX_SRIOX_ASMBLY_ID()
72 … (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) in CVMX_SRIOX_ASMBLY_ID()
73 cvmx_warn("CVMX_SRIOX_ASMBLY_ID(%lu) is invalid on this chip\n", block_id); in CVMX_SRIOX_ASMBLY_ID()
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HDcvmx-stxx-defs.h56 static inline uint64_t CVMX_STXX_ARB_CTL(unsigned long block_id) in CVMX_STXX_ARB_CTL() argument
59 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || in CVMX_STXX_ARB_CTL()
60 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) in CVMX_STXX_ARB_CTL()
61 cvmx_warn("CVMX_STXX_ARB_CTL(%lu) is invalid on this chip\n", block_id); in CVMX_STXX_ARB_CTL()
62 return CVMX_ADD_IO_SEG(0x0001180090000608ull) + ((block_id) & 1) * 0x8000000ull; in CVMX_STXX_ARB_CTL()
65 #define CVMX_STXX_ARB_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000608ull) + ((block_id) & 1) * 0x… argument
68 static inline uint64_t CVMX_STXX_BCKPRS_CNT(unsigned long block_id) in CVMX_STXX_BCKPRS_CNT() argument
71 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || in CVMX_STXX_BCKPRS_CNT()
72 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) in CVMX_STXX_BCKPRS_CNT()
73 cvmx_warn("CVMX_STXX_BCKPRS_CNT(%lu) is invalid on this chip\n", block_id); in CVMX_STXX_BCKPRS_CNT()
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HDcvmx-pciercx-defs.h56 static inline uint64_t CVMX_PCIERCX_CFG000(unsigned long block_id) in CVMX_PCIERCX_CFG000() argument
59 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || in CVMX_PCIERCX_CFG000()
60 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || in CVMX_PCIERCX_CFG000()
61 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || in CVMX_PCIERCX_CFG000()
62 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || in CVMX_PCIERCX_CFG000()
63 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || in CVMX_PCIERCX_CFG000()
64 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || in CVMX_PCIERCX_CFG000()
65 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) in CVMX_PCIERCX_CFG000()
66 cvmx_warn("CVMX_PCIERCX_CFG000(%lu) is invalid on this chip\n", block_id); in CVMX_PCIERCX_CFG000()
70 #define CVMX_PCIERCX_CFG000(block_id) (0x0000000000000000ull) argument
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HDcvmx-pemx-defs.h56 static inline uint64_t CVMX_PEMX_BAR1_INDEXX(unsigned long offset, unsigned long block_id) in CVMX_PEMX_BAR1_INDEXX() argument
59 (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset <= 15)) && ((block_id <= 1)))) || in CVMX_PEMX_BAR1_INDEXX()
60 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 15)) && ((block_id <= 1)))) || in CVMX_PEMX_BAR1_INDEXX()
61 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 15)) && ((block_id <= 1)))) || in CVMX_PEMX_BAR1_INDEXX()
62 (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset <= 15)) && ((block_id <= 1)))) || in CVMX_PEMX_BAR1_INDEXX()
63 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset <= 15)) && ((block_id <= 1)))))) in CVMX_PEMX_BAR1_INDEXX()
64 cvmx_warn("CVMX_PEMX_BAR1_INDEXX(%lu,%lu) is invalid on this chip\n", offset, block_id); in CVMX_PEMX_BAR1_INDEXX()
65 …return CVMX_ADD_IO_SEG(0x00011800C00000A8ull) + (((offset) & 15) + ((block_id) & 1) * 0x200000ull)… in CVMX_PEMX_BAR1_INDEXX()
68 …efine CVMX_PEMX_BAR1_INDEXX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A8ull) + (((offset)… argument
71 static inline uint64_t CVMX_PEMX_BAR2_MASK(unsigned long block_id) in CVMX_PEMX_BAR2_MASK() argument
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HDcvmx-pcieepx-defs.h56 static inline uint64_t CVMX_PCIEEPX_CFG000(unsigned long block_id) in CVMX_PCIEEPX_CFG000() argument
59 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || in CVMX_PCIEEPX_CFG000()
60 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || in CVMX_PCIEEPX_CFG000()
61 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || in CVMX_PCIEEPX_CFG000()
62 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || in CVMX_PCIEEPX_CFG000()
63 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || in CVMX_PCIEEPX_CFG000()
64 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || in CVMX_PCIEEPX_CFG000()
65 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) in CVMX_PCIEEPX_CFG000()
66 cvmx_warn("CVMX_PCIEEPX_CFG000(%lu) is invalid on this chip\n", block_id); in CVMX_PCIEEPX_CFG000()
70 #define CVMX_PCIEEPX_CFG000(block_id) (0x0000000000000000ull) argument
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HDcvmx-lmcx-defs.h56 static inline uint64_t CVMX_LMCX_BIST_CTL(unsigned long block_id) in CVMX_LMCX_BIST_CTL() argument
59 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || in CVMX_LMCX_BIST_CTL()
60 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || in CVMX_LMCX_BIST_CTL()
61 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))))) in CVMX_LMCX_BIST_CTL()
62 cvmx_warn("CVMX_LMCX_BIST_CTL(%lu) is invalid on this chip\n", block_id); in CVMX_LMCX_BIST_CTL()
63 return CVMX_ADD_IO_SEG(0x00011800880000F0ull) + ((block_id) & 1) * 0x60000000ull; in CVMX_LMCX_BIST_CTL()
66 #define CVMX_LMCX_BIST_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000F0ull) + ((block_id) & 1) * 0… argument
69 static inline uint64_t CVMX_LMCX_BIST_RESULT(unsigned long block_id) in CVMX_LMCX_BIST_RESULT() argument
72 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || in CVMX_LMCX_BIST_RESULT()
73 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || in CVMX_LMCX_BIST_RESULT()
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HDcvmx-gmxx-defs.h55 static inline uint64_t CVMX_GMXX_BAD_REG(unsigned long block_id) in CVMX_GMXX_BAD_REG() argument
64 if ((block_id == 0)) in CVMX_GMXX_BAD_REG()
65 return CVMX_ADD_IO_SEG(0x0001180008000518ull) + ((block_id) & 0) * 0x8000000ull; in CVMX_GMXX_BAD_REG()
72 if ((block_id <= 1)) in CVMX_GMXX_BAD_REG()
73 return CVMX_ADD_IO_SEG(0x0001180008000518ull) + ((block_id) & 1) * 0x8000000ull; in CVMX_GMXX_BAD_REG()
76 if ((block_id <= 4)) in CVMX_GMXX_BAD_REG()
77 return CVMX_ADD_IO_SEG(0x0001180008000518ull) + ((block_id) & 7) * 0x1000000ull; in CVMX_GMXX_BAD_REG()
80 cvmx_warn("CVMX_GMXX_BAD_REG (block_id = %lu) not supported on this chip\n", block_id); in CVMX_GMXX_BAD_REG()
81 return CVMX_ADD_IO_SEG(0x0001180008000518ull) + ((block_id) & 0) * 0x8000000ull; in CVMX_GMXX_BAD_REG()
83 static inline uint64_t CVMX_GMXX_BIST(unsigned long block_id) in CVMX_GMXX_BIST() argument
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HDcvmx-pcsx-defs.h55 static inline uint64_t CVMX_PCSX_ANX_ADV_REG(unsigned long offset, unsigned long block_id) in CVMX_PCSX_ANX_ADV_REG() argument
59 if (((offset <= 1)) && ((block_id == 0))) in CVMX_PCSX_ANX_ADV_REG()
60 …return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) *… in CVMX_PCSX_ANX_ADV_REG()
64 if (((offset <= 3)) && ((block_id == 0))) in CVMX_PCSX_ANX_ADV_REG()
65 …return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) *… in CVMX_PCSX_ANX_ADV_REG()
70 if (((offset <= 3)) && ((block_id <= 1))) in CVMX_PCSX_ANX_ADV_REG()
71 …return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) *… in CVMX_PCSX_ANX_ADV_REG()
74 if (((offset <= 3)) && ((block_id <= 4))) in CVMX_PCSX_ANX_ADV_REG()
75 …return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * … in CVMX_PCSX_ANX_ADV_REG()
78 cvmx_warn("CVMX_PCSX_ANX_ADV_REG (%lu, %lu) not supported on this chip\n", offset, block_id); in CVMX_PCSX_ANX_ADV_REG()
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HDcvmx-spxx-defs.h56 static inline uint64_t CVMX_SPXX_BCKPRS_CNT(unsigned long block_id) in CVMX_SPXX_BCKPRS_CNT() argument
59 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || in CVMX_SPXX_BCKPRS_CNT()
60 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) in CVMX_SPXX_BCKPRS_CNT()
61 cvmx_warn("CVMX_SPXX_BCKPRS_CNT(%lu) is invalid on this chip\n", block_id); in CVMX_SPXX_BCKPRS_CNT()
62 return CVMX_ADD_IO_SEG(0x0001180090000340ull) + ((block_id) & 1) * 0x8000000ull; in CVMX_SPXX_BCKPRS_CNT()
65 #define CVMX_SPXX_BCKPRS_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000340ull) + ((block_id) & 1) *… argument
68 static inline uint64_t CVMX_SPXX_BIST_STAT(unsigned long block_id) in CVMX_SPXX_BIST_STAT() argument
71 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || in CVMX_SPXX_BIST_STAT()
72 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) in CVMX_SPXX_BIST_STAT()
73 cvmx_warn("CVMX_SPXX_BIST_STAT(%lu) is invalid on this chip\n", block_id); in CVMX_SPXX_BIST_STAT()
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HDcvmx-pcsxx-defs.h55 static inline uint64_t CVMX_PCSXX_10GBX_STATUS_REG(unsigned long block_id) in CVMX_PCSXX_10GBX_STATUS_REG() argument
61 if ((block_id <= 1)) in CVMX_PCSXX_10GBX_STATUS_REG()
62 return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + ((block_id) & 1) * 0x8000000ull; in CVMX_PCSXX_10GBX_STATUS_REG()
66 if ((block_id == 0)) in CVMX_PCSXX_10GBX_STATUS_REG()
67 return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + ((block_id) & 0) * 0x8000000ull; in CVMX_PCSXX_10GBX_STATUS_REG()
70 if ((block_id <= 4)) in CVMX_PCSXX_10GBX_STATUS_REG()
71 return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + ((block_id) & 7) * 0x1000000ull; in CVMX_PCSXX_10GBX_STATUS_REG()
74 cvmx_warn("CVMX_PCSXX_10GBX_STATUS_REG (block_id = %lu) not supported on this chip\n", block_id); in CVMX_PCSXX_10GBX_STATUS_REG()
75 return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + ((block_id) & 7) * 0x1000000ull; in CVMX_PCSXX_10GBX_STATUS_REG()
77 static inline uint64_t CVMX_PCSXX_BIST_STATUS_REG(unsigned long block_id) in CVMX_PCSXX_BIST_STATUS_REG() argument
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HDcvmx-usbnx-defs.h56 static inline uint64_t CVMX_USBNX_BIST_STATUS(unsigned long block_id) in CVMX_USBNX_BIST_STATUS() argument
59 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || in CVMX_USBNX_BIST_STATUS()
60 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || in CVMX_USBNX_BIST_STATUS()
61 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || in CVMX_USBNX_BIST_STATUS()
62 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || in CVMX_USBNX_BIST_STATUS()
63 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) in CVMX_USBNX_BIST_STATUS()
64 cvmx_warn("CVMX_USBNX_BIST_STATUS(%lu) is invalid on this chip\n", block_id); in CVMX_USBNX_BIST_STATUS()
65 return CVMX_ADD_IO_SEG(0x00011800680007F8ull) + ((block_id) & 1) * 0x10000000ull; in CVMX_USBNX_BIST_STATUS()
68 #define CVMX_USBNX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800680007F8ull) + ((block_id) & 1)… argument
71 static inline uint64_t CVMX_USBNX_CLK_CTL(unsigned long block_id) in CVMX_USBNX_CLK_CTL() argument
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HDcvmx-uctlx-defs.h56 static inline uint64_t CVMX_UCTLX_BIST_STATUS(unsigned long block_id) in CVMX_UCTLX_BIST_STATUS() argument
59 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || in CVMX_UCTLX_BIST_STATUS()
60 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || in CVMX_UCTLX_BIST_STATUS()
61 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || in CVMX_UCTLX_BIST_STATUS()
62 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || in CVMX_UCTLX_BIST_STATUS()
63 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) in CVMX_UCTLX_BIST_STATUS()
64 cvmx_warn("CVMX_UCTLX_BIST_STATUS(%lu) is invalid on this chip\n", block_id); in CVMX_UCTLX_BIST_STATUS()
68 #define CVMX_UCTLX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A0ull)) argument
71 static inline uint64_t CVMX_UCTLX_CLK_RST_CTL(unsigned long block_id) in CVMX_UCTLX_CLK_RST_CTL() argument
74 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || in CVMX_UCTLX_CLK_RST_CTL()
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HDcvmx-pescx-defs.h56 static inline uint64_t CVMX_PESCX_BIST_STATUS(unsigned long block_id) in CVMX_PESCX_BIST_STATUS() argument
59 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || in CVMX_PESCX_BIST_STATUS()
60 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))))) in CVMX_PESCX_BIST_STATUS()
61 cvmx_warn("CVMX_PESCX_BIST_STATUS(%lu) is invalid on this chip\n", block_id); in CVMX_PESCX_BIST_STATUS()
62 return CVMX_ADD_IO_SEG(0x00011800C8000018ull) + ((block_id) & 1) * 0x8000000ull; in CVMX_PESCX_BIST_STATUS()
65 #define CVMX_PESCX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000018ull) + ((block_id) & 1)… argument
68 static inline uint64_t CVMX_PESCX_BIST_STATUS2(unsigned long block_id) in CVMX_PESCX_BIST_STATUS2() argument
71 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || in CVMX_PESCX_BIST_STATUS2()
72 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))))) in CVMX_PESCX_BIST_STATUS2()
73 cvmx_warn("CVMX_PESCX_BIST_STATUS2(%lu) is invalid on this chip\n", block_id); in CVMX_PESCX_BIST_STATUS2()
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HDcvmx-ciu2-defs.h56 static inline uint64_t CVMX_CIU2_ACK_IOX_INT(unsigned long block_id) in CVMX_CIU2_ACK_IOX_INT() argument
59 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))))) in CVMX_CIU2_ACK_IOX_INT()
60 cvmx_warn("CVMX_CIU2_ACK_IOX_INT(%lu) is invalid on this chip\n", block_id); in CVMX_CIU2_ACK_IOX_INT()
61 return CVMX_ADD_IO_SEG(0x00010701080C0800ull) + ((block_id) & 1) * 0x200000ull; in CVMX_CIU2_ACK_IOX_INT()
64 #define CVMX_CIU2_ACK_IOX_INT(block_id) (CVMX_ADD_IO_SEG(0x00010701080C0800ull) + ((block_id) & 1) … argument
67 static inline uint64_t CVMX_CIU2_ACK_PPX_IP2(unsigned long block_id) in CVMX_CIU2_ACK_PPX_IP2() argument
70 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31))))) in CVMX_CIU2_ACK_PPX_IP2()
71 cvmx_warn("CVMX_CIU2_ACK_PPX_IP2(%lu) is invalid on this chip\n", block_id); in CVMX_CIU2_ACK_PPX_IP2()
72 return CVMX_ADD_IO_SEG(0x00010701000C0000ull) + ((block_id) & 31) * 0x200000ull; in CVMX_CIU2_ACK_PPX_IP2()
75 #define CVMX_CIU2_ACK_PPX_IP2(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0000ull) + ((block_id) & 31)… argument
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HDcvmx-srxx-defs.h56 static inline uint64_t CVMX_SRXX_COM_CTL(unsigned long block_id) in CVMX_SRXX_COM_CTL() argument
59 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || in CVMX_SRXX_COM_CTL()
60 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) in CVMX_SRXX_COM_CTL()
61 cvmx_warn("CVMX_SRXX_COM_CTL(%lu) is invalid on this chip\n", block_id); in CVMX_SRXX_COM_CTL()
62 return CVMX_ADD_IO_SEG(0x0001180090000200ull) + ((block_id) & 1) * 0x8000000ull; in CVMX_SRXX_COM_CTL()
65 #define CVMX_SRXX_COM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000200ull) + ((block_id) & 1) * 0x… argument
68 static inline uint64_t CVMX_SRXX_IGN_RX_FULL(unsigned long block_id) in CVMX_SRXX_IGN_RX_FULL() argument
71 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) || in CVMX_SRXX_IGN_RX_FULL()
72 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1))))) in CVMX_SRXX_IGN_RX_FULL()
73 cvmx_warn("CVMX_SRXX_IGN_RX_FULL(%lu) is invalid on this chip\n", block_id); in CVMX_SRXX_IGN_RX_FULL()
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HDcvmx-trax-defs.h56 static inline uint64_t CVMX_TRAX_BIST_STATUS(unsigned long block_id) in CVMX_TRAX_BIST_STATUS() argument
59 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || in CVMX_TRAX_BIST_STATUS()
60 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || in CVMX_TRAX_BIST_STATUS()
61 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || in CVMX_TRAX_BIST_STATUS()
62 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || in CVMX_TRAX_BIST_STATUS()
63 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || in CVMX_TRAX_BIST_STATUS()
64 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || in CVMX_TRAX_BIST_STATUS()
65 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || in CVMX_TRAX_BIST_STATUS()
66 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || in CVMX_TRAX_BIST_STATUS()
67 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || in CVMX_TRAX_BIST_STATUS()
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HDcvmx-l2c-defs.h111 static inline uint64_t CVMX_L2C_BST_MEMX(unsigned long block_id) in CVMX_L2C_BST_MEMX() argument
114 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || in CVMX_L2C_BST_MEMX()
115 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || in CVMX_L2C_BST_MEMX()
116 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || in CVMX_L2C_BST_MEMX()
117 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || in CVMX_L2C_BST_MEMX()
118 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) in CVMX_L2C_BST_MEMX()
119 cvmx_warn("CVMX_L2C_BST_MEMX(%lu) is invalid on this chip\n", block_id); in CVMX_L2C_BST_MEMX()
120 return CVMX_ADD_IO_SEG(0x0001180080C007F8ull) + ((block_id) & 3) * 0x40000ull; in CVMX_L2C_BST_MEMX()
123 #define CVMX_L2C_BST_MEMX(block_id) (CVMX_ADD_IO_SEG(0x0001180080C007F8ull) + ((block_id) & 3) * 0x… argument
126 static inline uint64_t CVMX_L2C_BST_TDTX(unsigned long block_id) in CVMX_L2C_BST_TDTX() argument
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/freebsd-11-stable/sys/dev/qlnx/qlnxe/
HDecore_dbg_fw_funcs.c233 enum block_id block_id; member
1932 enum block_id block_id) in get_dbg_bus_block_desc() argument
1936 return (struct dbg_bus_block *)&dbg_bus_blocks[block_id * MAX_CHIP_IDS + dev_data->chip_id]; in get_dbg_bus_block_desc()
1941 enum block_id block_id) in get_dbg_bus_line_desc() argument
1947 block_bus = &dev_data->bus.blocks[block_id]; in get_dbg_bus_line_desc()
1948 block_desc = get_dbg_bus_block_desc(p_hwfn, block_id); in get_dbg_bus_line_desc()
2109 if (dev_data->block_in_reset[storm->block_id]) in ecore_dump_fw_ver_param()
2369 u32 block_id; in ecore_bus_disable_inputs() local
2375 if (dev_data->block_in_reset[storm->block_id]) in ecore_bus_disable_inputs()
2394 …if (dev_data->block_in_reset[storm->block_id] || ecore_rd(p_hwfn, p_ptt, storm->sem_sync_dbg_empty… in ecore_bus_disable_inputs()
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HDecore_dbg_fw_funcs.h216 enum block_id block,
348 enum block_id block,
423 enum block_id block,
863 enum block_id block,
894 enum block_id block);
/freebsd-11-stable/contrib/llvm-project/lldb/source/Plugins/SymbolFile/NativePDB/
HDSymbolFileNativePDB.cpp355 Block &SymbolFileNativePDB::CreateBlock(PdbCompilandSymId block_id) { in CreateBlock() argument
356 CompilandIndexItem *cii = m_index->compilands().GetCompiland(block_id.modi); in CreateBlock()
357 CVSymbol sym = cii->m_debug_stream.readSymbolAtOffset(block_id.offset); in CreateBlock()
363 return GetOrCreateFunction(block_id, *comp_unit)->GetBlock(false); in CreateBlock()
374 PdbCompilandSymId parent_id(block_id.modi, block.Parent); in CreateBlock()
376 lldb::user_id_t opaque_block_uid = toOpaqueUid(block_id); in CreateBlock()
380 m_ast->GetOrCreateBlockDecl(block_id); in CreateBlock()
881 Block &SymbolFileNativePDB::GetOrCreateBlock(PdbCompilandSymId block_id) { in GetOrCreateBlock() argument
882 auto iter = m_blocks.find(toOpaqueUid(block_id)); in GetOrCreateBlock()
886 return CreateBlock(block_id); in GetOrCreateBlock()
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HDPdbAstBuilder.cpp811 PdbAstBuilder::GetOrCreateBlockDecl(PdbCompilandSymId block_id) { in GetOrCreateBlockDecl() argument
812 if (clang::Decl *decl = TryGetDecl(block_id)) in GetOrCreateBlockDecl()
815 clang::DeclContext *scope = GetParentDeclContext(block_id); in GetOrCreateBlockDecl()
818 m_uid_to_decl.insert({toOpaqueUid(block_id), block_decl}); in GetOrCreateBlockDecl()
822 status.uid = toOpaqueUid(block_id); in GetOrCreateBlockDecl()
1265 void PdbAstBuilder::ParseBlockChildren(PdbCompilandSymId block_id) { in ParseBlockChildren() argument
1266 CVSymbol sym = m_index.ReadSymbolRecord(block_id); in ParseBlockChildren()
1270 m_index.compilands().GetOrCreateCompiland(block_id.modi); in ParseBlockChildren()
1272 cii.m_debug_stream.getSymbolArrayForScope(block_id.offset); in ParseBlockChildren()
1278 skipFunctionParameters(*m_uid_to_decl[toOpaqueUid(block_id)], symbols); in ParseBlockChildren()
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