1 /*- 2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef MLX5_IFC_H 29 #define MLX5_IFC_H 30 31 #include <dev/mlx5/mlx5_fpga/mlx5_ifc_fpga.h> 32 33 enum { 34 MLX5_EVENT_TYPE_COMP = 0x0, 35 MLX5_EVENT_TYPE_PATH_MIG = 0x1, 36 MLX5_EVENT_TYPE_COMM_EST = 0x2, 37 MLX5_EVENT_TYPE_SQ_DRAINED = 0x3, 38 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13, 39 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14, 40 MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c, 41 MLX5_EVENT_TYPE_DCT_KEY_VIOLATION = 0x1d, 42 MLX5_EVENT_TYPE_CQ_ERROR = 0x4, 43 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x5, 44 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x7, 45 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc, 46 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 47 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 48 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 49 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x8, 50 MLX5_EVENT_TYPE_PORT_CHANGE = 0x9, 51 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15, 52 MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT = 0x16, 53 MLX5_EVENT_TYPE_TEMP_WARN_EVENT = 0x17, 54 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19, 55 MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT = 0x1e, 56 MLX5_EVENT_TYPE_CODING_PPS_EVENT = 0x25, 57 MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT = 0x22, 58 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a, 59 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b, 60 MLX5_EVENT_TYPE_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 61 MLX5_EVENT_TYPE_CMD = 0xa, 62 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb, 63 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd, 64 MLX5_EVENT_TYPE_FPGA_ERROR = 0x20, 65 MLX5_EVENT_TYPE_FPGA_QP_ERROR = 0x21, 66 }; 67 68 enum { 69 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 70 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 71 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 72 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3, 73 MLX5_MODIFY_TIR_BITMASK_SELF_LB_EN = 0x4 74 }; 75 76 enum { 77 MLX5_MODIFY_RQT_BITMASK_RQN_LIST = 0x1, 78 }; 79 80 enum { 81 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 82 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 83 }; 84 85 enum { 86 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 87 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 88 MLX5_CMD_OP_INIT_HCA = 0x102, 89 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 90 MLX5_CMD_OP_ENABLE_HCA = 0x104, 91 MLX5_CMD_OP_DISABLE_HCA = 0x105, 92 MLX5_CMD_OP_QUERY_PAGES = 0x107, 93 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 94 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 95 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 96 MLX5_CMD_OP_SET_ISSI = 0x10b, 97 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 98 MLX5_CMD_OP_QUERY_OTHER_HCA_CAP = 0x10e, 99 MLX5_CMD_OP_MODIFY_OTHER_HCA_CAP = 0x10f, 100 MLX5_CMD_OP_CREATE_MKEY = 0x200, 101 MLX5_CMD_OP_QUERY_MKEY = 0x201, 102 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 103 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 104 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 105 MLX5_CMD_OP_CREATE_EQ = 0x301, 106 MLX5_CMD_OP_DESTROY_EQ = 0x302, 107 MLX5_CMD_OP_QUERY_EQ = 0x303, 108 MLX5_CMD_OP_GEN_EQE = 0x304, 109 MLX5_CMD_OP_CREATE_CQ = 0x400, 110 MLX5_CMD_OP_DESTROY_CQ = 0x401, 111 MLX5_CMD_OP_QUERY_CQ = 0x402, 112 MLX5_CMD_OP_MODIFY_CQ = 0x403, 113 MLX5_CMD_OP_CREATE_QP = 0x500, 114 MLX5_CMD_OP_DESTROY_QP = 0x501, 115 MLX5_CMD_OP_RST2INIT_QP = 0x502, 116 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 117 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 118 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 119 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 120 MLX5_CMD_OP_2ERR_QP = 0x507, 121 MLX5_CMD_OP_2RST_QP = 0x50a, 122 MLX5_CMD_OP_QUERY_QP = 0x50b, 123 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 124 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 125 MLX5_CMD_OP_CREATE_PSV = 0x600, 126 MLX5_CMD_OP_DESTROY_PSV = 0x601, 127 MLX5_CMD_OP_CREATE_SRQ = 0x700, 128 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 129 MLX5_CMD_OP_QUERY_SRQ = 0x702, 130 MLX5_CMD_OP_ARM_RQ = 0x703, 131 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 132 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 133 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 134 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 135 MLX5_CMD_OP_CREATE_DCT = 0x710, 136 MLX5_CMD_OP_DESTROY_DCT = 0x711, 137 MLX5_CMD_OP_DRAIN_DCT = 0x712, 138 MLX5_CMD_OP_QUERY_DCT = 0x713, 139 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 140 MLX5_CMD_OP_SET_DC_CNAK_TRACE = 0x715, 141 MLX5_CMD_OP_QUERY_DC_CNAK_TRACE = 0x716, 142 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 143 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 144 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 145 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 146 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 147 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 148 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 149 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 150 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 151 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 152 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 153 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 154 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 155 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 156 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 157 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 158 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 159 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780, 160 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 161 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 162 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 163 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 164 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 165 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 166 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 167 MLX5_CMD_OP_ALLOC_PD = 0x800, 168 MLX5_CMD_OP_DEALLOC_PD = 0x801, 169 MLX5_CMD_OP_ALLOC_UAR = 0x802, 170 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 171 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 172 MLX5_CMD_OP_ACCESS_REG = 0x805, 173 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 174 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 175 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 176 MLX5_CMD_OP_MAD_IFC = 0x50d, 177 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 178 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 179 MLX5_CMD_OP_NOP = 0x80d, 180 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 181 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 182 MLX5_CMD_OP_SET_BURST_SIZE = 0x812, 183 MLX5_CMD_OP_QUERY_BURST_SIZE = 0x813, 184 MLX5_CMD_OP_ACTIVATE_TRACER = 0x814, 185 MLX5_CMD_OP_DEACTIVATE_TRACER = 0x815, 186 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 187 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 188 MLX5_CMD_OP_SET_DIAGNOSTICS = 0x820, 189 MLX5_CMD_OP_QUERY_DIAGNOSTICS = 0x821, 190 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 191 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 192 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 193 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 194 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 195 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 196 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 197 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 198 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 199 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 200 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 201 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 202 MLX5_CMD_OP_CREATE_LAG = 0x840, 203 MLX5_CMD_OP_MODIFY_LAG = 0x841, 204 MLX5_CMD_OP_QUERY_LAG = 0x842, 205 MLX5_CMD_OP_DESTROY_LAG = 0x843, 206 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 207 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 208 MLX5_CMD_OP_CREATE_TIR = 0x900, 209 MLX5_CMD_OP_MODIFY_TIR = 0x901, 210 MLX5_CMD_OP_DESTROY_TIR = 0x902, 211 MLX5_CMD_OP_QUERY_TIR = 0x903, 212 MLX5_CMD_OP_CREATE_SQ = 0x904, 213 MLX5_CMD_OP_MODIFY_SQ = 0x905, 214 MLX5_CMD_OP_DESTROY_SQ = 0x906, 215 MLX5_CMD_OP_QUERY_SQ = 0x907, 216 MLX5_CMD_OP_CREATE_RQ = 0x908, 217 MLX5_CMD_OP_MODIFY_RQ = 0x909, 218 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 219 MLX5_CMD_OP_QUERY_RQ = 0x90b, 220 MLX5_CMD_OP_CREATE_RMP = 0x90c, 221 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 222 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 223 MLX5_CMD_OP_QUERY_RMP = 0x90f, 224 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 225 MLX5_CMD_OP_QUERY_DELAY_DROP_PARAMS = 0x911, 226 MLX5_CMD_OP_CREATE_TIS = 0x912, 227 MLX5_CMD_OP_MODIFY_TIS = 0x913, 228 MLX5_CMD_OP_DESTROY_TIS = 0x914, 229 MLX5_CMD_OP_QUERY_TIS = 0x915, 230 MLX5_CMD_OP_CREATE_RQT = 0x916, 231 MLX5_CMD_OP_MODIFY_RQT = 0x917, 232 MLX5_CMD_OP_DESTROY_RQT = 0x918, 233 MLX5_CMD_OP_QUERY_RQT = 0x919, 234 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 235 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 236 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 237 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 238 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 239 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 240 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 241 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 242 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 243 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 244 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 245 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 246 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 247 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 248 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d, 249 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e, 250 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 251 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 252 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 253 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 254 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 255 }; 256 257 enum { 258 MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_QUERY_FW_INFO = 0x8007, 259 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_CAPABILITY = 0x8400, 260 MLX5_ICMD_CMDS_OPCODE_ICMD_ACCESS_REGISTER = 0x9001, 261 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_VIRTUAL_MAC = 0x9003, 262 MLX5_ICMD_CMDS_OPCODE_ICMD_SET_VIRTUAL_MAC = 0x9004, 263 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_WOL_ROL = 0x9005, 264 MLX5_ICMD_CMDS_OPCODE_ICMD_SET_WOL_ROL = 0x9006, 265 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_INIT = 0x9007, 266 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_HEADER_STATUS = 0x9008, 267 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_ETOC_STATUS = 0x9009, 268 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_SET_EVENT = 0x900a, 269 MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_INIT_OCSD = 0xf004 270 }; 271 272 struct mlx5_ifc_flow_table_fields_supported_bits { 273 u8 outer_dmac[0x1]; 274 u8 outer_smac[0x1]; 275 u8 outer_ether_type[0x1]; 276 u8 reserved_0[0x1]; 277 u8 outer_first_prio[0x1]; 278 u8 outer_first_cfi[0x1]; 279 u8 outer_first_vid[0x1]; 280 u8 reserved_1[0x1]; 281 u8 outer_second_prio[0x1]; 282 u8 outer_second_cfi[0x1]; 283 u8 outer_second_vid[0x1]; 284 u8 outer_ipv6_flow_label[0x1]; 285 u8 outer_sip[0x1]; 286 u8 outer_dip[0x1]; 287 u8 outer_frag[0x1]; 288 u8 outer_ip_protocol[0x1]; 289 u8 outer_ip_ecn[0x1]; 290 u8 outer_ip_dscp[0x1]; 291 u8 outer_udp_sport[0x1]; 292 u8 outer_udp_dport[0x1]; 293 u8 outer_tcp_sport[0x1]; 294 u8 outer_tcp_dport[0x1]; 295 u8 outer_tcp_flags[0x1]; 296 u8 outer_gre_protocol[0x1]; 297 u8 outer_gre_key[0x1]; 298 u8 outer_vxlan_vni[0x1]; 299 u8 outer_geneve_vni[0x1]; 300 u8 outer_geneve_oam[0x1]; 301 u8 outer_geneve_protocol_type[0x1]; 302 u8 outer_geneve_opt_len[0x1]; 303 u8 reserved_2[0x1]; 304 u8 source_eswitch_port[0x1]; 305 306 u8 inner_dmac[0x1]; 307 u8 inner_smac[0x1]; 308 u8 inner_ether_type[0x1]; 309 u8 reserved_3[0x1]; 310 u8 inner_first_prio[0x1]; 311 u8 inner_first_cfi[0x1]; 312 u8 inner_first_vid[0x1]; 313 u8 reserved_4[0x1]; 314 u8 inner_second_prio[0x1]; 315 u8 inner_second_cfi[0x1]; 316 u8 inner_second_vid[0x1]; 317 u8 inner_ipv6_flow_label[0x1]; 318 u8 inner_sip[0x1]; 319 u8 inner_dip[0x1]; 320 u8 inner_frag[0x1]; 321 u8 inner_ip_protocol[0x1]; 322 u8 inner_ip_ecn[0x1]; 323 u8 inner_ip_dscp[0x1]; 324 u8 inner_udp_sport[0x1]; 325 u8 inner_udp_dport[0x1]; 326 u8 inner_tcp_sport[0x1]; 327 u8 inner_tcp_dport[0x1]; 328 u8 inner_tcp_flags[0x1]; 329 u8 reserved_5[0x9]; 330 331 u8 reserved_6[0x1a]; 332 u8 bth_dst_qp[0x1]; 333 u8 reserved_7[0x4]; 334 u8 source_sqn[0x1]; 335 336 u8 reserved_8[0x20]; 337 }; 338 339 struct mlx5_ifc_eth_discard_cntrs_grp_bits { 340 u8 ingress_general_high[0x20]; 341 342 u8 ingress_general_low[0x20]; 343 344 u8 ingress_policy_engine_high[0x20]; 345 346 u8 ingress_policy_engine_low[0x20]; 347 348 u8 ingress_vlan_membership_high[0x20]; 349 350 u8 ingress_vlan_membership_low[0x20]; 351 352 u8 ingress_tag_frame_type_high[0x20]; 353 354 u8 ingress_tag_frame_type_low[0x20]; 355 356 u8 egress_vlan_membership_high[0x20]; 357 358 u8 egress_vlan_membership_low[0x20]; 359 360 u8 loopback_filter_high[0x20]; 361 362 u8 loopback_filter_low[0x20]; 363 364 u8 egress_general_high[0x20]; 365 366 u8 egress_general_low[0x20]; 367 368 u8 reserved_at_1c0[0x40]; 369 370 u8 egress_hoq_high[0x20]; 371 372 u8 egress_hoq_low[0x20]; 373 374 u8 port_isolation_high[0x20]; 375 376 u8 port_isolation_low[0x20]; 377 378 u8 egress_policy_engine_high[0x20]; 379 380 u8 egress_policy_engine_low[0x20]; 381 382 u8 ingress_tx_link_down_high[0x20]; 383 384 u8 ingress_tx_link_down_low[0x20]; 385 386 u8 egress_stp_filter_high[0x20]; 387 388 u8 egress_stp_filter_low[0x20]; 389 390 u8 egress_hoq_stall_high[0x20]; 391 392 u8 egress_hoq_stall_low[0x20]; 393 394 u8 reserved_at_340[0x440]; 395 }; 396 struct mlx5_ifc_flow_table_prop_layout_bits { 397 u8 ft_support[0x1]; 398 u8 flow_tag[0x1]; 399 u8 flow_counter[0x1]; 400 u8 flow_modify_en[0x1]; 401 u8 modify_root[0x1]; 402 u8 identified_miss_table[0x1]; 403 u8 flow_table_modify[0x1]; 404 u8 encap[0x1]; 405 u8 decap[0x1]; 406 u8 reset_root_to_default[0x1]; 407 u8 reserved_at_a[0x16]; 408 409 u8 reserved_at_20[0x2]; 410 u8 log_max_ft_size[0x6]; 411 u8 reserved_at_28[0x10]; 412 u8 max_ft_level[0x8]; 413 414 u8 reserved_at_40[0x20]; 415 416 u8 reserved_at_60[0x18]; 417 u8 log_max_ft_num[0x8]; 418 419 u8 reserved_at_80[0x10]; 420 u8 log_max_flow_counter[0x8]; 421 u8 log_max_destination[0x8]; 422 423 u8 reserved_at_a0[0x18]; 424 u8 log_max_flow[0x8]; 425 426 u8 reserved_at_c0[0x40]; 427 428 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 429 430 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 431 }; 432 433 struct mlx5_ifc_odp_per_transport_service_cap_bits { 434 u8 send[0x1]; 435 u8 receive[0x1]; 436 u8 write[0x1]; 437 u8 read[0x1]; 438 u8 atomic[0x1]; 439 u8 srq_receive[0x1]; 440 u8 reserved_0[0x1a]; 441 }; 442 443 struct mlx5_ifc_flow_counter_list_bits { 444 u8 reserved_0[0x10]; 445 u8 flow_counter_id[0x10]; 446 447 u8 reserved_1[0x20]; 448 }; 449 450 enum { 451 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0x0, 452 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 0x1, 453 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 0x2, 454 MLX5_FLOW_CONTEXT_DEST_TYPE_QP = 0x3, 455 }; 456 457 struct mlx5_ifc_dest_format_struct_bits { 458 u8 destination_type[0x8]; 459 u8 destination_id[0x18]; 460 461 u8 reserved_0[0x20]; 462 }; 463 464 struct mlx5_ifc_ipv4_layout_bits { 465 u8 reserved_at_0[0x60]; 466 467 u8 ipv4[0x20]; 468 }; 469 470 struct mlx5_ifc_ipv6_layout_bits { 471 u8 ipv6[16][0x8]; 472 }; 473 474 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 475 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 476 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 477 u8 reserved_at_0[0x80]; 478 }; 479 480 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 481 u8 smac_47_16[0x20]; 482 483 u8 smac_15_0[0x10]; 484 u8 ethertype[0x10]; 485 486 u8 dmac_47_16[0x20]; 487 488 u8 dmac_15_0[0x10]; 489 u8 first_prio[0x3]; 490 u8 first_cfi[0x1]; 491 u8 first_vid[0xc]; 492 493 u8 ip_protocol[0x8]; 494 u8 ip_dscp[0x6]; 495 u8 ip_ecn[0x2]; 496 u8 cvlan_tag[0x1]; 497 u8 svlan_tag[0x1]; 498 u8 frag[0x1]; 499 u8 reserved_1[0x4]; 500 u8 tcp_flags[0x9]; 501 502 u8 tcp_sport[0x10]; 503 u8 tcp_dport[0x10]; 504 505 u8 reserved_2[0x20]; 506 507 u8 udp_sport[0x10]; 508 u8 udp_dport[0x10]; 509 510 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 511 512 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 513 }; 514 515 struct mlx5_ifc_fte_match_set_misc_bits { 516 u8 reserved_0[0x8]; 517 u8 source_sqn[0x18]; 518 519 u8 reserved_1[0x10]; 520 u8 source_port[0x10]; 521 522 u8 outer_second_prio[0x3]; 523 u8 outer_second_cfi[0x1]; 524 u8 outer_second_vid[0xc]; 525 u8 inner_second_prio[0x3]; 526 u8 inner_second_cfi[0x1]; 527 u8 inner_second_vid[0xc]; 528 529 u8 outer_second_vlan_tag[0x1]; 530 u8 inner_second_vlan_tag[0x1]; 531 u8 reserved_2[0xe]; 532 u8 gre_protocol[0x10]; 533 534 u8 gre_key_h[0x18]; 535 u8 gre_key_l[0x8]; 536 537 u8 vxlan_vni[0x18]; 538 u8 reserved_3[0x8]; 539 540 u8 geneve_vni[0x18]; 541 u8 reserved4[0x7]; 542 u8 geneve_oam[0x1]; 543 544 u8 reserved_5[0xc]; 545 u8 outer_ipv6_flow_label[0x14]; 546 547 u8 reserved_6[0xc]; 548 u8 inner_ipv6_flow_label[0x14]; 549 550 u8 reserved_7[0xa]; 551 u8 geneve_opt_len[0x6]; 552 u8 geneve_protocol_type[0x10]; 553 554 u8 reserved_8[0x8]; 555 u8 bth_dst_qp[0x18]; 556 557 u8 reserved_9[0xa0]; 558 }; 559 560 struct mlx5_ifc_cmd_pas_bits { 561 u8 pa_h[0x20]; 562 563 u8 pa_l[0x14]; 564 u8 reserved_0[0xc]; 565 }; 566 567 struct mlx5_ifc_uint64_bits { 568 u8 hi[0x20]; 569 570 u8 lo[0x20]; 571 }; 572 573 struct mlx5_ifc_application_prio_entry_bits { 574 u8 reserved_0[0x8]; 575 u8 priority[0x3]; 576 u8 reserved_1[0x2]; 577 u8 sel[0x3]; 578 u8 protocol_id[0x10]; 579 }; 580 581 struct mlx5_ifc_nodnic_ring_doorbell_bits { 582 u8 reserved_0[0x8]; 583 u8 ring_pi[0x10]; 584 u8 reserved_1[0x8]; 585 }; 586 587 enum { 588 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 589 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 590 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 591 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 592 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 593 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 594 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 595 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 596 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 597 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 598 }; 599 600 struct mlx5_ifc_ads_bits { 601 u8 fl[0x1]; 602 u8 free_ar[0x1]; 603 u8 reserved_0[0xe]; 604 u8 pkey_index[0x10]; 605 606 u8 reserved_1[0x8]; 607 u8 grh[0x1]; 608 u8 mlid[0x7]; 609 u8 rlid[0x10]; 610 611 u8 ack_timeout[0x5]; 612 u8 reserved_2[0x3]; 613 u8 src_addr_index[0x8]; 614 u8 log_rtm[0x4]; 615 u8 stat_rate[0x4]; 616 u8 hop_limit[0x8]; 617 618 u8 reserved_3[0x4]; 619 u8 tclass[0x8]; 620 u8 flow_label[0x14]; 621 622 u8 rgid_rip[16][0x8]; 623 624 u8 reserved_4[0x4]; 625 u8 f_dscp[0x1]; 626 u8 f_ecn[0x1]; 627 u8 reserved_5[0x1]; 628 u8 f_eth_prio[0x1]; 629 u8 ecn[0x2]; 630 u8 dscp[0x6]; 631 u8 udp_sport[0x10]; 632 633 u8 dei_cfi[0x1]; 634 u8 eth_prio[0x3]; 635 u8 sl[0x4]; 636 u8 port[0x8]; 637 u8 rmac_47_32[0x10]; 638 639 u8 rmac_31_0[0x20]; 640 }; 641 642 struct mlx5_ifc_diagnostic_counter_cap_bits { 643 u8 sync[0x1]; 644 u8 reserved_0[0xf]; 645 u8 counter_id[0x10]; 646 }; 647 648 struct mlx5_ifc_debug_cap_bits { 649 u8 reserved_0[0x18]; 650 u8 log_max_samples[0x8]; 651 652 u8 single[0x1]; 653 u8 repetitive[0x1]; 654 u8 health_mon_rx_activity[0x1]; 655 u8 reserved_1[0x15]; 656 u8 log_min_sample_period[0x8]; 657 658 u8 reserved_2[0x1c0]; 659 660 struct mlx5_ifc_diagnostic_counter_cap_bits diagnostic_counter[0x1f0]; 661 }; 662 663 struct mlx5_ifc_qos_cap_bits { 664 u8 packet_pacing[0x1]; 665 u8 esw_scheduling[0x1]; 666 u8 esw_bw_share[0x1]; 667 u8 esw_rate_limit[0x1]; 668 u8 hll[0x1]; 669 u8 packet_pacing_burst_bound[0x1]; 670 u8 reserved_at_6[0x1a]; 671 672 u8 reserved_at_20[0x20]; 673 674 u8 packet_pacing_max_rate[0x20]; 675 676 u8 packet_pacing_min_rate[0x20]; 677 678 u8 reserved_at_80[0x10]; 679 u8 packet_pacing_rate_table_size[0x10]; 680 681 u8 esw_element_type[0x10]; 682 u8 esw_tsar_type[0x10]; 683 684 u8 reserved_at_c0[0x10]; 685 u8 max_qos_para_vport[0x10]; 686 687 u8 max_tsar_bw_share[0x20]; 688 689 u8 reserved_at_100[0x700]; 690 }; 691 692 struct mlx5_ifc_snapshot_cap_bits { 693 u8 reserved_0[0x1d]; 694 u8 suspend_qp_uc[0x1]; 695 u8 suspend_qp_ud[0x1]; 696 u8 suspend_qp_rc[0x1]; 697 698 u8 reserved_1[0x1c]; 699 u8 restore_pd[0x1]; 700 u8 restore_uar[0x1]; 701 u8 restore_mkey[0x1]; 702 u8 restore_qp[0x1]; 703 704 u8 reserved_2[0x1e]; 705 u8 named_mkey[0x1]; 706 u8 named_qp[0x1]; 707 708 u8 reserved_3[0x7a0]; 709 }; 710 711 struct mlx5_ifc_e_switch_cap_bits { 712 u8 vport_svlan_strip[0x1]; 713 u8 vport_cvlan_strip[0x1]; 714 u8 vport_svlan_insert[0x1]; 715 u8 vport_cvlan_insert_if_not_exist[0x1]; 716 u8 vport_cvlan_insert_overwrite[0x1]; 717 718 u8 reserved_0[0x19]; 719 720 u8 nic_vport_node_guid_modify[0x1]; 721 u8 nic_vport_port_guid_modify[0x1]; 722 723 u8 reserved_1[0x7e0]; 724 }; 725 726 struct mlx5_ifc_flow_table_eswitch_cap_bits { 727 u8 reserved_0[0x200]; 728 729 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 730 731 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 732 733 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 734 735 u8 reserved_1[0x7800]; 736 }; 737 738 struct mlx5_ifc_flow_table_nic_cap_bits { 739 u8 nic_rx_multi_path_tirs[0x1]; 740 u8 nic_rx_multi_path_tirs_fts[0x1]; 741 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 742 u8 reserved_at_3[0x1fd]; 743 744 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 745 746 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 747 748 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 749 750 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 751 752 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 753 754 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 755 756 u8 reserved_1[0x7200]; 757 }; 758 759 struct mlx5_ifc_pddr_module_info_bits { 760 u8 cable_technology[0x8]; 761 u8 cable_breakout[0x8]; 762 u8 ext_ethernet_compliance_code[0x8]; 763 u8 ethernet_compliance_code[0x8]; 764 765 u8 cable_type[0x4]; 766 u8 cable_vendor[0x4]; 767 u8 cable_length[0x8]; 768 u8 cable_identifier[0x8]; 769 u8 cable_power_class[0x8]; 770 771 u8 reserved_at_40[0x8]; 772 u8 cable_rx_amp[0x8]; 773 u8 cable_rx_emphasis[0x8]; 774 u8 cable_tx_equalization[0x8]; 775 776 u8 reserved_at_60[0x8]; 777 u8 cable_attenuation_12g[0x8]; 778 u8 cable_attenuation_7g[0x8]; 779 u8 cable_attenuation_5g[0x8]; 780 781 u8 reserved_at_80[0x8]; 782 u8 rx_cdr_cap[0x4]; 783 u8 tx_cdr_cap[0x4]; 784 u8 reserved_at_90[0x4]; 785 u8 rx_cdr_state[0x4]; 786 u8 reserved_at_98[0x4]; 787 u8 tx_cdr_state[0x4]; 788 789 u8 vendor_name[16][0x8]; 790 791 u8 vendor_pn[16][0x8]; 792 793 u8 vendor_rev[0x20]; 794 795 u8 fw_version[0x20]; 796 797 u8 vendor_sn[16][0x8]; 798 799 u8 temperature[0x10]; 800 u8 voltage[0x10]; 801 802 u8 rx_power_lane0[0x10]; 803 u8 rx_power_lane1[0x10]; 804 805 u8 rx_power_lane2[0x10]; 806 u8 rx_power_lane3[0x10]; 807 808 u8 reserved_at_2c0[0x40]; 809 810 u8 tx_power_lane0[0x10]; 811 u8 tx_power_lane1[0x10]; 812 813 u8 tx_power_lane2[0x10]; 814 u8 tx_power_lane3[0x10]; 815 816 u8 reserved_at_340[0x40]; 817 818 u8 tx_bias_lane0[0x10]; 819 u8 tx_bias_lane1[0x10]; 820 821 u8 tx_bias_lane2[0x10]; 822 u8 tx_bias_lane3[0x10]; 823 824 u8 reserved_at_3c0[0x40]; 825 826 u8 temperature_high_th[0x10]; 827 u8 temperature_low_th[0x10]; 828 829 u8 voltage_high_th[0x10]; 830 u8 voltage_low_th[0x10]; 831 832 u8 rx_power_high_th[0x10]; 833 u8 rx_power_low_th[0x10]; 834 835 u8 tx_power_high_th[0x10]; 836 u8 tx_power_low_th[0x10]; 837 838 u8 tx_bias_high_th[0x10]; 839 u8 tx_bias_low_th[0x10]; 840 841 u8 reserved_at_4a0[0x10]; 842 u8 wavelength[0x10]; 843 844 u8 reserved_at_4c0[0x300]; 845 }; 846 847 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 848 u8 csum_cap[0x1]; 849 u8 vlan_cap[0x1]; 850 u8 lro_cap[0x1]; 851 u8 lro_psh_flag[0x1]; 852 u8 lro_time_stamp[0x1]; 853 u8 lro_max_msg_sz_mode[0x2]; 854 u8 wqe_vlan_insert[0x1]; 855 u8 self_lb_en_modifiable[0x1]; 856 u8 self_lb_mc[0x1]; 857 u8 self_lb_uc[0x1]; 858 u8 max_lso_cap[0x5]; 859 u8 multi_pkt_send_wqe[0x2]; 860 u8 wqe_inline_mode[0x2]; 861 u8 rss_ind_tbl_cap[0x4]; 862 u8 scatter_fcs[0x1]; 863 u8 reserved_1[0x2]; 864 u8 tunnel_lso_const_out_ip_id[0x1]; 865 u8 tunnel_lro_gre[0x1]; 866 u8 tunnel_lro_vxlan[0x1]; 867 u8 tunnel_statless_gre[0x1]; 868 u8 tunnel_stateless_vxlan[0x1]; 869 870 u8 swp[0x1]; 871 u8 swp_csum[0x1]; 872 u8 swp_lso[0x1]; 873 u8 reserved_2[0x1b]; 874 u8 max_geneve_opt_len[0x1]; 875 u8 tunnel_stateless_geneve_rx[0x1]; 876 877 u8 reserved_3[0x10]; 878 u8 lro_min_mss_size[0x10]; 879 880 u8 reserved_4[0x120]; 881 882 u8 lro_timer_supported_periods[4][0x20]; 883 884 u8 reserved_5[0x600]; 885 }; 886 887 enum { 888 MLX5_ROCE_CAP_L3_TYPE_GRH = 0x1, 889 MLX5_ROCE_CAP_L3_TYPE_IPV4 = 0x2, 890 MLX5_ROCE_CAP_L3_TYPE_IPV6 = 0x4, 891 }; 892 893 struct mlx5_ifc_roce_cap_bits { 894 u8 roce_apm[0x1]; 895 u8 rts2rts_primary_eth_prio[0x1]; 896 u8 roce_rx_allow_untagged[0x1]; 897 u8 rts2rts_src_addr_index_for_vlan_valid_vlan_id[0x1]; 898 899 u8 reserved_0[0x1c]; 900 901 u8 reserved_1[0x60]; 902 903 u8 reserved_2[0xc]; 904 u8 l3_type[0x4]; 905 u8 reserved_3[0x8]; 906 u8 roce_version[0x8]; 907 908 u8 reserved_4[0x10]; 909 u8 r_roce_dest_udp_port[0x10]; 910 911 u8 r_roce_max_src_udp_port[0x10]; 912 u8 r_roce_min_src_udp_port[0x10]; 913 914 u8 reserved_5[0x10]; 915 u8 roce_address_table_size[0x10]; 916 917 u8 reserved_6[0x700]; 918 }; 919 920 enum { 921 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x1, 922 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 923 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 924 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 925 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 926 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 927 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 928 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 929 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 930 }; 931 932 enum { 933 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 934 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 935 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 936 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 937 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 938 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 939 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 940 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 941 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 942 }; 943 944 struct mlx5_ifc_atomic_caps_bits { 945 u8 reserved_0[0x40]; 946 947 u8 atomic_req_8B_endianess_mode[0x2]; 948 u8 reserved_1[0x4]; 949 u8 supported_atomic_req_8B_endianess_mode_1[0x1]; 950 951 u8 reserved_2[0x19]; 952 953 u8 reserved_3[0x20]; 954 955 u8 reserved_4[0x10]; 956 u8 atomic_operations[0x10]; 957 958 u8 reserved_5[0x10]; 959 u8 atomic_size_qp[0x10]; 960 961 u8 reserved_6[0x10]; 962 u8 atomic_size_dc[0x10]; 963 964 u8 reserved_7[0x720]; 965 }; 966 967 struct mlx5_ifc_odp_cap_bits { 968 u8 reserved_0[0x40]; 969 970 u8 sig[0x1]; 971 u8 reserved_1[0x1f]; 972 973 u8 reserved_2[0x20]; 974 975 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 976 977 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 978 979 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 980 981 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 982 983 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 984 985 u8 reserved_3[0x6e0]; 986 }; 987 988 enum { 989 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 990 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 991 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 992 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 993 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 994 }; 995 996 enum { 997 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 998 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 999 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1000 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1001 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1002 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1003 }; 1004 1005 enum { 1006 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1007 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1008 }; 1009 1010 enum { 1011 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1012 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1013 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1014 }; 1015 1016 struct mlx5_ifc_cmd_hca_cap_bits { 1017 u8 reserved_0[0x80]; 1018 1019 u8 log_max_srq_sz[0x8]; 1020 u8 log_max_qp_sz[0x8]; 1021 u8 reserved_1[0xb]; 1022 u8 log_max_qp[0x5]; 1023 1024 u8 reserved_2[0xb]; 1025 u8 log_max_srq[0x5]; 1026 u8 reserved_3[0x10]; 1027 1028 u8 reserved_4[0x8]; 1029 u8 log_max_cq_sz[0x8]; 1030 u8 reserved_5[0xb]; 1031 u8 log_max_cq[0x5]; 1032 1033 u8 log_max_eq_sz[0x8]; 1034 u8 relaxed_ordering_write[1]; 1035 u8 reserved_6[0x1]; 1036 u8 log_max_mkey[0x6]; 1037 u8 reserved_7[0xb]; 1038 u8 fast_teardown[0x1]; 1039 u8 log_max_eq[0x4]; 1040 1041 u8 max_indirection[0x8]; 1042 u8 reserved_8[0x1]; 1043 u8 log_max_mrw_sz[0x7]; 1044 u8 force_teardown[0x1]; 1045 u8 reserved_9[0x1]; 1046 u8 log_max_bsf_list_size[0x6]; 1047 u8 reserved_10[0x2]; 1048 u8 log_max_klm_list_size[0x6]; 1049 1050 u8 reserved_11[0xa]; 1051 u8 log_max_ra_req_dc[0x6]; 1052 u8 reserved_12[0xa]; 1053 u8 log_max_ra_res_dc[0x6]; 1054 1055 u8 reserved_13[0xa]; 1056 u8 log_max_ra_req_qp[0x6]; 1057 u8 reserved_14[0xa]; 1058 u8 log_max_ra_res_qp[0x6]; 1059 1060 u8 pad_cap[0x1]; 1061 u8 cc_query_allowed[0x1]; 1062 u8 cc_modify_allowed[0x1]; 1063 u8 start_pad[0x1]; 1064 u8 cache_line_128byte[0x1]; 1065 u8 reserved_at_165[0xa]; 1066 u8 qcam_reg[0x1]; 1067 u8 gid_table_size[0x10]; 1068 1069 u8 out_of_seq_cnt[0x1]; 1070 u8 vport_counters[0x1]; 1071 u8 retransmission_q_counters[0x1]; 1072 u8 debug[0x1]; 1073 u8 modify_rq_counters_set_id[0x1]; 1074 u8 rq_delay_drop[0x1]; 1075 u8 max_qp_cnt[0xa]; 1076 u8 pkey_table_size[0x10]; 1077 1078 u8 vport_group_manager[0x1]; 1079 u8 vhca_group_manager[0x1]; 1080 u8 ib_virt[0x1]; 1081 u8 eth_virt[0x1]; 1082 u8 reserved_17[0x1]; 1083 u8 ets[0x1]; 1084 u8 nic_flow_table[0x1]; 1085 u8 eswitch_flow_table[0x1]; 1086 u8 reserved_18[0x1]; 1087 u8 mcam_reg[0x1]; 1088 u8 pcam_reg[0x1]; 1089 u8 local_ca_ack_delay[0x5]; 1090 u8 port_module_event[0x1]; 1091 u8 reserved_19[0x5]; 1092 u8 port_type[0x2]; 1093 u8 num_ports[0x8]; 1094 1095 u8 snapshot[0x1]; 1096 u8 reserved_20[0x2]; 1097 u8 log_max_msg[0x5]; 1098 u8 reserved_21[0x4]; 1099 u8 max_tc[0x4]; 1100 u8 temp_warn_event[0x1]; 1101 u8 dcbx[0x1]; 1102 u8 general_notification_event[0x1]; 1103 u8 reserved_at_1d3[0x2]; 1104 u8 fpga[0x1]; 1105 u8 rol_s[0x1]; 1106 u8 rol_g[0x1]; 1107 u8 reserved_23[0x1]; 1108 u8 wol_s[0x1]; 1109 u8 wol_g[0x1]; 1110 u8 wol_a[0x1]; 1111 u8 wol_b[0x1]; 1112 u8 wol_m[0x1]; 1113 u8 wol_u[0x1]; 1114 u8 wol_p[0x1]; 1115 1116 u8 stat_rate_support[0x10]; 1117 u8 reserved_24[0xc]; 1118 u8 cqe_version[0x4]; 1119 1120 u8 compact_address_vector[0x1]; 1121 u8 striding_rq[0x1]; 1122 u8 reserved_25[0x1]; 1123 u8 ipoib_enhanced_offloads[0x1]; 1124 u8 ipoib_ipoib_offloads[0x1]; 1125 u8 reserved_26[0x8]; 1126 u8 dc_connect_qp[0x1]; 1127 u8 dc_cnak_trace[0x1]; 1128 u8 drain_sigerr[0x1]; 1129 u8 cmdif_checksum[0x2]; 1130 u8 sigerr_cqe[0x1]; 1131 u8 reserved_27[0x1]; 1132 u8 wq_signature[0x1]; 1133 u8 sctr_data_cqe[0x1]; 1134 u8 reserved_28[0x1]; 1135 u8 sho[0x1]; 1136 u8 tph[0x1]; 1137 u8 rf[0x1]; 1138 u8 dct[0x1]; 1139 u8 qos[0x1]; 1140 u8 eth_net_offloads[0x1]; 1141 u8 roce[0x1]; 1142 u8 atomic[0x1]; 1143 u8 reserved_30[0x1]; 1144 1145 u8 cq_oi[0x1]; 1146 u8 cq_resize[0x1]; 1147 u8 cq_moderation[0x1]; 1148 u8 cq_period_mode_modify[0x1]; 1149 u8 cq_invalidate[0x1]; 1150 u8 reserved_at_225[0x1]; 1151 u8 cq_eq_remap[0x1]; 1152 u8 pg[0x1]; 1153 u8 block_lb_mc[0x1]; 1154 u8 exponential_backoff[0x1]; 1155 u8 scqe_break_moderation[0x1]; 1156 u8 cq_period_start_from_cqe[0x1]; 1157 u8 cd[0x1]; 1158 u8 atm[0x1]; 1159 u8 apm[0x1]; 1160 u8 imaicl[0x1]; 1161 u8 reserved_32[0x6]; 1162 u8 qkv[0x1]; 1163 u8 pkv[0x1]; 1164 u8 set_deth_sqpn[0x1]; 1165 u8 reserved_33[0x3]; 1166 u8 xrc[0x1]; 1167 u8 ud[0x1]; 1168 u8 uc[0x1]; 1169 u8 rc[0x1]; 1170 1171 u8 reserved_34[0xa]; 1172 u8 uar_sz[0x6]; 1173 u8 reserved_35[0x8]; 1174 u8 log_pg_sz[0x8]; 1175 1176 u8 bf[0x1]; 1177 u8 driver_version[0x1]; 1178 u8 pad_tx_eth_packet[0x1]; 1179 u8 reserved_36[0x8]; 1180 u8 log_bf_reg_size[0x5]; 1181 u8 reserved_37[0x10]; 1182 1183 u8 num_of_diagnostic_counters[0x10]; 1184 u8 max_wqe_sz_sq[0x10]; 1185 1186 u8 reserved_38[0x10]; 1187 u8 max_wqe_sz_rq[0x10]; 1188 1189 u8 reserved_39[0x10]; 1190 u8 max_wqe_sz_sq_dc[0x10]; 1191 1192 u8 reserved_40[0x7]; 1193 u8 max_qp_mcg[0x19]; 1194 1195 u8 reserved_41[0x18]; 1196 u8 log_max_mcg[0x8]; 1197 1198 u8 reserved_42[0x3]; 1199 u8 log_max_transport_domain[0x5]; 1200 u8 reserved_43[0x3]; 1201 u8 log_max_pd[0x5]; 1202 u8 reserved_44[0xb]; 1203 u8 log_max_xrcd[0x5]; 1204 1205 u8 nic_receive_steering_discard[0x1]; 1206 u8 reserved_45[0x7]; 1207 u8 log_max_flow_counter_bulk[0x8]; 1208 u8 max_flow_counter[0x10]; 1209 1210 u8 reserved_46[0x3]; 1211 u8 log_max_rq[0x5]; 1212 u8 reserved_47[0x3]; 1213 u8 log_max_sq[0x5]; 1214 u8 reserved_48[0x3]; 1215 u8 log_max_tir[0x5]; 1216 u8 reserved_49[0x3]; 1217 u8 log_max_tis[0x5]; 1218 1219 u8 basic_cyclic_rcv_wqe[0x1]; 1220 u8 reserved_50[0x2]; 1221 u8 log_max_rmp[0x5]; 1222 u8 reserved_51[0x3]; 1223 u8 log_max_rqt[0x5]; 1224 u8 reserved_52[0x3]; 1225 u8 log_max_rqt_size[0x5]; 1226 u8 reserved_53[0x3]; 1227 u8 log_max_tis_per_sq[0x5]; 1228 1229 u8 reserved_54[0x3]; 1230 u8 log_max_stride_sz_rq[0x5]; 1231 u8 reserved_55[0x3]; 1232 u8 log_min_stride_sz_rq[0x5]; 1233 u8 reserved_56[0x3]; 1234 u8 log_max_stride_sz_sq[0x5]; 1235 u8 reserved_57[0x3]; 1236 u8 log_min_stride_sz_sq[0x5]; 1237 1238 u8 reserved_58[0x1b]; 1239 u8 log_max_wq_sz[0x5]; 1240 1241 u8 nic_vport_change_event[0x1]; 1242 u8 disable_local_lb[0x1]; 1243 u8 reserved_59[0x9]; 1244 u8 log_max_vlan_list[0x5]; 1245 u8 reserved_60[0x3]; 1246 u8 log_max_current_mc_list[0x5]; 1247 u8 reserved_61[0x3]; 1248 u8 log_max_current_uc_list[0x5]; 1249 1250 u8 reserved_62[0x80]; 1251 1252 u8 reserved_63[0x3]; 1253 u8 log_max_l2_table[0x5]; 1254 u8 reserved_64[0x8]; 1255 u8 log_uar_page_sz[0x10]; 1256 1257 u8 reserved_65[0x20]; 1258 1259 u8 device_frequency_mhz[0x20]; 1260 1261 u8 device_frequency_khz[0x20]; 1262 1263 u8 reserved_66[0x80]; 1264 1265 u8 log_max_atomic_size_qp[0x8]; 1266 u8 reserved_67[0x10]; 1267 u8 log_max_atomic_size_dc[0x8]; 1268 1269 u8 reserved_68[0x1f]; 1270 u8 cqe_compression[0x1]; 1271 1272 u8 cqe_compression_timeout[0x10]; 1273 u8 cqe_compression_max_num[0x10]; 1274 1275 u8 reserved_69[0x220]; 1276 }; 1277 1278 enum mlx5_flow_destination_type { 1279 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1280 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1281 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1282 }; 1283 1284 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1285 struct mlx5_ifc_dest_format_struct_bits dest_format_struct; 1286 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1287 u8 reserved_0[0x40]; 1288 }; 1289 1290 struct mlx5_ifc_fte_match_param_bits { 1291 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1292 1293 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1294 1295 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1296 1297 u8 reserved_0[0xa00]; 1298 }; 1299 1300 enum { 1301 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1302 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1303 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1304 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1305 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1306 }; 1307 1308 struct mlx5_ifc_rx_hash_field_select_bits { 1309 u8 l3_prot_type[0x1]; 1310 u8 l4_prot_type[0x1]; 1311 u8 selected_fields[0x1e]; 1312 }; 1313 1314 enum { 1315 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1316 MLX5_WQ_TYPE_CYCLIC = 0x1, 1317 MLX5_WQ_TYPE_STRQ_LINKED_LIST = 0x2, 1318 MLX5_WQ_TYPE_STRQ_CYCLIC = 0x3, 1319 }; 1320 1321 enum rq_type { 1322 RQ_TYPE_NONE, 1323 RQ_TYPE_STRIDE, 1324 }; 1325 1326 enum { 1327 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1328 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1329 }; 1330 1331 struct mlx5_ifc_wq_bits { 1332 u8 wq_type[0x4]; 1333 u8 wq_signature[0x1]; 1334 u8 end_padding_mode[0x2]; 1335 u8 cd_slave[0x1]; 1336 u8 reserved_0[0x18]; 1337 1338 u8 hds_skip_first_sge[0x1]; 1339 u8 log2_hds_buf_size[0x3]; 1340 u8 reserved_1[0x7]; 1341 u8 page_offset[0x5]; 1342 u8 lwm[0x10]; 1343 1344 u8 reserved_2[0x8]; 1345 u8 pd[0x18]; 1346 1347 u8 reserved_3[0x8]; 1348 u8 uar_page[0x18]; 1349 1350 u8 dbr_addr[0x40]; 1351 1352 u8 hw_counter[0x20]; 1353 1354 u8 sw_counter[0x20]; 1355 1356 u8 reserved_4[0xc]; 1357 u8 log_wq_stride[0x4]; 1358 u8 reserved_5[0x3]; 1359 u8 log_wq_pg_sz[0x5]; 1360 u8 reserved_6[0x3]; 1361 u8 log_wq_sz[0x5]; 1362 1363 u8 reserved_7[0x15]; 1364 u8 single_wqe_log_num_of_strides[0x3]; 1365 u8 two_byte_shift_en[0x1]; 1366 u8 reserved_8[0x4]; 1367 u8 single_stride_log_num_of_bytes[0x3]; 1368 1369 u8 reserved_9[0x4c0]; 1370 1371 struct mlx5_ifc_cmd_pas_bits pas[0]; 1372 }; 1373 1374 struct mlx5_ifc_rq_num_bits { 1375 u8 reserved_0[0x8]; 1376 u8 rq_num[0x18]; 1377 }; 1378 1379 struct mlx5_ifc_mac_address_layout_bits { 1380 u8 reserved_0[0x10]; 1381 u8 mac_addr_47_32[0x10]; 1382 1383 u8 mac_addr_31_0[0x20]; 1384 }; 1385 1386 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1387 u8 reserved_0[0xa0]; 1388 1389 u8 min_time_between_cnps[0x20]; 1390 1391 u8 reserved_1[0x12]; 1392 u8 cnp_dscp[0x6]; 1393 u8 reserved_2[0x4]; 1394 u8 cnp_prio_mode[0x1]; 1395 u8 cnp_802p_prio[0x3]; 1396 1397 u8 reserved_3[0x720]; 1398 }; 1399 1400 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1401 u8 reserved_0[0x60]; 1402 1403 u8 reserved_1[0x4]; 1404 u8 clamp_tgt_rate[0x1]; 1405 u8 reserved_2[0x3]; 1406 u8 clamp_tgt_rate_after_time_inc[0x1]; 1407 u8 reserved_3[0x17]; 1408 1409 u8 reserved_4[0x20]; 1410 1411 u8 rpg_time_reset[0x20]; 1412 1413 u8 rpg_byte_reset[0x20]; 1414 1415 u8 rpg_threshold[0x20]; 1416 1417 u8 rpg_max_rate[0x20]; 1418 1419 u8 rpg_ai_rate[0x20]; 1420 1421 u8 rpg_hai_rate[0x20]; 1422 1423 u8 rpg_gd[0x20]; 1424 1425 u8 rpg_min_dec_fac[0x20]; 1426 1427 u8 rpg_min_rate[0x20]; 1428 1429 u8 reserved_5[0xe0]; 1430 1431 u8 rate_to_set_on_first_cnp[0x20]; 1432 1433 u8 dce_tcp_g[0x20]; 1434 1435 u8 dce_tcp_rtt[0x20]; 1436 1437 u8 rate_reduce_monitor_period[0x20]; 1438 1439 u8 reserved_6[0x20]; 1440 1441 u8 initial_alpha_value[0x20]; 1442 1443 u8 reserved_7[0x4a0]; 1444 }; 1445 1446 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1447 u8 reserved_0[0x80]; 1448 1449 u8 rppp_max_rps[0x20]; 1450 1451 u8 rpg_time_reset[0x20]; 1452 1453 u8 rpg_byte_reset[0x20]; 1454 1455 u8 rpg_threshold[0x20]; 1456 1457 u8 rpg_max_rate[0x20]; 1458 1459 u8 rpg_ai_rate[0x20]; 1460 1461 u8 rpg_hai_rate[0x20]; 1462 1463 u8 rpg_gd[0x20]; 1464 1465 u8 rpg_min_dec_fac[0x20]; 1466 1467 u8 rpg_min_rate[0x20]; 1468 1469 u8 reserved_1[0x640]; 1470 }; 1471 1472 enum { 1473 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1474 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1475 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1476 }; 1477 1478 struct mlx5_ifc_resize_field_select_bits { 1479 u8 resize_field_select[0x20]; 1480 }; 1481 1482 enum { 1483 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1484 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1485 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1486 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1487 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD_MODE = 0x10, 1488 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_STATUS = 0x20, 1489 }; 1490 1491 struct mlx5_ifc_modify_field_select_bits { 1492 u8 modify_field_select[0x20]; 1493 }; 1494 1495 struct mlx5_ifc_field_select_r_roce_np_bits { 1496 u8 field_select_r_roce_np[0x20]; 1497 }; 1498 1499 enum { 1500 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE = 0x2, 1501 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE_AFTER_TIME_INC = 0x4, 1502 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_TIME_RESET = 0x8, 1503 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_BYTE_RESET = 0x10, 1504 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_THRESHOLD = 0x20, 1505 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MAX_RATE = 0x40, 1506 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_AI_RATE = 0x80, 1507 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_HAI_RATE = 0x100, 1508 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_DEC_FAC = 0x200, 1509 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_RATE = 0x400, 1510 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_TO_SET_ON_FIRST_CNP = 0x800, 1511 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_G = 0x1000, 1512 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_RTT = 0x2000, 1513 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_REDUCE_MONITOR_PERIOD = 0x4000, 1514 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_INITIAL_ALPHA_VALUE = 0x8000, 1515 }; 1516 1517 struct mlx5_ifc_field_select_r_roce_rp_bits { 1518 u8 field_select_r_roce_rp[0x20]; 1519 }; 1520 1521 enum { 1522 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1523 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1524 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1525 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1526 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1527 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1528 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1529 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1530 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1531 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1532 }; 1533 1534 struct mlx5_ifc_field_select_802_1qau_rp_bits { 1535 u8 field_select_8021qaurp[0x20]; 1536 }; 1537 1538 struct mlx5_ifc_pptb_reg_bits { 1539 u8 reserved_at_0[0x2]; 1540 u8 mm[0x2]; 1541 u8 reserved_at_4[0x4]; 1542 u8 local_port[0x8]; 1543 u8 reserved_at_10[0x6]; 1544 u8 cm[0x1]; 1545 u8 um[0x1]; 1546 u8 pm[0x8]; 1547 1548 u8 prio_x_buff[0x20]; 1549 1550 u8 pm_msb[0x8]; 1551 u8 reserved_at_48[0x10]; 1552 u8 ctrl_buff[0x4]; 1553 u8 untagged_buff[0x4]; 1554 }; 1555 1556 struct mlx5_ifc_dcbx_app_reg_bits { 1557 u8 reserved_0[0x8]; 1558 u8 port_number[0x8]; 1559 u8 reserved_1[0x10]; 1560 1561 u8 reserved_2[0x1a]; 1562 u8 num_app_prio[0x6]; 1563 1564 u8 reserved_3[0x40]; 1565 1566 struct mlx5_ifc_application_prio_entry_bits app_prio[0]; 1567 }; 1568 1569 struct mlx5_ifc_dcbx_param_reg_bits { 1570 u8 dcbx_cee_cap[0x1]; 1571 u8 dcbx_ieee_cap[0x1]; 1572 u8 dcbx_standby_cap[0x1]; 1573 u8 reserved_0[0x5]; 1574 u8 port_number[0x8]; 1575 u8 reserved_1[0xa]; 1576 u8 max_application_table_size[0x6]; 1577 1578 u8 reserved_2[0x15]; 1579 u8 version_oper[0x3]; 1580 u8 reserved_3[0x5]; 1581 u8 version_admin[0x3]; 1582 1583 u8 willing_admin[0x1]; 1584 u8 reserved_4[0x3]; 1585 u8 pfc_cap_oper[0x4]; 1586 u8 reserved_5[0x4]; 1587 u8 pfc_cap_admin[0x4]; 1588 u8 reserved_6[0x4]; 1589 u8 num_of_tc_oper[0x4]; 1590 u8 reserved_7[0x4]; 1591 u8 num_of_tc_admin[0x4]; 1592 1593 u8 remote_willing[0x1]; 1594 u8 reserved_8[0x3]; 1595 u8 remote_pfc_cap[0x4]; 1596 u8 reserved_9[0x14]; 1597 u8 remote_num_of_tc[0x4]; 1598 1599 u8 reserved_10[0x18]; 1600 u8 error[0x8]; 1601 1602 u8 reserved_11[0x160]; 1603 }; 1604 1605 struct mlx5_ifc_qhll_bits { 1606 u8 reserved_at_0[0x8]; 1607 u8 local_port[0x8]; 1608 u8 reserved_at_10[0x10]; 1609 1610 u8 reserved_at_20[0x1b]; 1611 u8 hll_time[0x5]; 1612 1613 u8 stall_en[0x1]; 1614 u8 reserved_at_41[0x1c]; 1615 u8 stall_cnt[0x3]; 1616 }; 1617 1618 struct mlx5_ifc_qetcr_reg_bits { 1619 u8 operation_type[0x2]; 1620 u8 cap_local_admin[0x1]; 1621 u8 cap_remote_admin[0x1]; 1622 u8 reserved_0[0x4]; 1623 u8 port_number[0x8]; 1624 u8 reserved_1[0x10]; 1625 1626 u8 reserved_2[0x20]; 1627 1628 u8 tc[8][0x40]; 1629 1630 u8 global_configuration[0x40]; 1631 }; 1632 1633 struct mlx5_ifc_nodnic_ring_config_reg_bits { 1634 u8 queue_address_63_32[0x20]; 1635 1636 u8 queue_address_31_12[0x14]; 1637 u8 reserved_0[0x6]; 1638 u8 log_size[0x6]; 1639 1640 struct mlx5_ifc_nodnic_ring_doorbell_bits doorbell; 1641 1642 u8 reserved_1[0x8]; 1643 u8 queue_number[0x18]; 1644 1645 u8 q_key[0x20]; 1646 1647 u8 reserved_2[0x10]; 1648 u8 pkey_index[0x10]; 1649 1650 u8 reserved_3[0x40]; 1651 }; 1652 1653 struct mlx5_ifc_nodnic_cq_arming_word_bits { 1654 u8 reserved_0[0x8]; 1655 u8 cq_ci[0x10]; 1656 u8 reserved_1[0x8]; 1657 }; 1658 1659 enum { 1660 MLX5_NODNIC_EVENT_WORD_LINK_TYPE_INFINIBAND = 0x0, 1661 MLX5_NODNIC_EVENT_WORD_LINK_TYPE_ETHERNET = 0x1, 1662 }; 1663 1664 enum { 1665 MLX5_NODNIC_EVENT_WORD_PORT_STATE_DOWN = 0x0, 1666 MLX5_NODNIC_EVENT_WORD_PORT_STATE_INITIALIZE = 0x1, 1667 MLX5_NODNIC_EVENT_WORD_PORT_STATE_ARMED = 0x2, 1668 MLX5_NODNIC_EVENT_WORD_PORT_STATE_ACTIVE = 0x3, 1669 }; 1670 1671 struct mlx5_ifc_nodnic_event_word_bits { 1672 u8 driver_reset_needed[0x1]; 1673 u8 port_management_change_event[0x1]; 1674 u8 reserved_0[0x19]; 1675 u8 link_type[0x1]; 1676 u8 port_state[0x4]; 1677 }; 1678 1679 struct mlx5_ifc_nic_vport_change_event_bits { 1680 u8 reserved_0[0x10]; 1681 u8 vport_num[0x10]; 1682 1683 u8 reserved_1[0xc0]; 1684 }; 1685 1686 struct mlx5_ifc_pages_req_event_bits { 1687 u8 reserved_0[0x10]; 1688 u8 function_id[0x10]; 1689 1690 u8 num_pages[0x20]; 1691 1692 u8 reserved_1[0xa0]; 1693 }; 1694 1695 struct mlx5_ifc_cmd_inter_comp_event_bits { 1696 u8 command_completion_vector[0x20]; 1697 1698 u8 reserved_0[0xc0]; 1699 }; 1700 1701 struct mlx5_ifc_stall_vl_event_bits { 1702 u8 reserved_0[0x18]; 1703 u8 port_num[0x1]; 1704 u8 reserved_1[0x3]; 1705 u8 vl[0x4]; 1706 1707 u8 reserved_2[0xa0]; 1708 }; 1709 1710 struct mlx5_ifc_db_bf_congestion_event_bits { 1711 u8 event_subtype[0x8]; 1712 u8 reserved_0[0x8]; 1713 u8 congestion_level[0x8]; 1714 u8 reserved_1[0x8]; 1715 1716 u8 reserved_2[0xa0]; 1717 }; 1718 1719 struct mlx5_ifc_gpio_event_bits { 1720 u8 reserved_0[0x60]; 1721 1722 u8 gpio_event_hi[0x20]; 1723 1724 u8 gpio_event_lo[0x20]; 1725 1726 u8 reserved_1[0x40]; 1727 }; 1728 1729 struct mlx5_ifc_port_state_change_event_bits { 1730 u8 reserved_0[0x40]; 1731 1732 u8 port_num[0x4]; 1733 u8 reserved_1[0x1c]; 1734 1735 u8 reserved_2[0x80]; 1736 }; 1737 1738 struct mlx5_ifc_dropped_packet_logged_bits { 1739 u8 reserved_0[0xe0]; 1740 }; 1741 1742 enum { 1743 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 1744 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 1745 }; 1746 1747 struct mlx5_ifc_cq_error_bits { 1748 u8 reserved_0[0x8]; 1749 u8 cqn[0x18]; 1750 1751 u8 reserved_1[0x20]; 1752 1753 u8 reserved_2[0x18]; 1754 u8 syndrome[0x8]; 1755 1756 u8 reserved_3[0x80]; 1757 }; 1758 1759 struct mlx5_ifc_rdma_page_fault_event_bits { 1760 u8 bytes_commited[0x20]; 1761 1762 u8 r_key[0x20]; 1763 1764 u8 reserved_0[0x10]; 1765 u8 packet_len[0x10]; 1766 1767 u8 rdma_op_len[0x20]; 1768 1769 u8 rdma_va[0x40]; 1770 1771 u8 reserved_1[0x5]; 1772 u8 rdma[0x1]; 1773 u8 write[0x1]; 1774 u8 requestor[0x1]; 1775 u8 qp_number[0x18]; 1776 }; 1777 1778 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 1779 u8 bytes_committed[0x20]; 1780 1781 u8 reserved_0[0x10]; 1782 u8 wqe_index[0x10]; 1783 1784 u8 reserved_1[0x10]; 1785 u8 len[0x10]; 1786 1787 u8 reserved_2[0x60]; 1788 1789 u8 reserved_3[0x5]; 1790 u8 rdma[0x1]; 1791 u8 write_read[0x1]; 1792 u8 requestor[0x1]; 1793 u8 qpn[0x18]; 1794 }; 1795 1796 enum { 1797 MLX5_QP_EVENTS_TYPE_QP = 0x0, 1798 MLX5_QP_EVENTS_TYPE_RQ = 0x1, 1799 MLX5_QP_EVENTS_TYPE_SQ = 0x2, 1800 }; 1801 1802 struct mlx5_ifc_qp_events_bits { 1803 u8 reserved_0[0xa0]; 1804 1805 u8 type[0x8]; 1806 u8 reserved_1[0x18]; 1807 1808 u8 reserved_2[0x8]; 1809 u8 qpn_rqn_sqn[0x18]; 1810 }; 1811 1812 struct mlx5_ifc_dct_events_bits { 1813 u8 reserved_0[0xc0]; 1814 1815 u8 reserved_1[0x8]; 1816 u8 dct_number[0x18]; 1817 }; 1818 1819 struct mlx5_ifc_comp_event_bits { 1820 u8 reserved_0[0xc0]; 1821 1822 u8 reserved_1[0x8]; 1823 u8 cq_number[0x18]; 1824 }; 1825 1826 struct mlx5_ifc_fw_version_bits { 1827 u8 major[0x10]; 1828 u8 reserved_0[0x10]; 1829 1830 u8 minor[0x10]; 1831 u8 subminor[0x10]; 1832 1833 u8 second[0x8]; 1834 u8 minute[0x8]; 1835 u8 hour[0x8]; 1836 u8 reserved_1[0x8]; 1837 1838 u8 year[0x10]; 1839 u8 month[0x8]; 1840 u8 day[0x8]; 1841 }; 1842 1843 enum { 1844 MLX5_QPC_STATE_RST = 0x0, 1845 MLX5_QPC_STATE_INIT = 0x1, 1846 MLX5_QPC_STATE_RTR = 0x2, 1847 MLX5_QPC_STATE_RTS = 0x3, 1848 MLX5_QPC_STATE_SQER = 0x4, 1849 MLX5_QPC_STATE_SQD = 0x5, 1850 MLX5_QPC_STATE_ERR = 0x6, 1851 MLX5_QPC_STATE_SUSPENDED = 0x9, 1852 }; 1853 1854 enum { 1855 MLX5_QPC_ST_RC = 0x0, 1856 MLX5_QPC_ST_UC = 0x1, 1857 MLX5_QPC_ST_UD = 0x2, 1858 MLX5_QPC_ST_XRC = 0x3, 1859 MLX5_QPC_ST_DCI = 0x5, 1860 MLX5_QPC_ST_QP0 = 0x7, 1861 MLX5_QPC_ST_QP1 = 0x8, 1862 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 1863 MLX5_QPC_ST_REG_UMR = 0xc, 1864 }; 1865 1866 enum { 1867 MLX5_QP_PM_ARMED = 0x0, 1868 MLX5_QP_PM_REARM = 0x1, 1869 MLX5_QPC_PM_STATE_RESERVED = 0x2, 1870 MLX5_QP_PM_MIGRATED = 0x3, 1871 }; 1872 1873 enum { 1874 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 1875 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 1876 }; 1877 1878 enum { 1879 MLX5_QPC_MTU_256_BYTES = 0x1, 1880 MLX5_QPC_MTU_512_BYTES = 0x2, 1881 MLX5_QPC_MTU_1K_BYTES = 0x3, 1882 MLX5_QPC_MTU_2K_BYTES = 0x4, 1883 MLX5_QPC_MTU_4K_BYTES = 0x5, 1884 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 1885 }; 1886 1887 enum { 1888 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 1889 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 1890 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 1891 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 1892 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 1893 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 1894 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 1895 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 1896 }; 1897 1898 enum { 1899 MLX5_QPC_CS_REQ_DISABLE = 0x0, 1900 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 1901 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 1902 }; 1903 1904 enum { 1905 MLX5_QPC_CS_RES_DISABLE = 0x0, 1906 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 1907 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 1908 }; 1909 1910 struct mlx5_ifc_qpc_bits { 1911 u8 state[0x4]; 1912 u8 lag_tx_port_affinity[0x4]; 1913 u8 st[0x8]; 1914 u8 reserved_1[0x3]; 1915 u8 pm_state[0x2]; 1916 u8 reserved_2[0x7]; 1917 u8 end_padding_mode[0x2]; 1918 u8 reserved_3[0x2]; 1919 1920 u8 wq_signature[0x1]; 1921 u8 block_lb_mc[0x1]; 1922 u8 atomic_like_write_en[0x1]; 1923 u8 latency_sensitive[0x1]; 1924 u8 reserved_4[0x1]; 1925 u8 drain_sigerr[0x1]; 1926 u8 reserved_5[0x2]; 1927 u8 pd[0x18]; 1928 1929 u8 mtu[0x3]; 1930 u8 log_msg_max[0x5]; 1931 u8 reserved_6[0x1]; 1932 u8 log_rq_size[0x4]; 1933 u8 log_rq_stride[0x3]; 1934 u8 no_sq[0x1]; 1935 u8 log_sq_size[0x4]; 1936 u8 reserved_7[0x6]; 1937 u8 rlky[0x1]; 1938 u8 ulp_stateless_offload_mode[0x4]; 1939 1940 u8 counter_set_id[0x8]; 1941 u8 uar_page[0x18]; 1942 1943 u8 reserved_8[0x8]; 1944 u8 user_index[0x18]; 1945 1946 u8 reserved_9[0x3]; 1947 u8 log_page_size[0x5]; 1948 u8 remote_qpn[0x18]; 1949 1950 struct mlx5_ifc_ads_bits primary_address_path; 1951 1952 struct mlx5_ifc_ads_bits secondary_address_path; 1953 1954 u8 log_ack_req_freq[0x4]; 1955 u8 reserved_10[0x4]; 1956 u8 log_sra_max[0x3]; 1957 u8 reserved_11[0x2]; 1958 u8 retry_count[0x3]; 1959 u8 rnr_retry[0x3]; 1960 u8 reserved_12[0x1]; 1961 u8 fre[0x1]; 1962 u8 cur_rnr_retry[0x3]; 1963 u8 cur_retry_count[0x3]; 1964 u8 reserved_13[0x5]; 1965 1966 u8 reserved_14[0x20]; 1967 1968 u8 reserved_15[0x8]; 1969 u8 next_send_psn[0x18]; 1970 1971 u8 reserved_16[0x8]; 1972 u8 cqn_snd[0x18]; 1973 1974 u8 reserved_at_400[0x8]; 1975 1976 u8 deth_sqpn[0x18]; 1977 u8 reserved_17[0x20]; 1978 1979 u8 reserved_18[0x8]; 1980 u8 last_acked_psn[0x18]; 1981 1982 u8 reserved_19[0x8]; 1983 u8 ssn[0x18]; 1984 1985 u8 reserved_20[0x8]; 1986 u8 log_rra_max[0x3]; 1987 u8 reserved_21[0x1]; 1988 u8 atomic_mode[0x4]; 1989 u8 rre[0x1]; 1990 u8 rwe[0x1]; 1991 u8 rae[0x1]; 1992 u8 reserved_22[0x1]; 1993 u8 page_offset[0x6]; 1994 u8 reserved_23[0x3]; 1995 u8 cd_slave_receive[0x1]; 1996 u8 cd_slave_send[0x1]; 1997 u8 cd_master[0x1]; 1998 1999 u8 reserved_24[0x3]; 2000 u8 min_rnr_nak[0x5]; 2001 u8 next_rcv_psn[0x18]; 2002 2003 u8 reserved_25[0x8]; 2004 u8 xrcd[0x18]; 2005 2006 u8 reserved_26[0x8]; 2007 u8 cqn_rcv[0x18]; 2008 2009 u8 dbr_addr[0x40]; 2010 2011 u8 q_key[0x20]; 2012 2013 u8 reserved_27[0x5]; 2014 u8 rq_type[0x3]; 2015 u8 srqn_rmpn[0x18]; 2016 2017 u8 reserved_28[0x8]; 2018 u8 rmsn[0x18]; 2019 2020 u8 hw_sq_wqebb_counter[0x10]; 2021 u8 sw_sq_wqebb_counter[0x10]; 2022 2023 u8 hw_rq_counter[0x20]; 2024 2025 u8 sw_rq_counter[0x20]; 2026 2027 u8 reserved_29[0x20]; 2028 2029 u8 reserved_30[0xf]; 2030 u8 cgs[0x1]; 2031 u8 cs_req[0x8]; 2032 u8 cs_res[0x8]; 2033 2034 u8 dc_access_key[0x40]; 2035 2036 u8 rdma_active[0x1]; 2037 u8 comm_est[0x1]; 2038 u8 suspended[0x1]; 2039 u8 reserved_31[0x5]; 2040 u8 send_msg_psn[0x18]; 2041 2042 u8 reserved_32[0x8]; 2043 u8 rcv_msg_psn[0x18]; 2044 2045 u8 rdma_va[0x40]; 2046 2047 u8 rdma_key[0x20]; 2048 2049 u8 reserved_33[0x20]; 2050 }; 2051 2052 struct mlx5_ifc_roce_addr_layout_bits { 2053 u8 source_l3_address[16][0x8]; 2054 2055 u8 reserved_0[0x3]; 2056 u8 vlan_valid[0x1]; 2057 u8 vlan_id[0xc]; 2058 u8 source_mac_47_32[0x10]; 2059 2060 u8 source_mac_31_0[0x20]; 2061 2062 u8 reserved_1[0x14]; 2063 u8 roce_l3_type[0x4]; 2064 u8 roce_version[0x8]; 2065 2066 u8 reserved_2[0x20]; 2067 }; 2068 2069 struct mlx5_ifc_rdbc_bits { 2070 u8 reserved_0[0x1c]; 2071 u8 type[0x4]; 2072 2073 u8 reserved_1[0x20]; 2074 2075 u8 reserved_2[0x8]; 2076 u8 psn[0x18]; 2077 2078 u8 rkey[0x20]; 2079 2080 u8 address[0x40]; 2081 2082 u8 byte_count[0x20]; 2083 2084 u8 reserved_3[0x20]; 2085 2086 u8 atomic_resp[32][0x8]; 2087 }; 2088 2089 enum { 2090 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 2091 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 2092 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 2093 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 2094 }; 2095 2096 struct mlx5_ifc_flow_context_bits { 2097 u8 reserved_0[0x20]; 2098 2099 u8 group_id[0x20]; 2100 2101 u8 reserved_1[0x8]; 2102 u8 flow_tag[0x18]; 2103 2104 u8 reserved_2[0x10]; 2105 u8 action[0x10]; 2106 2107 u8 reserved_3[0x8]; 2108 u8 destination_list_size[0x18]; 2109 2110 u8 reserved_4[0x8]; 2111 u8 flow_counter_list_size[0x18]; 2112 2113 u8 reserved_5[0x140]; 2114 2115 struct mlx5_ifc_fte_match_param_bits match_value; 2116 2117 u8 reserved_6[0x600]; 2118 2119 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0]; 2120 }; 2121 2122 enum { 2123 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 2124 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 2125 }; 2126 2127 struct mlx5_ifc_xrc_srqc_bits { 2128 u8 state[0x4]; 2129 u8 log_xrc_srq_size[0x4]; 2130 u8 reserved_0[0x18]; 2131 2132 u8 wq_signature[0x1]; 2133 u8 cont_srq[0x1]; 2134 u8 reserved_1[0x1]; 2135 u8 rlky[0x1]; 2136 u8 basic_cyclic_rcv_wqe[0x1]; 2137 u8 log_rq_stride[0x3]; 2138 u8 xrcd[0x18]; 2139 2140 u8 page_offset[0x6]; 2141 u8 reserved_2[0x2]; 2142 u8 cqn[0x18]; 2143 2144 u8 reserved_3[0x20]; 2145 2146 u8 reserved_4[0x2]; 2147 u8 log_page_size[0x6]; 2148 u8 user_index[0x18]; 2149 2150 u8 reserved_5[0x20]; 2151 2152 u8 reserved_6[0x8]; 2153 u8 pd[0x18]; 2154 2155 u8 lwm[0x10]; 2156 u8 wqe_cnt[0x10]; 2157 2158 u8 reserved_7[0x40]; 2159 2160 u8 db_record_addr_h[0x20]; 2161 2162 u8 db_record_addr_l[0x1e]; 2163 u8 reserved_8[0x2]; 2164 2165 u8 reserved_9[0x80]; 2166 }; 2167 2168 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 2169 u8 counter_error_queues[0x20]; 2170 2171 u8 total_error_queues[0x20]; 2172 2173 u8 send_queue_priority_update_flow[0x20]; 2174 2175 u8 reserved_at_60[0x20]; 2176 2177 u8 nic_receive_steering_discard[0x40]; 2178 2179 u8 receive_discard_vport_down[0x40]; 2180 2181 u8 transmit_discard_vport_down[0x40]; 2182 2183 u8 reserved_at_140[0xec0]; 2184 }; 2185 2186 struct mlx5_ifc_traffic_counter_bits { 2187 u8 packets[0x40]; 2188 2189 u8 octets[0x40]; 2190 }; 2191 2192 struct mlx5_ifc_tisc_bits { 2193 u8 strict_lag_tx_port_affinity[0x1]; 2194 u8 reserved_at_1[0x3]; 2195 u8 lag_tx_port_affinity[0x04]; 2196 2197 u8 reserved_at_8[0x4]; 2198 u8 prio[0x4]; 2199 u8 reserved_1[0x10]; 2200 2201 u8 reserved_2[0x100]; 2202 2203 u8 reserved_3[0x8]; 2204 u8 transport_domain[0x18]; 2205 2206 u8 reserved_4[0x8]; 2207 u8 underlay_qpn[0x18]; 2208 2209 u8 reserved_5[0x3a0]; 2210 }; 2211 2212 enum { 2213 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2214 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2215 }; 2216 2217 enum { 2218 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2219 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2220 }; 2221 2222 enum { 2223 MLX5_TIRC_RX_HASH_FN_HASH_NONE = 0x0, 2224 MLX5_TIRC_RX_HASH_FN_HASH_INVERTED_XOR8 = 0x1, 2225 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ = 0x2, 2226 }; 2227 2228 enum { 2229 MLX5_TIRC_SELF_LB_EN_ENABLE_UNICAST = 0x1, 2230 MLX5_TIRC_SELF_LB_EN_ENABLE_MULTICAST = 0x2, 2231 }; 2232 2233 struct mlx5_ifc_tirc_bits { 2234 u8 reserved_0[0x20]; 2235 2236 u8 disp_type[0x4]; 2237 u8 reserved_1[0x1c]; 2238 2239 u8 reserved_2[0x40]; 2240 2241 u8 reserved_3[0x4]; 2242 u8 lro_timeout_period_usecs[0x10]; 2243 u8 lro_enable_mask[0x4]; 2244 u8 lro_max_msg_sz[0x8]; 2245 2246 u8 reserved_4[0x40]; 2247 2248 u8 reserved_5[0x8]; 2249 u8 inline_rqn[0x18]; 2250 2251 u8 rx_hash_symmetric[0x1]; 2252 u8 reserved_6[0x1]; 2253 u8 tunneled_offload_en[0x1]; 2254 u8 reserved_7[0x5]; 2255 u8 indirect_table[0x18]; 2256 2257 u8 rx_hash_fn[0x4]; 2258 u8 reserved_8[0x2]; 2259 u8 self_lb_en[0x2]; 2260 u8 transport_domain[0x18]; 2261 2262 u8 rx_hash_toeplitz_key[10][0x20]; 2263 2264 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2265 2266 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2267 2268 u8 reserved_9[0x4c0]; 2269 }; 2270 2271 enum { 2272 MLX5_SRQC_STATE_GOOD = 0x0, 2273 MLX5_SRQC_STATE_ERROR = 0x1, 2274 }; 2275 2276 struct mlx5_ifc_srqc_bits { 2277 u8 state[0x4]; 2278 u8 log_srq_size[0x4]; 2279 u8 reserved_0[0x18]; 2280 2281 u8 wq_signature[0x1]; 2282 u8 cont_srq[0x1]; 2283 u8 reserved_1[0x1]; 2284 u8 rlky[0x1]; 2285 u8 reserved_2[0x1]; 2286 u8 log_rq_stride[0x3]; 2287 u8 xrcd[0x18]; 2288 2289 u8 page_offset[0x6]; 2290 u8 reserved_3[0x2]; 2291 u8 cqn[0x18]; 2292 2293 u8 reserved_4[0x20]; 2294 2295 u8 reserved_5[0x2]; 2296 u8 log_page_size[0x6]; 2297 u8 reserved_6[0x18]; 2298 2299 u8 reserved_7[0x20]; 2300 2301 u8 reserved_8[0x8]; 2302 u8 pd[0x18]; 2303 2304 u8 lwm[0x10]; 2305 u8 wqe_cnt[0x10]; 2306 2307 u8 reserved_9[0x40]; 2308 2309 u8 dbr_addr[0x40]; 2310 2311 u8 reserved_10[0x80]; 2312 }; 2313 2314 enum { 2315 MLX5_SQC_STATE_RST = 0x0, 2316 MLX5_SQC_STATE_RDY = 0x1, 2317 MLX5_SQC_STATE_ERR = 0x3, 2318 }; 2319 2320 struct mlx5_ifc_sqc_bits { 2321 u8 rlkey[0x1]; 2322 u8 cd_master[0x1]; 2323 u8 fre[0x1]; 2324 u8 flush_in_error_en[0x1]; 2325 u8 allow_multi_pkt_send_wqe[0x1]; 2326 u8 min_wqe_inline_mode[0x3]; 2327 u8 state[0x4]; 2328 u8 reg_umr[0x1]; 2329 u8 allow_swp[0x1]; 2330 u8 reserved_0[0x12]; 2331 2332 u8 reserved_1[0x8]; 2333 u8 user_index[0x18]; 2334 2335 u8 reserved_2[0x8]; 2336 u8 cqn[0x18]; 2337 2338 u8 reserved_3[0x80]; 2339 2340 u8 qos_para_vport_number[0x10]; 2341 u8 packet_pacing_rate_limit_index[0x10]; 2342 2343 u8 tis_lst_sz[0x10]; 2344 u8 reserved_4[0x10]; 2345 2346 u8 reserved_5[0x40]; 2347 2348 u8 reserved_6[0x8]; 2349 u8 tis_num_0[0x18]; 2350 2351 struct mlx5_ifc_wq_bits wq; 2352 }; 2353 2354 enum { 2355 MLX5_TSAR_TYPE_DWRR = 0, 2356 MLX5_TSAR_TYPE_ROUND_ROUBIN = 1, 2357 MLX5_TSAR_TYPE_ETS = 2 2358 }; 2359 2360 struct mlx5_ifc_tsar_element_attributes_bits { 2361 u8 reserved_0[0x8]; 2362 u8 tsar_type[0x8]; 2363 u8 reserved_1[0x10]; 2364 }; 2365 2366 struct mlx5_ifc_vport_element_attributes_bits { 2367 u8 reserved_0[0x10]; 2368 u8 vport_number[0x10]; 2369 }; 2370 2371 struct mlx5_ifc_vport_tc_element_attributes_bits { 2372 u8 traffic_class[0x10]; 2373 u8 vport_number[0x10]; 2374 }; 2375 2376 struct mlx5_ifc_para_vport_tc_element_attributes_bits { 2377 u8 reserved_0[0x0C]; 2378 u8 traffic_class[0x04]; 2379 u8 qos_para_vport_number[0x10]; 2380 }; 2381 2382 enum { 2383 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 2384 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 2385 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 2386 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 2387 }; 2388 2389 struct mlx5_ifc_scheduling_context_bits { 2390 u8 element_type[0x8]; 2391 u8 reserved_at_8[0x18]; 2392 2393 u8 element_attributes[0x20]; 2394 2395 u8 parent_element_id[0x20]; 2396 2397 u8 reserved_at_60[0x40]; 2398 2399 u8 bw_share[0x20]; 2400 2401 u8 max_average_bw[0x20]; 2402 2403 u8 reserved_at_e0[0x120]; 2404 }; 2405 2406 struct mlx5_ifc_rqtc_bits { 2407 u8 reserved_0[0xa0]; 2408 2409 u8 reserved_1[0x10]; 2410 u8 rqt_max_size[0x10]; 2411 2412 u8 reserved_2[0x10]; 2413 u8 rqt_actual_size[0x10]; 2414 2415 u8 reserved_3[0x6a0]; 2416 2417 struct mlx5_ifc_rq_num_bits rq_num[0]; 2418 }; 2419 2420 enum { 2421 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2422 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2423 }; 2424 2425 enum { 2426 MLX5_RQC_STATE_RST = 0x0, 2427 MLX5_RQC_STATE_RDY = 0x1, 2428 MLX5_RQC_STATE_ERR = 0x3, 2429 }; 2430 2431 enum { 2432 MLX5_RQC_DROPLESS_MODE_DISABLE = 0x0, 2433 MLX5_RQC_DROPLESS_MODE_ENABLE = 0x1, 2434 }; 2435 2436 struct mlx5_ifc_rqc_bits { 2437 u8 rlkey[0x1]; 2438 u8 delay_drop_en[0x1]; 2439 u8 scatter_fcs[0x1]; 2440 u8 vlan_strip_disable[0x1]; 2441 u8 mem_rq_type[0x4]; 2442 u8 state[0x4]; 2443 u8 reserved_1[0x1]; 2444 u8 flush_in_error_en[0x1]; 2445 u8 reserved_2[0x12]; 2446 2447 u8 reserved_3[0x8]; 2448 u8 user_index[0x18]; 2449 2450 u8 reserved_4[0x8]; 2451 u8 cqn[0x18]; 2452 2453 u8 counter_set_id[0x8]; 2454 u8 reserved_5[0x18]; 2455 2456 u8 reserved_6[0x8]; 2457 u8 rmpn[0x18]; 2458 2459 u8 reserved_7[0xe0]; 2460 2461 struct mlx5_ifc_wq_bits wq; 2462 }; 2463 2464 enum { 2465 MLX5_RMPC_STATE_RDY = 0x1, 2466 MLX5_RMPC_STATE_ERR = 0x3, 2467 }; 2468 2469 struct mlx5_ifc_rmpc_bits { 2470 u8 reserved_0[0x8]; 2471 u8 state[0x4]; 2472 u8 reserved_1[0x14]; 2473 2474 u8 basic_cyclic_rcv_wqe[0x1]; 2475 u8 reserved_2[0x1f]; 2476 2477 u8 reserved_3[0x140]; 2478 2479 struct mlx5_ifc_wq_bits wq; 2480 }; 2481 2482 enum { 2483 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS = 0x0, 2484 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_MC_MAC_ADDRESS = 0x1, 2485 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_VLAN_LIST = 0x2, 2486 }; 2487 2488 struct mlx5_ifc_nic_vport_context_bits { 2489 u8 reserved_0[0x5]; 2490 u8 min_wqe_inline_mode[0x3]; 2491 u8 reserved_1[0x15]; 2492 u8 disable_mc_local_lb[0x1]; 2493 u8 disable_uc_local_lb[0x1]; 2494 u8 roce_en[0x1]; 2495 2496 u8 arm_change_event[0x1]; 2497 u8 reserved_2[0x1a]; 2498 u8 event_on_mtu[0x1]; 2499 u8 event_on_promisc_change[0x1]; 2500 u8 event_on_vlan_change[0x1]; 2501 u8 event_on_mc_address_change[0x1]; 2502 u8 event_on_uc_address_change[0x1]; 2503 2504 u8 reserved_3[0xe0]; 2505 2506 u8 reserved_4[0x10]; 2507 u8 mtu[0x10]; 2508 2509 u8 system_image_guid[0x40]; 2510 2511 u8 port_guid[0x40]; 2512 2513 u8 node_guid[0x40]; 2514 2515 u8 reserved_5[0x140]; 2516 2517 u8 qkey_violation_counter[0x10]; 2518 u8 reserved_6[0x10]; 2519 2520 u8 reserved_7[0x420]; 2521 2522 u8 promisc_uc[0x1]; 2523 u8 promisc_mc[0x1]; 2524 u8 promisc_all[0x1]; 2525 u8 reserved_8[0x2]; 2526 u8 allowed_list_type[0x3]; 2527 u8 reserved_9[0xc]; 2528 u8 allowed_list_size[0xc]; 2529 2530 struct mlx5_ifc_mac_address_layout_bits permanent_address; 2531 2532 u8 reserved_10[0x20]; 2533 2534 u8 current_uc_mac_address[0][0x40]; 2535 }; 2536 2537 enum { 2538 MLX5_ACCESS_MODE_PA = 0x0, 2539 MLX5_ACCESS_MODE_MTT = 0x1, 2540 MLX5_ACCESS_MODE_KLM = 0x2, 2541 }; 2542 2543 struct mlx5_ifc_mkc_bits { 2544 u8 reserved_at_0[0x1]; 2545 u8 free[0x1]; 2546 u8 reserved_at_2[0x1]; 2547 u8 access_mode_4_2[0x3]; 2548 u8 reserved_at_6[0x7]; 2549 u8 relaxed_ordering_write[0x1]; 2550 u8 reserved_at_e[0x1]; 2551 u8 small_fence_on_rdma_read_response[0x1]; 2552 u8 umr_en[0x1]; 2553 u8 a[0x1]; 2554 u8 rw[0x1]; 2555 u8 rr[0x1]; 2556 u8 lw[0x1]; 2557 u8 lr[0x1]; 2558 u8 access_mode[0x2]; 2559 u8 reserved_2[0x8]; 2560 2561 u8 qpn[0x18]; 2562 u8 mkey_7_0[0x8]; 2563 2564 u8 reserved_3[0x20]; 2565 2566 u8 length64[0x1]; 2567 u8 bsf_en[0x1]; 2568 u8 sync_umr[0x1]; 2569 u8 reserved_4[0x2]; 2570 u8 expected_sigerr_count[0x1]; 2571 u8 reserved_5[0x1]; 2572 u8 en_rinval[0x1]; 2573 u8 pd[0x18]; 2574 2575 u8 start_addr[0x40]; 2576 2577 u8 len[0x40]; 2578 2579 u8 bsf_octword_size[0x20]; 2580 2581 u8 reserved_6[0x80]; 2582 2583 u8 translations_octword_size[0x20]; 2584 2585 u8 reserved_7[0x1b]; 2586 u8 log_page_size[0x5]; 2587 2588 u8 reserved_8[0x20]; 2589 }; 2590 2591 struct mlx5_ifc_pkey_bits { 2592 u8 reserved_0[0x10]; 2593 u8 pkey[0x10]; 2594 }; 2595 2596 struct mlx5_ifc_array128_auto_bits { 2597 u8 array128_auto[16][0x8]; 2598 }; 2599 2600 enum { 2601 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_PORT_GUID = 0x0, 2602 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_NODE_GUID = 0x1, 2603 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_VPORT_STATE_POLICY = 0x2, 2604 }; 2605 2606 enum { 2607 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_SLEEP = 0x1, 2608 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_POLLING = 0x2, 2609 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_DISABLED = 0x3, 2610 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PORTCONFIGURATIONTRAINING = 0x4, 2611 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKUP = 0x5, 2612 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKERRORRECOVERY = 0x6, 2613 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PHYTEST = 0x7, 2614 }; 2615 2616 enum { 2617 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_DOWN = 0x0, 2618 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_UP = 0x1, 2619 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_FOLLOW = 0x2, 2620 }; 2621 2622 enum { 2623 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_DOWN = 0x1, 2624 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_INIT = 0x2, 2625 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ARM = 0x3, 2626 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ACTIVE = 0x4, 2627 }; 2628 2629 enum { 2630 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_DOWN = 0x1, 2631 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_INIT = 0x2, 2632 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ARM = 0x3, 2633 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ACTIVE = 0x4, 2634 }; 2635 2636 struct mlx5_ifc_hca_vport_context_bits { 2637 u8 field_select[0x20]; 2638 2639 u8 reserved_0[0xe0]; 2640 2641 u8 sm_virt_aware[0x1]; 2642 u8 has_smi[0x1]; 2643 u8 has_raw[0x1]; 2644 u8 grh_required[0x1]; 2645 u8 reserved_1[0x1]; 2646 u8 min_wqe_inline_mode[0x3]; 2647 u8 reserved_2[0x8]; 2648 u8 port_physical_state[0x4]; 2649 u8 vport_state_policy[0x4]; 2650 u8 port_state[0x4]; 2651 u8 vport_state[0x4]; 2652 2653 u8 reserved_3[0x20]; 2654 2655 u8 system_image_guid[0x40]; 2656 2657 u8 port_guid[0x40]; 2658 2659 u8 node_guid[0x40]; 2660 2661 u8 cap_mask1[0x20]; 2662 2663 u8 cap_mask1_field_select[0x20]; 2664 2665 u8 cap_mask2[0x20]; 2666 2667 u8 cap_mask2_field_select[0x20]; 2668 2669 u8 reserved_4[0x80]; 2670 2671 u8 lid[0x10]; 2672 u8 reserved_5[0x4]; 2673 u8 init_type_reply[0x4]; 2674 u8 lmc[0x3]; 2675 u8 subnet_timeout[0x5]; 2676 2677 u8 sm_lid[0x10]; 2678 u8 sm_sl[0x4]; 2679 u8 reserved_6[0xc]; 2680 2681 u8 qkey_violation_counter[0x10]; 2682 u8 pkey_violation_counter[0x10]; 2683 2684 u8 reserved_7[0xca0]; 2685 }; 2686 2687 union mlx5_ifc_hca_cap_union_bits { 2688 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2689 struct mlx5_ifc_odp_cap_bits odp_cap; 2690 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2691 struct mlx5_ifc_roce_cap_bits roce_cap; 2692 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2693 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2694 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2695 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2696 struct mlx5_ifc_snapshot_cap_bits snapshot_cap; 2697 struct mlx5_ifc_debug_cap_bits diagnostic_counters_cap; 2698 struct mlx5_ifc_qos_cap_bits qos_cap; 2699 u8 reserved_0[0x8000]; 2700 }; 2701 2702 enum { 2703 MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_DEFAULT = 0x0, 2704 MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_IDENTIFIED = 0x1, 2705 }; 2706 2707 struct mlx5_ifc_flow_table_context_bits { 2708 u8 encap_en[0x1]; 2709 u8 decap_en[0x1]; 2710 u8 reserved_at_2[0x2]; 2711 u8 table_miss_action[0x4]; 2712 u8 level[0x8]; 2713 u8 reserved_at_10[0x8]; 2714 u8 log_size[0x8]; 2715 2716 u8 reserved_at_20[0x8]; 2717 u8 table_miss_id[0x18]; 2718 2719 u8 reserved_at_40[0x8]; 2720 u8 lag_master_next_table_id[0x18]; 2721 2722 u8 reserved_at_60[0xe0]; 2723 }; 2724 2725 struct mlx5_ifc_esw_vport_context_bits { 2726 u8 reserved_0[0x3]; 2727 u8 vport_svlan_strip[0x1]; 2728 u8 vport_cvlan_strip[0x1]; 2729 u8 vport_svlan_insert[0x1]; 2730 u8 vport_cvlan_insert[0x2]; 2731 u8 reserved_1[0x18]; 2732 2733 u8 reserved_2[0x20]; 2734 2735 u8 svlan_cfi[0x1]; 2736 u8 svlan_pcp[0x3]; 2737 u8 svlan_id[0xc]; 2738 u8 cvlan_cfi[0x1]; 2739 u8 cvlan_pcp[0x3]; 2740 u8 cvlan_id[0xc]; 2741 2742 u8 reserved_3[0x7a0]; 2743 }; 2744 2745 enum { 2746 MLX5_EQC_STATUS_OK = 0x0, 2747 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 2748 }; 2749 2750 enum { 2751 MLX5_EQ_STATE_ARMED = 0x9, 2752 MLX5_EQ_STATE_FIRED = 0xa, 2753 }; 2754 2755 struct mlx5_ifc_eqc_bits { 2756 u8 status[0x4]; 2757 u8 reserved_0[0x9]; 2758 u8 ec[0x1]; 2759 u8 oi[0x1]; 2760 u8 reserved_1[0x5]; 2761 u8 st[0x4]; 2762 u8 reserved_2[0x8]; 2763 2764 u8 reserved_3[0x20]; 2765 2766 u8 reserved_4[0x14]; 2767 u8 page_offset[0x6]; 2768 u8 reserved_5[0x6]; 2769 2770 u8 reserved_6[0x3]; 2771 u8 log_eq_size[0x5]; 2772 u8 uar_page[0x18]; 2773 2774 u8 reserved_7[0x20]; 2775 2776 u8 reserved_8[0x18]; 2777 u8 intr[0x8]; 2778 2779 u8 reserved_9[0x3]; 2780 u8 log_page_size[0x5]; 2781 u8 reserved_10[0x18]; 2782 2783 u8 reserved_11[0x60]; 2784 2785 u8 reserved_12[0x8]; 2786 u8 consumer_counter[0x18]; 2787 2788 u8 reserved_13[0x8]; 2789 u8 producer_counter[0x18]; 2790 2791 u8 reserved_14[0x80]; 2792 }; 2793 2794 enum { 2795 MLX5_DCTC_STATE_ACTIVE = 0x0, 2796 MLX5_DCTC_STATE_DRAINING = 0x1, 2797 MLX5_DCTC_STATE_DRAINED = 0x2, 2798 }; 2799 2800 enum { 2801 MLX5_DCTC_CS_RES_DISABLE = 0x0, 2802 MLX5_DCTC_CS_RES_NA = 0x1, 2803 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 2804 }; 2805 2806 enum { 2807 MLX5_DCTC_MTU_256_BYTES = 0x1, 2808 MLX5_DCTC_MTU_512_BYTES = 0x2, 2809 MLX5_DCTC_MTU_1K_BYTES = 0x3, 2810 MLX5_DCTC_MTU_2K_BYTES = 0x4, 2811 MLX5_DCTC_MTU_4K_BYTES = 0x5, 2812 }; 2813 2814 struct mlx5_ifc_dctc_bits { 2815 u8 reserved_0[0x4]; 2816 u8 state[0x4]; 2817 u8 reserved_1[0x18]; 2818 2819 u8 reserved_2[0x8]; 2820 u8 user_index[0x18]; 2821 2822 u8 reserved_3[0x8]; 2823 u8 cqn[0x18]; 2824 2825 u8 counter_set_id[0x8]; 2826 u8 atomic_mode[0x4]; 2827 u8 rre[0x1]; 2828 u8 rwe[0x1]; 2829 u8 rae[0x1]; 2830 u8 atomic_like_write_en[0x1]; 2831 u8 latency_sensitive[0x1]; 2832 u8 rlky[0x1]; 2833 u8 reserved_4[0xe]; 2834 2835 u8 reserved_5[0x8]; 2836 u8 cs_res[0x8]; 2837 u8 reserved_6[0x3]; 2838 u8 min_rnr_nak[0x5]; 2839 u8 reserved_7[0x8]; 2840 2841 u8 reserved_8[0x8]; 2842 u8 srqn[0x18]; 2843 2844 u8 reserved_9[0x8]; 2845 u8 pd[0x18]; 2846 2847 u8 tclass[0x8]; 2848 u8 reserved_10[0x4]; 2849 u8 flow_label[0x14]; 2850 2851 u8 dc_access_key[0x40]; 2852 2853 u8 reserved_11[0x5]; 2854 u8 mtu[0x3]; 2855 u8 port[0x8]; 2856 u8 pkey_index[0x10]; 2857 2858 u8 reserved_12[0x8]; 2859 u8 my_addr_index[0x8]; 2860 u8 reserved_13[0x8]; 2861 u8 hop_limit[0x8]; 2862 2863 u8 dc_access_key_violation_count[0x20]; 2864 2865 u8 reserved_14[0x14]; 2866 u8 dei_cfi[0x1]; 2867 u8 eth_prio[0x3]; 2868 u8 ecn[0x2]; 2869 u8 dscp[0x6]; 2870 2871 u8 reserved_15[0x40]; 2872 }; 2873 2874 enum { 2875 MLX5_CQC_STATUS_OK = 0x0, 2876 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 2877 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 2878 }; 2879 2880 enum { 2881 CQE_SIZE_64 = 0x0, 2882 CQE_SIZE_128 = 0x1, 2883 }; 2884 2885 enum { 2886 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 2887 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 2888 }; 2889 2890 enum { 2891 MLX5_CQ_STATE_SOLICITED_ARMED = 0x6, 2892 MLX5_CQ_STATE_ARMED = 0x9, 2893 MLX5_CQ_STATE_FIRED = 0xa, 2894 }; 2895 2896 struct mlx5_ifc_cqc_bits { 2897 u8 status[0x4]; 2898 u8 reserved_0[0x4]; 2899 u8 cqe_sz[0x3]; 2900 u8 cc[0x1]; 2901 u8 reserved_1[0x1]; 2902 u8 scqe_break_moderation_en[0x1]; 2903 u8 oi[0x1]; 2904 u8 cq_period_mode[0x2]; 2905 u8 cqe_compression_en[0x1]; 2906 u8 mini_cqe_res_format[0x2]; 2907 u8 st[0x4]; 2908 u8 reserved_2[0x8]; 2909 2910 u8 reserved_3[0x20]; 2911 2912 u8 reserved_4[0x14]; 2913 u8 page_offset[0x6]; 2914 u8 reserved_5[0x6]; 2915 2916 u8 reserved_6[0x3]; 2917 u8 log_cq_size[0x5]; 2918 u8 uar_page[0x18]; 2919 2920 u8 reserved_7[0x4]; 2921 u8 cq_period[0xc]; 2922 u8 cq_max_count[0x10]; 2923 2924 u8 reserved_8[0x18]; 2925 u8 c_eqn[0x8]; 2926 2927 u8 reserved_9[0x3]; 2928 u8 log_page_size[0x5]; 2929 u8 reserved_10[0x18]; 2930 2931 u8 reserved_11[0x20]; 2932 2933 u8 reserved_12[0x8]; 2934 u8 last_notified_index[0x18]; 2935 2936 u8 reserved_13[0x8]; 2937 u8 last_solicit_index[0x18]; 2938 2939 u8 reserved_14[0x8]; 2940 u8 consumer_counter[0x18]; 2941 2942 u8 reserved_15[0x8]; 2943 u8 producer_counter[0x18]; 2944 2945 u8 reserved_16[0x40]; 2946 2947 u8 dbr_addr[0x40]; 2948 }; 2949 2950 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 2951 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 2952 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 2953 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 2954 u8 reserved_0[0x800]; 2955 }; 2956 2957 struct mlx5_ifc_query_adapter_param_block_bits { 2958 u8 reserved_0[0xc0]; 2959 2960 u8 reserved_1[0x8]; 2961 u8 ieee_vendor_id[0x18]; 2962 2963 u8 reserved_2[0x10]; 2964 u8 vsd_vendor_id[0x10]; 2965 2966 u8 vsd[208][0x8]; 2967 2968 u8 vsd_contd_psid[16][0x8]; 2969 }; 2970 2971 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 2972 struct mlx5_ifc_modify_field_select_bits modify_field_select; 2973 struct mlx5_ifc_resize_field_select_bits resize_field_select; 2974 u8 reserved_0[0x20]; 2975 }; 2976 2977 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 2978 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 2979 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 2980 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 2981 u8 reserved_0[0x20]; 2982 }; 2983 2984 struct mlx5_ifc_bufferx_reg_bits { 2985 u8 reserved_0[0x6]; 2986 u8 lossy[0x1]; 2987 u8 epsb[0x1]; 2988 u8 reserved_1[0xc]; 2989 u8 size[0xc]; 2990 2991 u8 xoff_threshold[0x10]; 2992 u8 xon_threshold[0x10]; 2993 }; 2994 2995 struct mlx5_ifc_config_item_bits { 2996 u8 valid[0x2]; 2997 u8 reserved_0[0x2]; 2998 u8 header_type[0x2]; 2999 u8 reserved_1[0x2]; 3000 u8 default_location[0x1]; 3001 u8 reserved_2[0x7]; 3002 u8 version[0x4]; 3003 u8 reserved_3[0x3]; 3004 u8 length[0x9]; 3005 3006 u8 type[0x20]; 3007 3008 u8 reserved_4[0x10]; 3009 u8 crc16[0x10]; 3010 }; 3011 3012 struct mlx5_ifc_nodnic_port_config_reg_bits { 3013 struct mlx5_ifc_nodnic_event_word_bits event; 3014 3015 u8 network_en[0x1]; 3016 u8 dma_en[0x1]; 3017 u8 promisc_en[0x1]; 3018 u8 promisc_multicast_en[0x1]; 3019 u8 reserved_0[0x17]; 3020 u8 receive_filter_en[0x5]; 3021 3022 u8 reserved_1[0x10]; 3023 u8 mac_47_32[0x10]; 3024 3025 u8 mac_31_0[0x20]; 3026 3027 u8 receive_filters_mgid_mac[64][0x8]; 3028 3029 u8 gid[16][0x8]; 3030 3031 u8 reserved_2[0x10]; 3032 u8 lid[0x10]; 3033 3034 u8 reserved_3[0xc]; 3035 u8 sm_sl[0x4]; 3036 u8 sm_lid[0x10]; 3037 3038 u8 completion_address_63_32[0x20]; 3039 3040 u8 completion_address_31_12[0x14]; 3041 u8 reserved_4[0x6]; 3042 u8 log_cq_size[0x6]; 3043 3044 u8 working_buffer_address_63_32[0x20]; 3045 3046 u8 working_buffer_address_31_12[0x14]; 3047 u8 reserved_5[0xc]; 3048 3049 struct mlx5_ifc_nodnic_cq_arming_word_bits arm_cq; 3050 3051 u8 pkey_index[0x10]; 3052 u8 pkey[0x10]; 3053 3054 struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring0; 3055 3056 struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring1; 3057 3058 struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring0; 3059 3060 struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring1; 3061 3062 u8 reserved_6[0x400]; 3063 }; 3064 3065 union mlx5_ifc_event_auto_bits { 3066 struct mlx5_ifc_comp_event_bits comp_event; 3067 struct mlx5_ifc_dct_events_bits dct_events; 3068 struct mlx5_ifc_qp_events_bits qp_events; 3069 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 3070 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 3071 struct mlx5_ifc_cq_error_bits cq_error; 3072 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 3073 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 3074 struct mlx5_ifc_gpio_event_bits gpio_event; 3075 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 3076 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 3077 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 3078 struct mlx5_ifc_pages_req_event_bits pages_req_event; 3079 struct mlx5_ifc_nic_vport_change_event_bits nic_vport_change_event; 3080 u8 reserved_0[0xe0]; 3081 }; 3082 3083 struct mlx5_ifc_health_buffer_bits { 3084 u8 reserved_0[0x100]; 3085 3086 u8 assert_existptr[0x20]; 3087 3088 u8 assert_callra[0x20]; 3089 3090 u8 reserved_1[0x40]; 3091 3092 u8 fw_version[0x20]; 3093 3094 u8 hw_id[0x20]; 3095 3096 u8 reserved_2[0x20]; 3097 3098 u8 irisc_index[0x8]; 3099 u8 synd[0x8]; 3100 u8 ext_synd[0x10]; 3101 }; 3102 3103 struct mlx5_ifc_register_loopback_control_bits { 3104 u8 no_lb[0x1]; 3105 u8 reserved_0[0x7]; 3106 u8 port[0x8]; 3107 u8 reserved_1[0x10]; 3108 3109 u8 reserved_2[0x60]; 3110 }; 3111 3112 struct mlx5_ifc_lrh_bits { 3113 u8 vl[4]; 3114 u8 lver[4]; 3115 u8 sl[4]; 3116 u8 reserved2[2]; 3117 u8 lnh[2]; 3118 u8 dlid[16]; 3119 u8 reserved5[5]; 3120 u8 pkt_len[11]; 3121 u8 slid[16]; 3122 }; 3123 3124 struct mlx5_ifc_icmd_set_wol_rol_out_bits { 3125 u8 reserved_0[0x40]; 3126 3127 u8 reserved_1[0x10]; 3128 u8 rol_mode[0x8]; 3129 u8 wol_mode[0x8]; 3130 }; 3131 3132 struct mlx5_ifc_icmd_set_wol_rol_in_bits { 3133 u8 reserved_0[0x40]; 3134 3135 u8 rol_mode_valid[0x1]; 3136 u8 wol_mode_valid[0x1]; 3137 u8 reserved_1[0xe]; 3138 u8 rol_mode[0x8]; 3139 u8 wol_mode[0x8]; 3140 3141 u8 reserved_2[0x7a0]; 3142 }; 3143 3144 struct mlx5_ifc_icmd_set_virtual_mac_in_bits { 3145 u8 virtual_mac_en[0x1]; 3146 u8 mac_aux_v[0x1]; 3147 u8 reserved_0[0x1e]; 3148 3149 u8 reserved_1[0x40]; 3150 3151 struct mlx5_ifc_mac_address_layout_bits virtual_mac; 3152 3153 u8 reserved_2[0x760]; 3154 }; 3155 3156 struct mlx5_ifc_icmd_query_virtual_mac_out_bits { 3157 u8 virtual_mac_en[0x1]; 3158 u8 mac_aux_v[0x1]; 3159 u8 reserved_0[0x1e]; 3160 3161 struct mlx5_ifc_mac_address_layout_bits permanent_mac; 3162 3163 struct mlx5_ifc_mac_address_layout_bits virtual_mac; 3164 3165 u8 reserved_1[0x760]; 3166 }; 3167 3168 struct mlx5_ifc_icmd_query_fw_info_out_bits { 3169 struct mlx5_ifc_fw_version_bits fw_version; 3170 3171 u8 reserved_0[0x10]; 3172 u8 hash_signature[0x10]; 3173 3174 u8 psid[16][0x8]; 3175 3176 u8 reserved_1[0x6e0]; 3177 }; 3178 3179 struct mlx5_ifc_icmd_query_cap_in_bits { 3180 u8 reserved_0[0x10]; 3181 u8 capability_group[0x10]; 3182 }; 3183 3184 struct mlx5_ifc_icmd_query_cap_general_bits { 3185 u8 nv_access[0x1]; 3186 u8 fw_info_psid[0x1]; 3187 u8 reserved_0[0x1e]; 3188 3189 u8 reserved_1[0x16]; 3190 u8 rol_s[0x1]; 3191 u8 rol_g[0x1]; 3192 u8 reserved_2[0x1]; 3193 u8 wol_s[0x1]; 3194 u8 wol_g[0x1]; 3195 u8 wol_a[0x1]; 3196 u8 wol_b[0x1]; 3197 u8 wol_m[0x1]; 3198 u8 wol_u[0x1]; 3199 u8 wol_p[0x1]; 3200 }; 3201 3202 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits { 3203 u8 status[0x8]; 3204 u8 reserved_0[0x18]; 3205 3206 u8 reserved_1[0x7e0]; 3207 }; 3208 3209 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits { 3210 u8 status[0x8]; 3211 u8 reserved_0[0x18]; 3212 3213 u8 reserved_1[0x7e0]; 3214 }; 3215 3216 struct mlx5_ifc_icmd_ocbb_init_in_bits { 3217 u8 address_hi[0x20]; 3218 3219 u8 address_lo[0x20]; 3220 3221 u8 reserved_0[0x7c0]; 3222 }; 3223 3224 struct mlx5_ifc_icmd_init_ocsd_in_bits { 3225 u8 reserved_0[0x20]; 3226 3227 u8 address_hi[0x20]; 3228 3229 u8 address_lo[0x20]; 3230 3231 u8 reserved_1[0x7a0]; 3232 }; 3233 3234 struct mlx5_ifc_icmd_access_reg_out_bits { 3235 u8 reserved_0[0x11]; 3236 u8 status[0x7]; 3237 u8 reserved_1[0x8]; 3238 3239 u8 register_id[0x10]; 3240 u8 reserved_2[0x10]; 3241 3242 u8 reserved_3[0x40]; 3243 3244 u8 reserved_4[0x5]; 3245 u8 len[0xb]; 3246 u8 reserved_5[0x10]; 3247 3248 u8 register_data[0][0x20]; 3249 }; 3250 3251 enum { 3252 MLX5_ICMD_ACCESS_REG_IN_METHOD_QUERY = 0x1, 3253 MLX5_ICMD_ACCESS_REG_IN_METHOD_WRITE = 0x2, 3254 }; 3255 3256 struct mlx5_ifc_icmd_access_reg_in_bits { 3257 u8 constant_1[0x5]; 3258 u8 constant_2[0xb]; 3259 u8 reserved_0[0x10]; 3260 3261 u8 register_id[0x10]; 3262 u8 reserved_1[0x1]; 3263 u8 method[0x7]; 3264 u8 constant_3[0x8]; 3265 3266 u8 reserved_2[0x40]; 3267 3268 u8 constant_4[0x5]; 3269 u8 len[0xb]; 3270 u8 reserved_3[0x10]; 3271 3272 u8 register_data[0][0x20]; 3273 }; 3274 3275 enum { 3276 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 3277 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 3278 }; 3279 3280 struct mlx5_ifc_teardown_hca_out_bits { 3281 u8 status[0x8]; 3282 u8 reserved_0[0x18]; 3283 3284 u8 syndrome[0x20]; 3285 3286 u8 reserved_1[0x3f]; 3287 3288 u8 state[0x1]; 3289 }; 3290 3291 enum { 3292 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 3293 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 3294 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 3295 }; 3296 3297 struct mlx5_ifc_teardown_hca_in_bits { 3298 u8 opcode[0x10]; 3299 u8 reserved_0[0x10]; 3300 3301 u8 reserved_1[0x10]; 3302 u8 op_mod[0x10]; 3303 3304 u8 reserved_2[0x10]; 3305 u8 profile[0x10]; 3306 3307 u8 reserved_3[0x20]; 3308 }; 3309 3310 struct mlx5_ifc_set_delay_drop_params_out_bits { 3311 u8 status[0x8]; 3312 u8 reserved_at_8[0x18]; 3313 3314 u8 syndrome[0x20]; 3315 3316 u8 reserved_at_40[0x40]; 3317 }; 3318 3319 struct mlx5_ifc_set_delay_drop_params_in_bits { 3320 u8 opcode[0x10]; 3321 u8 reserved_at_10[0x10]; 3322 3323 u8 reserved_at_20[0x10]; 3324 u8 op_mod[0x10]; 3325 3326 u8 reserved_at_40[0x20]; 3327 3328 u8 reserved_at_60[0x10]; 3329 u8 delay_drop_timeout[0x10]; 3330 }; 3331 3332 struct mlx5_ifc_query_delay_drop_params_out_bits { 3333 u8 status[0x8]; 3334 u8 reserved_at_8[0x18]; 3335 3336 u8 syndrome[0x20]; 3337 3338 u8 reserved_at_40[0x20]; 3339 3340 u8 reserved_at_60[0x10]; 3341 u8 delay_drop_timeout[0x10]; 3342 }; 3343 3344 struct mlx5_ifc_query_delay_drop_params_in_bits { 3345 u8 opcode[0x10]; 3346 u8 reserved_at_10[0x10]; 3347 3348 u8 reserved_at_20[0x10]; 3349 u8 op_mod[0x10]; 3350 3351 u8 reserved_at_40[0x40]; 3352 }; 3353 3354 struct mlx5_ifc_suspend_qp_out_bits { 3355 u8 status[0x8]; 3356 u8 reserved_0[0x18]; 3357 3358 u8 syndrome[0x20]; 3359 3360 u8 reserved_1[0x40]; 3361 }; 3362 3363 struct mlx5_ifc_suspend_qp_in_bits { 3364 u8 opcode[0x10]; 3365 u8 reserved_0[0x10]; 3366 3367 u8 reserved_1[0x10]; 3368 u8 op_mod[0x10]; 3369 3370 u8 reserved_2[0x8]; 3371 u8 qpn[0x18]; 3372 3373 u8 reserved_3[0x20]; 3374 }; 3375 3376 struct mlx5_ifc_sqerr2rts_qp_out_bits { 3377 u8 status[0x8]; 3378 u8 reserved_0[0x18]; 3379 3380 u8 syndrome[0x20]; 3381 3382 u8 reserved_1[0x40]; 3383 }; 3384 3385 struct mlx5_ifc_sqerr2rts_qp_in_bits { 3386 u8 opcode[0x10]; 3387 u8 reserved_0[0x10]; 3388 3389 u8 reserved_1[0x10]; 3390 u8 op_mod[0x10]; 3391 3392 u8 reserved_2[0x8]; 3393 u8 qpn[0x18]; 3394 3395 u8 reserved_3[0x20]; 3396 3397 u8 opt_param_mask[0x20]; 3398 3399 u8 reserved_4[0x20]; 3400 3401 struct mlx5_ifc_qpc_bits qpc; 3402 3403 u8 reserved_5[0x80]; 3404 }; 3405 3406 struct mlx5_ifc_sqd2rts_qp_out_bits { 3407 u8 status[0x8]; 3408 u8 reserved_0[0x18]; 3409 3410 u8 syndrome[0x20]; 3411 3412 u8 reserved_1[0x40]; 3413 }; 3414 3415 struct mlx5_ifc_sqd2rts_qp_in_bits { 3416 u8 opcode[0x10]; 3417 u8 reserved_0[0x10]; 3418 3419 u8 reserved_1[0x10]; 3420 u8 op_mod[0x10]; 3421 3422 u8 reserved_2[0x8]; 3423 u8 qpn[0x18]; 3424 3425 u8 reserved_3[0x20]; 3426 3427 u8 opt_param_mask[0x20]; 3428 3429 u8 reserved_4[0x20]; 3430 3431 struct mlx5_ifc_qpc_bits qpc; 3432 3433 u8 reserved_5[0x80]; 3434 }; 3435 3436 struct mlx5_ifc_set_wol_rol_out_bits { 3437 u8 status[0x8]; 3438 u8 reserved_0[0x18]; 3439 3440 u8 syndrome[0x20]; 3441 3442 u8 reserved_1[0x40]; 3443 }; 3444 3445 struct mlx5_ifc_set_wol_rol_in_bits { 3446 u8 opcode[0x10]; 3447 u8 reserved_0[0x10]; 3448 3449 u8 reserved_1[0x10]; 3450 u8 op_mod[0x10]; 3451 3452 u8 rol_mode_valid[0x1]; 3453 u8 wol_mode_valid[0x1]; 3454 u8 reserved_2[0xe]; 3455 u8 rol_mode[0x8]; 3456 u8 wol_mode[0x8]; 3457 3458 u8 reserved_3[0x20]; 3459 }; 3460 3461 struct mlx5_ifc_set_roce_address_out_bits { 3462 u8 status[0x8]; 3463 u8 reserved_0[0x18]; 3464 3465 u8 syndrome[0x20]; 3466 3467 u8 reserved_1[0x40]; 3468 }; 3469 3470 struct mlx5_ifc_set_roce_address_in_bits { 3471 u8 opcode[0x10]; 3472 u8 reserved_0[0x10]; 3473 3474 u8 reserved_1[0x10]; 3475 u8 op_mod[0x10]; 3476 3477 u8 roce_address_index[0x10]; 3478 u8 reserved_2[0x10]; 3479 3480 u8 reserved_3[0x20]; 3481 3482 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3483 }; 3484 3485 struct mlx5_ifc_set_rdb_out_bits { 3486 u8 status[0x8]; 3487 u8 reserved_0[0x18]; 3488 3489 u8 syndrome[0x20]; 3490 3491 u8 reserved_1[0x40]; 3492 }; 3493 3494 struct mlx5_ifc_set_rdb_in_bits { 3495 u8 opcode[0x10]; 3496 u8 reserved_0[0x10]; 3497 3498 u8 reserved_1[0x10]; 3499 u8 op_mod[0x10]; 3500 3501 u8 reserved_2[0x8]; 3502 u8 qpn[0x18]; 3503 3504 u8 reserved_3[0x18]; 3505 u8 rdb_list_size[0x8]; 3506 3507 struct mlx5_ifc_rdbc_bits rdb_context[0]; 3508 }; 3509 3510 struct mlx5_ifc_set_mad_demux_out_bits { 3511 u8 status[0x8]; 3512 u8 reserved_0[0x18]; 3513 3514 u8 syndrome[0x20]; 3515 3516 u8 reserved_1[0x40]; 3517 }; 3518 3519 enum { 3520 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 3521 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 3522 }; 3523 3524 struct mlx5_ifc_set_mad_demux_in_bits { 3525 u8 opcode[0x10]; 3526 u8 reserved_0[0x10]; 3527 3528 u8 reserved_1[0x10]; 3529 u8 op_mod[0x10]; 3530 3531 u8 reserved_2[0x20]; 3532 3533 u8 reserved_3[0x6]; 3534 u8 demux_mode[0x2]; 3535 u8 reserved_4[0x18]; 3536 }; 3537 3538 struct mlx5_ifc_set_l2_table_entry_out_bits { 3539 u8 status[0x8]; 3540 u8 reserved_0[0x18]; 3541 3542 u8 syndrome[0x20]; 3543 3544 u8 reserved_1[0x40]; 3545 }; 3546 3547 struct mlx5_ifc_set_l2_table_entry_in_bits { 3548 u8 opcode[0x10]; 3549 u8 reserved_0[0x10]; 3550 3551 u8 reserved_1[0x10]; 3552 u8 op_mod[0x10]; 3553 3554 u8 reserved_2[0x60]; 3555 3556 u8 reserved_3[0x8]; 3557 u8 table_index[0x18]; 3558 3559 u8 reserved_4[0x20]; 3560 3561 u8 reserved_5[0x13]; 3562 u8 vlan_valid[0x1]; 3563 u8 vlan[0xc]; 3564 3565 struct mlx5_ifc_mac_address_layout_bits mac_address; 3566 3567 u8 reserved_6[0xc0]; 3568 }; 3569 3570 struct mlx5_ifc_set_issi_out_bits { 3571 u8 status[0x8]; 3572 u8 reserved_0[0x18]; 3573 3574 u8 syndrome[0x20]; 3575 3576 u8 reserved_1[0x40]; 3577 }; 3578 3579 struct mlx5_ifc_set_issi_in_bits { 3580 u8 opcode[0x10]; 3581 u8 reserved_0[0x10]; 3582 3583 u8 reserved_1[0x10]; 3584 u8 op_mod[0x10]; 3585 3586 u8 reserved_2[0x10]; 3587 u8 current_issi[0x10]; 3588 3589 u8 reserved_3[0x20]; 3590 }; 3591 3592 struct mlx5_ifc_set_hca_cap_out_bits { 3593 u8 status[0x8]; 3594 u8 reserved_0[0x18]; 3595 3596 u8 syndrome[0x20]; 3597 3598 u8 reserved_1[0x40]; 3599 }; 3600 3601 struct mlx5_ifc_set_hca_cap_in_bits { 3602 u8 opcode[0x10]; 3603 u8 reserved_0[0x10]; 3604 3605 u8 reserved_1[0x10]; 3606 u8 op_mod[0x10]; 3607 3608 u8 reserved_2[0x40]; 3609 3610 union mlx5_ifc_hca_cap_union_bits capability; 3611 }; 3612 3613 enum { 3614 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 3615 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 3616 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 3617 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 3618 }; 3619 3620 struct mlx5_ifc_set_flow_table_root_out_bits { 3621 u8 status[0x8]; 3622 u8 reserved_0[0x18]; 3623 3624 u8 syndrome[0x20]; 3625 3626 u8 reserved_1[0x40]; 3627 }; 3628 3629 struct mlx5_ifc_set_flow_table_root_in_bits { 3630 u8 opcode[0x10]; 3631 u8 reserved_0[0x10]; 3632 3633 u8 reserved_1[0x10]; 3634 u8 op_mod[0x10]; 3635 3636 u8 other_vport[0x1]; 3637 u8 reserved_2[0xf]; 3638 u8 vport_number[0x10]; 3639 3640 u8 reserved_3[0x20]; 3641 3642 u8 table_type[0x8]; 3643 u8 reserved_4[0x18]; 3644 3645 u8 reserved_5[0x8]; 3646 u8 table_id[0x18]; 3647 3648 u8 reserved_6[0x8]; 3649 u8 underlay_qpn[0x18]; 3650 3651 u8 reserved_7[0x120]; 3652 }; 3653 3654 struct mlx5_ifc_set_fte_out_bits { 3655 u8 status[0x8]; 3656 u8 reserved_0[0x18]; 3657 3658 u8 syndrome[0x20]; 3659 3660 u8 reserved_1[0x40]; 3661 }; 3662 3663 struct mlx5_ifc_set_fte_in_bits { 3664 u8 opcode[0x10]; 3665 u8 reserved_0[0x10]; 3666 3667 u8 reserved_1[0x10]; 3668 u8 op_mod[0x10]; 3669 3670 u8 other_vport[0x1]; 3671 u8 reserved_2[0xf]; 3672 u8 vport_number[0x10]; 3673 3674 u8 reserved_3[0x20]; 3675 3676 u8 table_type[0x8]; 3677 u8 reserved_4[0x18]; 3678 3679 u8 reserved_5[0x8]; 3680 u8 table_id[0x18]; 3681 3682 u8 reserved_6[0x18]; 3683 u8 modify_enable_mask[0x8]; 3684 3685 u8 reserved_7[0x20]; 3686 3687 u8 flow_index[0x20]; 3688 3689 u8 reserved_8[0xe0]; 3690 3691 struct mlx5_ifc_flow_context_bits flow_context; 3692 }; 3693 3694 struct mlx5_ifc_set_driver_version_out_bits { 3695 u8 status[0x8]; 3696 u8 reserved_0[0x18]; 3697 3698 u8 syndrome[0x20]; 3699 3700 u8 reserved_1[0x40]; 3701 }; 3702 3703 struct mlx5_ifc_set_driver_version_in_bits { 3704 u8 opcode[0x10]; 3705 u8 reserved_0[0x10]; 3706 3707 u8 reserved_1[0x10]; 3708 u8 op_mod[0x10]; 3709 3710 u8 reserved_2[0x40]; 3711 3712 u8 driver_version[64][0x8]; 3713 }; 3714 3715 struct mlx5_ifc_set_dc_cnak_trace_out_bits { 3716 u8 status[0x8]; 3717 u8 reserved_0[0x18]; 3718 3719 u8 syndrome[0x20]; 3720 3721 u8 reserved_1[0x40]; 3722 }; 3723 3724 struct mlx5_ifc_set_dc_cnak_trace_in_bits { 3725 u8 opcode[0x10]; 3726 u8 reserved_0[0x10]; 3727 3728 u8 reserved_1[0x10]; 3729 u8 op_mod[0x10]; 3730 3731 u8 enable[0x1]; 3732 u8 reserved_2[0x1f]; 3733 3734 u8 reserved_3[0x160]; 3735 3736 struct mlx5_ifc_cmd_pas_bits pas; 3737 }; 3738 3739 struct mlx5_ifc_set_burst_size_out_bits { 3740 u8 status[0x8]; 3741 u8 reserved_0[0x18]; 3742 3743 u8 syndrome[0x20]; 3744 3745 u8 reserved_1[0x40]; 3746 }; 3747 3748 struct mlx5_ifc_set_burst_size_in_bits { 3749 u8 opcode[0x10]; 3750 u8 reserved_0[0x10]; 3751 3752 u8 reserved_1[0x10]; 3753 u8 op_mod[0x10]; 3754 3755 u8 reserved_2[0x20]; 3756 3757 u8 reserved_3[0x9]; 3758 u8 device_burst_size[0x17]; 3759 }; 3760 3761 struct mlx5_ifc_rts2rts_qp_out_bits { 3762 u8 status[0x8]; 3763 u8 reserved_0[0x18]; 3764 3765 u8 syndrome[0x20]; 3766 3767 u8 reserved_1[0x40]; 3768 }; 3769 3770 struct mlx5_ifc_rts2rts_qp_in_bits { 3771 u8 opcode[0x10]; 3772 u8 reserved_0[0x10]; 3773 3774 u8 reserved_1[0x10]; 3775 u8 op_mod[0x10]; 3776 3777 u8 reserved_2[0x8]; 3778 u8 qpn[0x18]; 3779 3780 u8 reserved_3[0x20]; 3781 3782 u8 opt_param_mask[0x20]; 3783 3784 u8 reserved_4[0x20]; 3785 3786 struct mlx5_ifc_qpc_bits qpc; 3787 3788 u8 reserved_5[0x80]; 3789 }; 3790 3791 struct mlx5_ifc_rtr2rts_qp_out_bits { 3792 u8 status[0x8]; 3793 u8 reserved_0[0x18]; 3794 3795 u8 syndrome[0x20]; 3796 3797 u8 reserved_1[0x40]; 3798 }; 3799 3800 struct mlx5_ifc_rtr2rts_qp_in_bits { 3801 u8 opcode[0x10]; 3802 u8 reserved_0[0x10]; 3803 3804 u8 reserved_1[0x10]; 3805 u8 op_mod[0x10]; 3806 3807 u8 reserved_2[0x8]; 3808 u8 qpn[0x18]; 3809 3810 u8 reserved_3[0x20]; 3811 3812 u8 opt_param_mask[0x20]; 3813 3814 u8 reserved_4[0x20]; 3815 3816 struct mlx5_ifc_qpc_bits qpc; 3817 3818 u8 reserved_5[0x80]; 3819 }; 3820 3821 struct mlx5_ifc_rst2init_qp_out_bits { 3822 u8 status[0x8]; 3823 u8 reserved_0[0x18]; 3824 3825 u8 syndrome[0x20]; 3826 3827 u8 reserved_1[0x40]; 3828 }; 3829 3830 struct mlx5_ifc_rst2init_qp_in_bits { 3831 u8 opcode[0x10]; 3832 u8 reserved_0[0x10]; 3833 3834 u8 reserved_1[0x10]; 3835 u8 op_mod[0x10]; 3836 3837 u8 reserved_2[0x8]; 3838 u8 qpn[0x18]; 3839 3840 u8 reserved_3[0x20]; 3841 3842 u8 opt_param_mask[0x20]; 3843 3844 u8 reserved_4[0x20]; 3845 3846 struct mlx5_ifc_qpc_bits qpc; 3847 3848 u8 reserved_5[0x80]; 3849 }; 3850 3851 struct mlx5_ifc_resume_qp_out_bits { 3852 u8 status[0x8]; 3853 u8 reserved_0[0x18]; 3854 3855 u8 syndrome[0x20]; 3856 3857 u8 reserved_1[0x40]; 3858 }; 3859 3860 struct mlx5_ifc_resume_qp_in_bits { 3861 u8 opcode[0x10]; 3862 u8 reserved_0[0x10]; 3863 3864 u8 reserved_1[0x10]; 3865 u8 op_mod[0x10]; 3866 3867 u8 reserved_2[0x8]; 3868 u8 qpn[0x18]; 3869 3870 u8 reserved_3[0x20]; 3871 }; 3872 3873 struct mlx5_ifc_query_xrc_srq_out_bits { 3874 u8 status[0x8]; 3875 u8 reserved_0[0x18]; 3876 3877 u8 syndrome[0x20]; 3878 3879 u8 reserved_1[0x40]; 3880 3881 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 3882 3883 u8 reserved_2[0x600]; 3884 3885 u8 pas[0][0x40]; 3886 }; 3887 3888 struct mlx5_ifc_query_xrc_srq_in_bits { 3889 u8 opcode[0x10]; 3890 u8 reserved_0[0x10]; 3891 3892 u8 reserved_1[0x10]; 3893 u8 op_mod[0x10]; 3894 3895 u8 reserved_2[0x8]; 3896 u8 xrc_srqn[0x18]; 3897 3898 u8 reserved_3[0x20]; 3899 }; 3900 3901 struct mlx5_ifc_query_wol_rol_out_bits { 3902 u8 status[0x8]; 3903 u8 reserved_0[0x18]; 3904 3905 u8 syndrome[0x20]; 3906 3907 u8 reserved_1[0x10]; 3908 u8 rol_mode[0x8]; 3909 u8 wol_mode[0x8]; 3910 3911 u8 reserved_2[0x20]; 3912 }; 3913 3914 struct mlx5_ifc_query_wol_rol_in_bits { 3915 u8 opcode[0x10]; 3916 u8 reserved_0[0x10]; 3917 3918 u8 reserved_1[0x10]; 3919 u8 op_mod[0x10]; 3920 3921 u8 reserved_2[0x40]; 3922 }; 3923 3924 enum { 3925 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 3926 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 3927 }; 3928 3929 struct mlx5_ifc_query_vport_state_out_bits { 3930 u8 status[0x8]; 3931 u8 reserved_0[0x18]; 3932 3933 u8 syndrome[0x20]; 3934 3935 u8 reserved_1[0x20]; 3936 3937 u8 reserved_2[0x18]; 3938 u8 admin_state[0x4]; 3939 u8 state[0x4]; 3940 }; 3941 3942 enum { 3943 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0, 3944 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, 3945 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_UPLINK = 0x2, 3946 }; 3947 3948 struct mlx5_ifc_query_vport_state_in_bits { 3949 u8 opcode[0x10]; 3950 u8 reserved_0[0x10]; 3951 3952 u8 reserved_1[0x10]; 3953 u8 op_mod[0x10]; 3954 3955 u8 other_vport[0x1]; 3956 u8 reserved_2[0xf]; 3957 u8 vport_number[0x10]; 3958 3959 u8 reserved_3[0x20]; 3960 }; 3961 3962 struct mlx5_ifc_query_vnic_env_out_bits { 3963 u8 status[0x8]; 3964 u8 reserved_at_8[0x18]; 3965 3966 u8 syndrome[0x20]; 3967 3968 u8 reserved_at_40[0x40]; 3969 3970 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 3971 }; 3972 3973 enum { 3974 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 3975 }; 3976 3977 struct mlx5_ifc_query_vnic_env_in_bits { 3978 u8 opcode[0x10]; 3979 u8 reserved_at_10[0x10]; 3980 3981 u8 reserved_at_20[0x10]; 3982 u8 op_mod[0x10]; 3983 3984 u8 other_vport[0x1]; 3985 u8 reserved_at_41[0xf]; 3986 u8 vport_number[0x10]; 3987 3988 u8 reserved_at_60[0x20]; 3989 }; 3990 3991 struct mlx5_ifc_query_vport_counter_out_bits { 3992 u8 status[0x8]; 3993 u8 reserved_0[0x18]; 3994 3995 u8 syndrome[0x20]; 3996 3997 u8 reserved_1[0x40]; 3998 3999 struct mlx5_ifc_traffic_counter_bits received_errors; 4000 4001 struct mlx5_ifc_traffic_counter_bits transmit_errors; 4002 4003 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 4004 4005 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 4006 4007 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 4008 4009 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 4010 4011 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 4012 4013 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 4014 4015 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 4016 4017 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 4018 4019 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 4020 4021 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 4022 4023 u8 reserved_2[0xa00]; 4024 }; 4025 4026 enum { 4027 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4028 }; 4029 4030 struct mlx5_ifc_query_vport_counter_in_bits { 4031 u8 opcode[0x10]; 4032 u8 reserved_0[0x10]; 4033 4034 u8 reserved_1[0x10]; 4035 u8 op_mod[0x10]; 4036 4037 u8 other_vport[0x1]; 4038 u8 reserved_2[0xb]; 4039 u8 port_num[0x4]; 4040 u8 vport_number[0x10]; 4041 4042 u8 reserved_3[0x60]; 4043 4044 u8 clear[0x1]; 4045 u8 reserved_4[0x1f]; 4046 4047 u8 reserved_5[0x20]; 4048 }; 4049 4050 struct mlx5_ifc_query_tis_out_bits { 4051 u8 status[0x8]; 4052 u8 reserved_0[0x18]; 4053 4054 u8 syndrome[0x20]; 4055 4056 u8 reserved_1[0x40]; 4057 4058 struct mlx5_ifc_tisc_bits tis_context; 4059 }; 4060 4061 struct mlx5_ifc_query_tis_in_bits { 4062 u8 opcode[0x10]; 4063 u8 reserved_0[0x10]; 4064 4065 u8 reserved_1[0x10]; 4066 u8 op_mod[0x10]; 4067 4068 u8 reserved_2[0x8]; 4069 u8 tisn[0x18]; 4070 4071 u8 reserved_3[0x20]; 4072 }; 4073 4074 struct mlx5_ifc_query_tir_out_bits { 4075 u8 status[0x8]; 4076 u8 reserved_0[0x18]; 4077 4078 u8 syndrome[0x20]; 4079 4080 u8 reserved_1[0xc0]; 4081 4082 struct mlx5_ifc_tirc_bits tir_context; 4083 }; 4084 4085 struct mlx5_ifc_query_tir_in_bits { 4086 u8 opcode[0x10]; 4087 u8 reserved_0[0x10]; 4088 4089 u8 reserved_1[0x10]; 4090 u8 op_mod[0x10]; 4091 4092 u8 reserved_2[0x8]; 4093 u8 tirn[0x18]; 4094 4095 u8 reserved_3[0x20]; 4096 }; 4097 4098 struct mlx5_ifc_query_srq_out_bits { 4099 u8 status[0x8]; 4100 u8 reserved_0[0x18]; 4101 4102 u8 syndrome[0x20]; 4103 4104 u8 reserved_1[0x40]; 4105 4106 struct mlx5_ifc_srqc_bits srq_context_entry; 4107 4108 u8 reserved_2[0x600]; 4109 4110 u8 pas[0][0x40]; 4111 }; 4112 4113 struct mlx5_ifc_query_srq_in_bits { 4114 u8 opcode[0x10]; 4115 u8 reserved_0[0x10]; 4116 4117 u8 reserved_1[0x10]; 4118 u8 op_mod[0x10]; 4119 4120 u8 reserved_2[0x8]; 4121 u8 srqn[0x18]; 4122 4123 u8 reserved_3[0x20]; 4124 }; 4125 4126 struct mlx5_ifc_query_sq_out_bits { 4127 u8 status[0x8]; 4128 u8 reserved_0[0x18]; 4129 4130 u8 syndrome[0x20]; 4131 4132 u8 reserved_1[0xc0]; 4133 4134 struct mlx5_ifc_sqc_bits sq_context; 4135 }; 4136 4137 struct mlx5_ifc_query_sq_in_bits { 4138 u8 opcode[0x10]; 4139 u8 reserved_0[0x10]; 4140 4141 u8 reserved_1[0x10]; 4142 u8 op_mod[0x10]; 4143 4144 u8 reserved_2[0x8]; 4145 u8 sqn[0x18]; 4146 4147 u8 reserved_3[0x20]; 4148 }; 4149 4150 struct mlx5_ifc_query_special_contexts_out_bits { 4151 u8 status[0x8]; 4152 u8 reserved_0[0x18]; 4153 4154 u8 syndrome[0x20]; 4155 4156 u8 dump_fill_mkey[0x20]; 4157 4158 u8 resd_lkey[0x20]; 4159 }; 4160 4161 struct mlx5_ifc_query_special_contexts_in_bits { 4162 u8 opcode[0x10]; 4163 u8 reserved_0[0x10]; 4164 4165 u8 reserved_1[0x10]; 4166 u8 op_mod[0x10]; 4167 4168 u8 reserved_2[0x40]; 4169 }; 4170 4171 struct mlx5_ifc_query_scheduling_element_out_bits { 4172 u8 status[0x8]; 4173 u8 reserved_at_8[0x18]; 4174 4175 u8 syndrome[0x20]; 4176 4177 u8 reserved_at_40[0xc0]; 4178 4179 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4180 4181 u8 reserved_at_300[0x100]; 4182 }; 4183 4184 enum { 4185 MLX5_SCHEDULING_ELEMENT_IN_HIERARCHY_E_SWITCH = 0x2, 4186 }; 4187 4188 struct mlx5_ifc_query_scheduling_element_in_bits { 4189 u8 opcode[0x10]; 4190 u8 reserved_at_10[0x10]; 4191 4192 u8 reserved_at_20[0x10]; 4193 u8 op_mod[0x10]; 4194 4195 u8 scheduling_hierarchy[0x8]; 4196 u8 reserved_at_48[0x18]; 4197 4198 u8 scheduling_element_id[0x20]; 4199 4200 u8 reserved_at_80[0x180]; 4201 }; 4202 4203 struct mlx5_ifc_query_rqt_out_bits { 4204 u8 status[0x8]; 4205 u8 reserved_0[0x18]; 4206 4207 u8 syndrome[0x20]; 4208 4209 u8 reserved_1[0xc0]; 4210 4211 struct mlx5_ifc_rqtc_bits rqt_context; 4212 }; 4213 4214 struct mlx5_ifc_query_rqt_in_bits { 4215 u8 opcode[0x10]; 4216 u8 reserved_0[0x10]; 4217 4218 u8 reserved_1[0x10]; 4219 u8 op_mod[0x10]; 4220 4221 u8 reserved_2[0x8]; 4222 u8 rqtn[0x18]; 4223 4224 u8 reserved_3[0x20]; 4225 }; 4226 4227 struct mlx5_ifc_query_rq_out_bits { 4228 u8 status[0x8]; 4229 u8 reserved_0[0x18]; 4230 4231 u8 syndrome[0x20]; 4232 4233 u8 reserved_1[0xc0]; 4234 4235 struct mlx5_ifc_rqc_bits rq_context; 4236 }; 4237 4238 struct mlx5_ifc_query_rq_in_bits { 4239 u8 opcode[0x10]; 4240 u8 reserved_0[0x10]; 4241 4242 u8 reserved_1[0x10]; 4243 u8 op_mod[0x10]; 4244 4245 u8 reserved_2[0x8]; 4246 u8 rqn[0x18]; 4247 4248 u8 reserved_3[0x20]; 4249 }; 4250 4251 struct mlx5_ifc_query_roce_address_out_bits { 4252 u8 status[0x8]; 4253 u8 reserved_0[0x18]; 4254 4255 u8 syndrome[0x20]; 4256 4257 u8 reserved_1[0x40]; 4258 4259 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4260 }; 4261 4262 struct mlx5_ifc_query_roce_address_in_bits { 4263 u8 opcode[0x10]; 4264 u8 reserved_0[0x10]; 4265 4266 u8 reserved_1[0x10]; 4267 u8 op_mod[0x10]; 4268 4269 u8 roce_address_index[0x10]; 4270 u8 reserved_2[0x10]; 4271 4272 u8 reserved_3[0x20]; 4273 }; 4274 4275 struct mlx5_ifc_query_rmp_out_bits { 4276 u8 status[0x8]; 4277 u8 reserved_0[0x18]; 4278 4279 u8 syndrome[0x20]; 4280 4281 u8 reserved_1[0xc0]; 4282 4283 struct mlx5_ifc_rmpc_bits rmp_context; 4284 }; 4285 4286 struct mlx5_ifc_query_rmp_in_bits { 4287 u8 opcode[0x10]; 4288 u8 reserved_0[0x10]; 4289 4290 u8 reserved_1[0x10]; 4291 u8 op_mod[0x10]; 4292 4293 u8 reserved_2[0x8]; 4294 u8 rmpn[0x18]; 4295 4296 u8 reserved_3[0x20]; 4297 }; 4298 4299 struct mlx5_ifc_query_rdb_out_bits { 4300 u8 status[0x8]; 4301 u8 reserved_0[0x18]; 4302 4303 u8 syndrome[0x20]; 4304 4305 u8 reserved_1[0x20]; 4306 4307 u8 reserved_2[0x18]; 4308 u8 rdb_list_size[0x8]; 4309 4310 struct mlx5_ifc_rdbc_bits rdb_context[0]; 4311 }; 4312 4313 struct mlx5_ifc_query_rdb_in_bits { 4314 u8 opcode[0x10]; 4315 u8 reserved_0[0x10]; 4316 4317 u8 reserved_1[0x10]; 4318 u8 op_mod[0x10]; 4319 4320 u8 reserved_2[0x8]; 4321 u8 qpn[0x18]; 4322 4323 u8 reserved_3[0x20]; 4324 }; 4325 4326 struct mlx5_ifc_query_qp_out_bits { 4327 u8 status[0x8]; 4328 u8 reserved_0[0x18]; 4329 4330 u8 syndrome[0x20]; 4331 4332 u8 reserved_1[0x40]; 4333 4334 u8 opt_param_mask[0x20]; 4335 4336 u8 reserved_2[0x20]; 4337 4338 struct mlx5_ifc_qpc_bits qpc; 4339 4340 u8 reserved_3[0x80]; 4341 4342 u8 pas[0][0x40]; 4343 }; 4344 4345 struct mlx5_ifc_query_qp_in_bits { 4346 u8 opcode[0x10]; 4347 u8 reserved_0[0x10]; 4348 4349 u8 reserved_1[0x10]; 4350 u8 op_mod[0x10]; 4351 4352 u8 reserved_2[0x8]; 4353 u8 qpn[0x18]; 4354 4355 u8 reserved_3[0x20]; 4356 }; 4357 4358 struct mlx5_ifc_query_q_counter_out_bits { 4359 u8 status[0x8]; 4360 u8 reserved_0[0x18]; 4361 4362 u8 syndrome[0x20]; 4363 4364 u8 reserved_1[0x40]; 4365 4366 u8 rx_write_requests[0x20]; 4367 4368 u8 reserved_2[0x20]; 4369 4370 u8 rx_read_requests[0x20]; 4371 4372 u8 reserved_3[0x20]; 4373 4374 u8 rx_atomic_requests[0x20]; 4375 4376 u8 reserved_4[0x20]; 4377 4378 u8 rx_dct_connect[0x20]; 4379 4380 u8 reserved_5[0x20]; 4381 4382 u8 out_of_buffer[0x20]; 4383 4384 u8 reserved_7[0x20]; 4385 4386 u8 out_of_sequence[0x20]; 4387 4388 u8 reserved_8[0x20]; 4389 4390 u8 duplicate_request[0x20]; 4391 4392 u8 reserved_9[0x20]; 4393 4394 u8 rnr_nak_retry_err[0x20]; 4395 4396 u8 reserved_10[0x20]; 4397 4398 u8 packet_seq_err[0x20]; 4399 4400 u8 reserved_11[0x20]; 4401 4402 u8 implied_nak_seq_err[0x20]; 4403 4404 u8 reserved_12[0x20]; 4405 4406 u8 local_ack_timeout_err[0x20]; 4407 4408 u8 reserved_13[0x20]; 4409 4410 u8 resp_rnr_nak[0x20]; 4411 4412 u8 reserved_14[0x20]; 4413 4414 u8 req_rnr_retries_exceeded[0x20]; 4415 4416 u8 reserved_15[0x460]; 4417 }; 4418 4419 struct mlx5_ifc_query_q_counter_in_bits { 4420 u8 opcode[0x10]; 4421 u8 reserved_0[0x10]; 4422 4423 u8 reserved_1[0x10]; 4424 u8 op_mod[0x10]; 4425 4426 u8 reserved_2[0x80]; 4427 4428 u8 clear[0x1]; 4429 u8 reserved_3[0x1f]; 4430 4431 u8 reserved_4[0x18]; 4432 u8 counter_set_id[0x8]; 4433 }; 4434 4435 struct mlx5_ifc_query_pages_out_bits { 4436 u8 status[0x8]; 4437 u8 reserved_0[0x18]; 4438 4439 u8 syndrome[0x20]; 4440 4441 u8 reserved_1[0x10]; 4442 u8 function_id[0x10]; 4443 4444 u8 num_pages[0x20]; 4445 }; 4446 4447 enum { 4448 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 4449 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 4450 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 4451 }; 4452 4453 struct mlx5_ifc_query_pages_in_bits { 4454 u8 opcode[0x10]; 4455 u8 reserved_0[0x10]; 4456 4457 u8 reserved_1[0x10]; 4458 u8 op_mod[0x10]; 4459 4460 u8 reserved_2[0x10]; 4461 u8 function_id[0x10]; 4462 4463 u8 reserved_3[0x20]; 4464 }; 4465 4466 struct mlx5_ifc_query_nic_vport_context_out_bits { 4467 u8 status[0x8]; 4468 u8 reserved_0[0x18]; 4469 4470 u8 syndrome[0x20]; 4471 4472 u8 reserved_1[0x40]; 4473 4474 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 4475 }; 4476 4477 struct mlx5_ifc_query_nic_vport_context_in_bits { 4478 u8 opcode[0x10]; 4479 u8 reserved_0[0x10]; 4480 4481 u8 reserved_1[0x10]; 4482 u8 op_mod[0x10]; 4483 4484 u8 other_vport[0x1]; 4485 u8 reserved_2[0xf]; 4486 u8 vport_number[0x10]; 4487 4488 u8 reserved_3[0x5]; 4489 u8 allowed_list_type[0x3]; 4490 u8 reserved_4[0x18]; 4491 }; 4492 4493 struct mlx5_ifc_query_mkey_out_bits { 4494 u8 status[0x8]; 4495 u8 reserved_0[0x18]; 4496 4497 u8 syndrome[0x20]; 4498 4499 u8 reserved_1[0x40]; 4500 4501 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 4502 4503 u8 reserved_2[0x600]; 4504 4505 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 4506 4507 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 4508 }; 4509 4510 struct mlx5_ifc_query_mkey_in_bits { 4511 u8 opcode[0x10]; 4512 u8 reserved_0[0x10]; 4513 4514 u8 reserved_1[0x10]; 4515 u8 op_mod[0x10]; 4516 4517 u8 reserved_2[0x8]; 4518 u8 mkey_index[0x18]; 4519 4520 u8 pg_access[0x1]; 4521 u8 reserved_3[0x1f]; 4522 }; 4523 4524 struct mlx5_ifc_query_mad_demux_out_bits { 4525 u8 status[0x8]; 4526 u8 reserved_0[0x18]; 4527 4528 u8 syndrome[0x20]; 4529 4530 u8 reserved_1[0x40]; 4531 4532 u8 mad_dumux_parameters_block[0x20]; 4533 }; 4534 4535 struct mlx5_ifc_query_mad_demux_in_bits { 4536 u8 opcode[0x10]; 4537 u8 reserved_0[0x10]; 4538 4539 u8 reserved_1[0x10]; 4540 u8 op_mod[0x10]; 4541 4542 u8 reserved_2[0x40]; 4543 }; 4544 4545 struct mlx5_ifc_query_l2_table_entry_out_bits { 4546 u8 status[0x8]; 4547 u8 reserved_0[0x18]; 4548 4549 u8 syndrome[0x20]; 4550 4551 u8 reserved_1[0xa0]; 4552 4553 u8 reserved_2[0x13]; 4554 u8 vlan_valid[0x1]; 4555 u8 vlan[0xc]; 4556 4557 struct mlx5_ifc_mac_address_layout_bits mac_address; 4558 4559 u8 reserved_3[0xc0]; 4560 }; 4561 4562 struct mlx5_ifc_query_l2_table_entry_in_bits { 4563 u8 opcode[0x10]; 4564 u8 reserved_0[0x10]; 4565 4566 u8 reserved_1[0x10]; 4567 u8 op_mod[0x10]; 4568 4569 u8 reserved_2[0x60]; 4570 4571 u8 reserved_3[0x8]; 4572 u8 table_index[0x18]; 4573 4574 u8 reserved_4[0x140]; 4575 }; 4576 4577 struct mlx5_ifc_query_issi_out_bits { 4578 u8 status[0x8]; 4579 u8 reserved_0[0x18]; 4580 4581 u8 syndrome[0x20]; 4582 4583 u8 reserved_1[0x10]; 4584 u8 current_issi[0x10]; 4585 4586 u8 reserved_2[0xa0]; 4587 4588 u8 supported_issi_reserved[76][0x8]; 4589 u8 supported_issi_dw0[0x20]; 4590 }; 4591 4592 struct mlx5_ifc_query_issi_in_bits { 4593 u8 opcode[0x10]; 4594 u8 reserved_0[0x10]; 4595 4596 u8 reserved_1[0x10]; 4597 u8 op_mod[0x10]; 4598 4599 u8 reserved_2[0x40]; 4600 }; 4601 4602 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 4603 u8 status[0x8]; 4604 u8 reserved_0[0x18]; 4605 4606 u8 syndrome[0x20]; 4607 4608 u8 reserved_1[0x40]; 4609 4610 struct mlx5_ifc_pkey_bits pkey[0]; 4611 }; 4612 4613 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 4614 u8 opcode[0x10]; 4615 u8 reserved_0[0x10]; 4616 4617 u8 reserved_1[0x10]; 4618 u8 op_mod[0x10]; 4619 4620 u8 other_vport[0x1]; 4621 u8 reserved_2[0xb]; 4622 u8 port_num[0x4]; 4623 u8 vport_number[0x10]; 4624 4625 u8 reserved_3[0x10]; 4626 u8 pkey_index[0x10]; 4627 }; 4628 4629 struct mlx5_ifc_query_hca_vport_gid_out_bits { 4630 u8 status[0x8]; 4631 u8 reserved_0[0x18]; 4632 4633 u8 syndrome[0x20]; 4634 4635 u8 reserved_1[0x20]; 4636 4637 u8 gids_num[0x10]; 4638 u8 reserved_2[0x10]; 4639 4640 struct mlx5_ifc_array128_auto_bits gid[0]; 4641 }; 4642 4643 struct mlx5_ifc_query_hca_vport_gid_in_bits { 4644 u8 opcode[0x10]; 4645 u8 reserved_0[0x10]; 4646 4647 u8 reserved_1[0x10]; 4648 u8 op_mod[0x10]; 4649 4650 u8 other_vport[0x1]; 4651 u8 reserved_2[0xb]; 4652 u8 port_num[0x4]; 4653 u8 vport_number[0x10]; 4654 4655 u8 reserved_3[0x10]; 4656 u8 gid_index[0x10]; 4657 }; 4658 4659 struct mlx5_ifc_query_hca_vport_context_out_bits { 4660 u8 status[0x8]; 4661 u8 reserved_0[0x18]; 4662 4663 u8 syndrome[0x20]; 4664 4665 u8 reserved_1[0x40]; 4666 4667 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 4668 }; 4669 4670 struct mlx5_ifc_query_hca_vport_context_in_bits { 4671 u8 opcode[0x10]; 4672 u8 reserved_0[0x10]; 4673 4674 u8 reserved_1[0x10]; 4675 u8 op_mod[0x10]; 4676 4677 u8 other_vport[0x1]; 4678 u8 reserved_2[0xb]; 4679 u8 port_num[0x4]; 4680 u8 vport_number[0x10]; 4681 4682 u8 reserved_3[0x20]; 4683 }; 4684 4685 struct mlx5_ifc_query_hca_cap_out_bits { 4686 u8 status[0x8]; 4687 u8 reserved_0[0x18]; 4688 4689 u8 syndrome[0x20]; 4690 4691 u8 reserved_1[0x40]; 4692 4693 union mlx5_ifc_hca_cap_union_bits capability; 4694 }; 4695 4696 struct mlx5_ifc_query_hca_cap_in_bits { 4697 u8 opcode[0x10]; 4698 u8 reserved_0[0x10]; 4699 4700 u8 reserved_1[0x10]; 4701 u8 op_mod[0x10]; 4702 4703 u8 reserved_2[0x40]; 4704 }; 4705 4706 struct mlx5_ifc_query_flow_table_out_bits { 4707 u8 status[0x8]; 4708 u8 reserved_at_8[0x18]; 4709 4710 u8 syndrome[0x20]; 4711 4712 u8 reserved_at_40[0x80]; 4713 4714 struct mlx5_ifc_flow_table_context_bits flow_table_context; 4715 }; 4716 4717 struct mlx5_ifc_query_flow_table_in_bits { 4718 u8 opcode[0x10]; 4719 u8 reserved_0[0x10]; 4720 4721 u8 reserved_1[0x10]; 4722 u8 op_mod[0x10]; 4723 4724 u8 other_vport[0x1]; 4725 u8 reserved_2[0xf]; 4726 u8 vport_number[0x10]; 4727 4728 u8 reserved_3[0x20]; 4729 4730 u8 table_type[0x8]; 4731 u8 reserved_4[0x18]; 4732 4733 u8 reserved_5[0x8]; 4734 u8 table_id[0x18]; 4735 4736 u8 reserved_6[0x140]; 4737 }; 4738 4739 struct mlx5_ifc_query_fte_out_bits { 4740 u8 status[0x8]; 4741 u8 reserved_0[0x18]; 4742 4743 u8 syndrome[0x20]; 4744 4745 u8 reserved_1[0x1c0]; 4746 4747 struct mlx5_ifc_flow_context_bits flow_context; 4748 }; 4749 4750 struct mlx5_ifc_query_fte_in_bits { 4751 u8 opcode[0x10]; 4752 u8 reserved_0[0x10]; 4753 4754 u8 reserved_1[0x10]; 4755 u8 op_mod[0x10]; 4756 4757 u8 other_vport[0x1]; 4758 u8 reserved_2[0xf]; 4759 u8 vport_number[0x10]; 4760 4761 u8 reserved_3[0x20]; 4762 4763 u8 table_type[0x8]; 4764 u8 reserved_4[0x18]; 4765 4766 u8 reserved_5[0x8]; 4767 u8 table_id[0x18]; 4768 4769 u8 reserved_6[0x40]; 4770 4771 u8 flow_index[0x20]; 4772 4773 u8 reserved_7[0xe0]; 4774 }; 4775 4776 enum { 4777 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 4778 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 4779 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 4780 }; 4781 4782 struct mlx5_ifc_query_flow_group_out_bits { 4783 u8 status[0x8]; 4784 u8 reserved_0[0x18]; 4785 4786 u8 syndrome[0x20]; 4787 4788 u8 reserved_1[0xa0]; 4789 4790 u8 start_flow_index[0x20]; 4791 4792 u8 reserved_2[0x20]; 4793 4794 u8 end_flow_index[0x20]; 4795 4796 u8 reserved_3[0xa0]; 4797 4798 u8 reserved_4[0x18]; 4799 u8 match_criteria_enable[0x8]; 4800 4801 struct mlx5_ifc_fte_match_param_bits match_criteria; 4802 4803 u8 reserved_5[0xe00]; 4804 }; 4805 4806 struct mlx5_ifc_query_flow_group_in_bits { 4807 u8 opcode[0x10]; 4808 u8 reserved_0[0x10]; 4809 4810 u8 reserved_1[0x10]; 4811 u8 op_mod[0x10]; 4812 4813 u8 other_vport[0x1]; 4814 u8 reserved_2[0xf]; 4815 u8 vport_number[0x10]; 4816 4817 u8 reserved_3[0x20]; 4818 4819 u8 table_type[0x8]; 4820 u8 reserved_4[0x18]; 4821 4822 u8 reserved_5[0x8]; 4823 u8 table_id[0x18]; 4824 4825 u8 group_id[0x20]; 4826 4827 u8 reserved_6[0x120]; 4828 }; 4829 4830 struct mlx5_ifc_query_flow_counter_out_bits { 4831 u8 status[0x8]; 4832 u8 reserved_at_8[0x18]; 4833 4834 u8 syndrome[0x20]; 4835 4836 u8 reserved_at_40[0x40]; 4837 4838 struct mlx5_ifc_traffic_counter_bits flow_statistics[0]; 4839 }; 4840 4841 struct mlx5_ifc_query_flow_counter_in_bits { 4842 u8 opcode[0x10]; 4843 u8 reserved_at_10[0x10]; 4844 4845 u8 reserved_at_20[0x10]; 4846 u8 op_mod[0x10]; 4847 4848 u8 reserved_at_40[0x80]; 4849 4850 u8 clear[0x1]; 4851 u8 reserved_at_c1[0xf]; 4852 u8 num_of_counters[0x10]; 4853 4854 u8 reserved_at_e0[0x10]; 4855 u8 flow_counter_id[0x10]; 4856 }; 4857 4858 struct mlx5_ifc_query_esw_vport_context_out_bits { 4859 u8 status[0x8]; 4860 u8 reserved_0[0x18]; 4861 4862 u8 syndrome[0x20]; 4863 4864 u8 reserved_1[0x40]; 4865 4866 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4867 }; 4868 4869 struct mlx5_ifc_query_esw_vport_context_in_bits { 4870 u8 opcode[0x10]; 4871 u8 reserved_0[0x10]; 4872 4873 u8 reserved_1[0x10]; 4874 u8 op_mod[0x10]; 4875 4876 u8 other_vport[0x1]; 4877 u8 reserved_2[0xf]; 4878 u8 vport_number[0x10]; 4879 4880 u8 reserved_3[0x20]; 4881 }; 4882 4883 struct mlx5_ifc_query_eq_out_bits { 4884 u8 status[0x8]; 4885 u8 reserved_0[0x18]; 4886 4887 u8 syndrome[0x20]; 4888 4889 u8 reserved_1[0x40]; 4890 4891 struct mlx5_ifc_eqc_bits eq_context_entry; 4892 4893 u8 reserved_2[0x40]; 4894 4895 u8 event_bitmask[0x40]; 4896 4897 u8 reserved_3[0x580]; 4898 4899 u8 pas[0][0x40]; 4900 }; 4901 4902 struct mlx5_ifc_query_eq_in_bits { 4903 u8 opcode[0x10]; 4904 u8 reserved_0[0x10]; 4905 4906 u8 reserved_1[0x10]; 4907 u8 op_mod[0x10]; 4908 4909 u8 reserved_2[0x18]; 4910 u8 eq_number[0x8]; 4911 4912 u8 reserved_3[0x20]; 4913 }; 4914 4915 struct mlx5_ifc_query_dct_out_bits { 4916 u8 status[0x8]; 4917 u8 reserved_0[0x18]; 4918 4919 u8 syndrome[0x20]; 4920 4921 u8 reserved_1[0x40]; 4922 4923 struct mlx5_ifc_dctc_bits dct_context_entry; 4924 4925 u8 reserved_2[0x180]; 4926 }; 4927 4928 struct mlx5_ifc_query_dct_in_bits { 4929 u8 opcode[0x10]; 4930 u8 reserved_0[0x10]; 4931 4932 u8 reserved_1[0x10]; 4933 u8 op_mod[0x10]; 4934 4935 u8 reserved_2[0x8]; 4936 u8 dctn[0x18]; 4937 4938 u8 reserved_3[0x20]; 4939 }; 4940 4941 struct mlx5_ifc_query_dc_cnak_trace_out_bits { 4942 u8 status[0x8]; 4943 u8 reserved_0[0x18]; 4944 4945 u8 syndrome[0x20]; 4946 4947 u8 enable[0x1]; 4948 u8 reserved_1[0x1f]; 4949 4950 u8 reserved_2[0x160]; 4951 4952 struct mlx5_ifc_cmd_pas_bits pas; 4953 }; 4954 4955 struct mlx5_ifc_query_dc_cnak_trace_in_bits { 4956 u8 opcode[0x10]; 4957 u8 reserved_0[0x10]; 4958 4959 u8 reserved_1[0x10]; 4960 u8 op_mod[0x10]; 4961 4962 u8 reserved_2[0x40]; 4963 }; 4964 4965 struct mlx5_ifc_query_cq_out_bits { 4966 u8 status[0x8]; 4967 u8 reserved_0[0x18]; 4968 4969 u8 syndrome[0x20]; 4970 4971 u8 reserved_1[0x40]; 4972 4973 struct mlx5_ifc_cqc_bits cq_context; 4974 4975 u8 reserved_2[0x600]; 4976 4977 u8 pas[0][0x40]; 4978 }; 4979 4980 struct mlx5_ifc_query_cq_in_bits { 4981 u8 opcode[0x10]; 4982 u8 reserved_0[0x10]; 4983 4984 u8 reserved_1[0x10]; 4985 u8 op_mod[0x10]; 4986 4987 u8 reserved_2[0x8]; 4988 u8 cqn[0x18]; 4989 4990 u8 reserved_3[0x20]; 4991 }; 4992 4993 struct mlx5_ifc_query_cong_status_out_bits { 4994 u8 status[0x8]; 4995 u8 reserved_0[0x18]; 4996 4997 u8 syndrome[0x20]; 4998 4999 u8 reserved_1[0x20]; 5000 5001 u8 enable[0x1]; 5002 u8 tag_enable[0x1]; 5003 u8 reserved_2[0x1e]; 5004 }; 5005 5006 struct mlx5_ifc_query_cong_status_in_bits { 5007 u8 opcode[0x10]; 5008 u8 reserved_0[0x10]; 5009 5010 u8 reserved_1[0x10]; 5011 u8 op_mod[0x10]; 5012 5013 u8 reserved_2[0x18]; 5014 u8 priority[0x4]; 5015 u8 cong_protocol[0x4]; 5016 5017 u8 reserved_3[0x20]; 5018 }; 5019 5020 struct mlx5_ifc_query_cong_statistics_out_bits { 5021 u8 status[0x8]; 5022 u8 reserved_0[0x18]; 5023 5024 u8 syndrome[0x20]; 5025 5026 u8 reserved_1[0x40]; 5027 5028 u8 rp_cur_flows[0x20]; 5029 5030 u8 sum_flows[0x20]; 5031 5032 u8 rp_cnp_ignored_high[0x20]; 5033 5034 u8 rp_cnp_ignored_low[0x20]; 5035 5036 u8 rp_cnp_handled_high[0x20]; 5037 5038 u8 rp_cnp_handled_low[0x20]; 5039 5040 u8 reserved_2[0x100]; 5041 5042 u8 time_stamp_high[0x20]; 5043 5044 u8 time_stamp_low[0x20]; 5045 5046 u8 accumulators_period[0x20]; 5047 5048 u8 np_ecn_marked_roce_packets_high[0x20]; 5049 5050 u8 np_ecn_marked_roce_packets_low[0x20]; 5051 5052 u8 np_cnp_sent_high[0x20]; 5053 5054 u8 np_cnp_sent_low[0x20]; 5055 5056 u8 reserved_3[0x560]; 5057 }; 5058 5059 struct mlx5_ifc_query_cong_statistics_in_bits { 5060 u8 opcode[0x10]; 5061 u8 reserved_0[0x10]; 5062 5063 u8 reserved_1[0x10]; 5064 u8 op_mod[0x10]; 5065 5066 u8 clear[0x1]; 5067 u8 reserved_2[0x1f]; 5068 5069 u8 reserved_3[0x20]; 5070 }; 5071 5072 struct mlx5_ifc_query_cong_params_out_bits { 5073 u8 status[0x8]; 5074 u8 reserved_0[0x18]; 5075 5076 u8 syndrome[0x20]; 5077 5078 u8 reserved_1[0x40]; 5079 5080 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5081 }; 5082 5083 struct mlx5_ifc_query_cong_params_in_bits { 5084 u8 opcode[0x10]; 5085 u8 reserved_0[0x10]; 5086 5087 u8 reserved_1[0x10]; 5088 u8 op_mod[0x10]; 5089 5090 u8 reserved_2[0x1c]; 5091 u8 cong_protocol[0x4]; 5092 5093 u8 reserved_3[0x20]; 5094 }; 5095 5096 struct mlx5_ifc_query_burst_size_out_bits { 5097 u8 status[0x8]; 5098 u8 reserved_0[0x18]; 5099 5100 u8 syndrome[0x20]; 5101 5102 u8 reserved_1[0x20]; 5103 5104 u8 reserved_2[0x9]; 5105 u8 device_burst_size[0x17]; 5106 }; 5107 5108 struct mlx5_ifc_query_burst_size_in_bits { 5109 u8 opcode[0x10]; 5110 u8 reserved_0[0x10]; 5111 5112 u8 reserved_1[0x10]; 5113 u8 op_mod[0x10]; 5114 5115 u8 reserved_2[0x40]; 5116 }; 5117 5118 struct mlx5_ifc_query_adapter_out_bits { 5119 u8 status[0x8]; 5120 u8 reserved_0[0x18]; 5121 5122 u8 syndrome[0x20]; 5123 5124 u8 reserved_1[0x40]; 5125 5126 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 5127 }; 5128 5129 struct mlx5_ifc_query_adapter_in_bits { 5130 u8 opcode[0x10]; 5131 u8 reserved_0[0x10]; 5132 5133 u8 reserved_1[0x10]; 5134 u8 op_mod[0x10]; 5135 5136 u8 reserved_2[0x40]; 5137 }; 5138 5139 struct mlx5_ifc_qp_2rst_out_bits { 5140 u8 status[0x8]; 5141 u8 reserved_0[0x18]; 5142 5143 u8 syndrome[0x20]; 5144 5145 u8 reserved_1[0x40]; 5146 }; 5147 5148 struct mlx5_ifc_qp_2rst_in_bits { 5149 u8 opcode[0x10]; 5150 u8 reserved_0[0x10]; 5151 5152 u8 reserved_1[0x10]; 5153 u8 op_mod[0x10]; 5154 5155 u8 reserved_2[0x8]; 5156 u8 qpn[0x18]; 5157 5158 u8 reserved_3[0x20]; 5159 }; 5160 5161 struct mlx5_ifc_qp_2err_out_bits { 5162 u8 status[0x8]; 5163 u8 reserved_0[0x18]; 5164 5165 u8 syndrome[0x20]; 5166 5167 u8 reserved_1[0x40]; 5168 }; 5169 5170 struct mlx5_ifc_qp_2err_in_bits { 5171 u8 opcode[0x10]; 5172 u8 reserved_0[0x10]; 5173 5174 u8 reserved_1[0x10]; 5175 u8 op_mod[0x10]; 5176 5177 u8 reserved_2[0x8]; 5178 u8 qpn[0x18]; 5179 5180 u8 reserved_3[0x20]; 5181 }; 5182 5183 struct mlx5_ifc_para_vport_element_bits { 5184 u8 reserved_at_0[0xc]; 5185 u8 traffic_class[0x4]; 5186 u8 qos_para_vport_number[0x10]; 5187 }; 5188 5189 struct mlx5_ifc_page_fault_resume_out_bits { 5190 u8 status[0x8]; 5191 u8 reserved_0[0x18]; 5192 5193 u8 syndrome[0x20]; 5194 5195 u8 reserved_1[0x40]; 5196 }; 5197 5198 struct mlx5_ifc_page_fault_resume_in_bits { 5199 u8 opcode[0x10]; 5200 u8 reserved_0[0x10]; 5201 5202 u8 reserved_1[0x10]; 5203 u8 op_mod[0x10]; 5204 5205 u8 error[0x1]; 5206 u8 reserved_2[0x4]; 5207 u8 rdma[0x1]; 5208 u8 read_write[0x1]; 5209 u8 req_res[0x1]; 5210 u8 qpn[0x18]; 5211 5212 u8 reserved_3[0x20]; 5213 }; 5214 5215 struct mlx5_ifc_nop_out_bits { 5216 u8 status[0x8]; 5217 u8 reserved_0[0x18]; 5218 5219 u8 syndrome[0x20]; 5220 5221 u8 reserved_1[0x40]; 5222 }; 5223 5224 struct mlx5_ifc_nop_in_bits { 5225 u8 opcode[0x10]; 5226 u8 reserved_0[0x10]; 5227 5228 u8 reserved_1[0x10]; 5229 u8 op_mod[0x10]; 5230 5231 u8 reserved_2[0x40]; 5232 }; 5233 5234 struct mlx5_ifc_modify_vport_state_out_bits { 5235 u8 status[0x8]; 5236 u8 reserved_0[0x18]; 5237 5238 u8 syndrome[0x20]; 5239 5240 u8 reserved_1[0x40]; 5241 }; 5242 5243 enum { 5244 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_NIC_VPORT = 0x0, 5245 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, 5246 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_UPLINK = 0x2, 5247 }; 5248 5249 enum { 5250 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_DOWN = 0x0, 5251 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_UP = 0x1, 5252 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_FOLLOW = 0x2, 5253 }; 5254 5255 struct mlx5_ifc_modify_vport_state_in_bits { 5256 u8 opcode[0x10]; 5257 u8 reserved_0[0x10]; 5258 5259 u8 reserved_1[0x10]; 5260 u8 op_mod[0x10]; 5261 5262 u8 other_vport[0x1]; 5263 u8 reserved_2[0xf]; 5264 u8 vport_number[0x10]; 5265 5266 u8 reserved_3[0x18]; 5267 u8 admin_state[0x4]; 5268 u8 reserved_4[0x4]; 5269 }; 5270 5271 struct mlx5_ifc_modify_tis_out_bits { 5272 u8 status[0x8]; 5273 u8 reserved_0[0x18]; 5274 5275 u8 syndrome[0x20]; 5276 5277 u8 reserved_1[0x40]; 5278 }; 5279 5280 struct mlx5_ifc_modify_tis_bitmask_bits { 5281 u8 reserved_at_0[0x20]; 5282 5283 u8 reserved_at_20[0x1d]; 5284 u8 lag_tx_port_affinity[0x1]; 5285 u8 strict_lag_tx_port_affinity[0x1]; 5286 u8 prio[0x1]; 5287 }; 5288 5289 struct mlx5_ifc_modify_tis_in_bits { 5290 u8 opcode[0x10]; 5291 u8 reserved_0[0x10]; 5292 5293 u8 reserved_1[0x10]; 5294 u8 op_mod[0x10]; 5295 5296 u8 reserved_2[0x8]; 5297 u8 tisn[0x18]; 5298 5299 u8 reserved_3[0x20]; 5300 5301 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 5302 5303 u8 reserved_4[0x40]; 5304 5305 struct mlx5_ifc_tisc_bits ctx; 5306 }; 5307 5308 struct mlx5_ifc_modify_tir_out_bits { 5309 u8 status[0x8]; 5310 u8 reserved_0[0x18]; 5311 5312 u8 syndrome[0x20]; 5313 5314 u8 reserved_1[0x40]; 5315 }; 5316 5317 enum 5318 { 5319 MLX5_MODIFY_SQ_BITMASK_PACKET_PACING_RATE_LIMIT_INDEX = 0x1 << 0, 5320 MLX5_MODIFY_SQ_BITMASK_QOS_PARA_VPORT_NUMBER = 0x1 << 1 5321 }; 5322 5323 struct mlx5_ifc_modify_tir_in_bits { 5324 u8 opcode[0x10]; 5325 u8 reserved_0[0x10]; 5326 5327 u8 reserved_1[0x10]; 5328 u8 op_mod[0x10]; 5329 5330 u8 reserved_2[0x8]; 5331 u8 tirn[0x18]; 5332 5333 u8 reserved_3[0x20]; 5334 5335 u8 modify_bitmask[0x40]; 5336 5337 u8 reserved_4[0x40]; 5338 5339 struct mlx5_ifc_tirc_bits tir_context; 5340 }; 5341 5342 struct mlx5_ifc_modify_sq_out_bits { 5343 u8 status[0x8]; 5344 u8 reserved_0[0x18]; 5345 5346 u8 syndrome[0x20]; 5347 5348 u8 reserved_1[0x40]; 5349 }; 5350 5351 struct mlx5_ifc_modify_sq_in_bits { 5352 u8 opcode[0x10]; 5353 u8 reserved_0[0x10]; 5354 5355 u8 reserved_1[0x10]; 5356 u8 op_mod[0x10]; 5357 5358 u8 sq_state[0x4]; 5359 u8 reserved_2[0x4]; 5360 u8 sqn[0x18]; 5361 5362 u8 reserved_3[0x20]; 5363 5364 u8 modify_bitmask[0x40]; 5365 5366 u8 reserved_4[0x40]; 5367 5368 struct mlx5_ifc_sqc_bits ctx; 5369 }; 5370 5371 struct mlx5_ifc_modify_scheduling_element_out_bits { 5372 u8 status[0x8]; 5373 u8 reserved_at_8[0x18]; 5374 5375 u8 syndrome[0x20]; 5376 5377 u8 reserved_at_40[0x1c0]; 5378 }; 5379 5380 enum { 5381 MLX5_MODIFY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5382 }; 5383 5384 enum { 5385 MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_BW_SHARE = 0x1, 5386 MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_MAX_AVERAGE_BW = 0x2, 5387 }; 5388 5389 struct mlx5_ifc_modify_scheduling_element_in_bits { 5390 u8 opcode[0x10]; 5391 u8 reserved_at_10[0x10]; 5392 5393 u8 reserved_at_20[0x10]; 5394 u8 op_mod[0x10]; 5395 5396 u8 scheduling_hierarchy[0x8]; 5397 u8 reserved_at_48[0x18]; 5398 5399 u8 scheduling_element_id[0x20]; 5400 5401 u8 reserved_at_80[0x20]; 5402 5403 u8 modify_bitmask[0x20]; 5404 5405 u8 reserved_at_c0[0x40]; 5406 5407 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5408 5409 u8 reserved_at_300[0x100]; 5410 }; 5411 5412 struct mlx5_ifc_modify_rqt_out_bits { 5413 u8 status[0x8]; 5414 u8 reserved_0[0x18]; 5415 5416 u8 syndrome[0x20]; 5417 5418 u8 reserved_1[0x40]; 5419 }; 5420 5421 struct mlx5_ifc_modify_rqt_in_bits { 5422 u8 opcode[0x10]; 5423 u8 reserved_0[0x10]; 5424 5425 u8 reserved_1[0x10]; 5426 u8 op_mod[0x10]; 5427 5428 u8 reserved_2[0x8]; 5429 u8 rqtn[0x18]; 5430 5431 u8 reserved_3[0x20]; 5432 5433 u8 modify_bitmask[0x40]; 5434 5435 u8 reserved_4[0x40]; 5436 5437 struct mlx5_ifc_rqtc_bits ctx; 5438 }; 5439 5440 struct mlx5_ifc_modify_rq_out_bits { 5441 u8 status[0x8]; 5442 u8 reserved_0[0x18]; 5443 5444 u8 syndrome[0x20]; 5445 5446 u8 reserved_1[0x40]; 5447 }; 5448 5449 enum { 5450 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 5451 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3, 5452 }; 5453 5454 struct mlx5_ifc_modify_rq_in_bits { 5455 u8 opcode[0x10]; 5456 u8 reserved_0[0x10]; 5457 5458 u8 reserved_1[0x10]; 5459 u8 op_mod[0x10]; 5460 5461 u8 rq_state[0x4]; 5462 u8 reserved_2[0x4]; 5463 u8 rqn[0x18]; 5464 5465 u8 reserved_3[0x20]; 5466 5467 u8 modify_bitmask[0x40]; 5468 5469 u8 reserved_4[0x40]; 5470 5471 struct mlx5_ifc_rqc_bits ctx; 5472 }; 5473 5474 struct mlx5_ifc_modify_rmp_out_bits { 5475 u8 status[0x8]; 5476 u8 reserved_0[0x18]; 5477 5478 u8 syndrome[0x20]; 5479 5480 u8 reserved_1[0x40]; 5481 }; 5482 5483 struct mlx5_ifc_rmp_bitmask_bits { 5484 u8 reserved[0x20]; 5485 5486 u8 reserved1[0x1f]; 5487 u8 lwm[0x1]; 5488 }; 5489 5490 struct mlx5_ifc_modify_rmp_in_bits { 5491 u8 opcode[0x10]; 5492 u8 reserved_0[0x10]; 5493 5494 u8 reserved_1[0x10]; 5495 u8 op_mod[0x10]; 5496 5497 u8 rmp_state[0x4]; 5498 u8 reserved_2[0x4]; 5499 u8 rmpn[0x18]; 5500 5501 u8 reserved_3[0x20]; 5502 5503 struct mlx5_ifc_rmp_bitmask_bits bitmask; 5504 5505 u8 reserved_4[0x40]; 5506 5507 struct mlx5_ifc_rmpc_bits ctx; 5508 }; 5509 5510 struct mlx5_ifc_modify_nic_vport_context_out_bits { 5511 u8 status[0x8]; 5512 u8 reserved_0[0x18]; 5513 5514 u8 syndrome[0x20]; 5515 5516 u8 reserved_1[0x40]; 5517 }; 5518 5519 struct mlx5_ifc_modify_nic_vport_field_select_bits { 5520 u8 reserved_0[0x14]; 5521 u8 disable_uc_local_lb[0x1]; 5522 u8 disable_mc_local_lb[0x1]; 5523 u8 node_guid[0x1]; 5524 u8 port_guid[0x1]; 5525 u8 min_wqe_inline_mode[0x1]; 5526 u8 mtu[0x1]; 5527 u8 change_event[0x1]; 5528 u8 promisc[0x1]; 5529 u8 permanent_address[0x1]; 5530 u8 addresses_list[0x1]; 5531 u8 roce_en[0x1]; 5532 u8 reserved_1[0x1]; 5533 }; 5534 5535 struct mlx5_ifc_modify_nic_vport_context_in_bits { 5536 u8 opcode[0x10]; 5537 u8 reserved_0[0x10]; 5538 5539 u8 reserved_1[0x10]; 5540 u8 op_mod[0x10]; 5541 5542 u8 other_vport[0x1]; 5543 u8 reserved_2[0xf]; 5544 u8 vport_number[0x10]; 5545 5546 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 5547 5548 u8 reserved_3[0x780]; 5549 5550 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5551 }; 5552 5553 struct mlx5_ifc_modify_hca_vport_context_out_bits { 5554 u8 status[0x8]; 5555 u8 reserved_0[0x18]; 5556 5557 u8 syndrome[0x20]; 5558 5559 u8 reserved_1[0x40]; 5560 }; 5561 5562 struct mlx5_ifc_grh_bits { 5563 u8 ip_version[4]; 5564 u8 traffic_class[8]; 5565 u8 flow_label[20]; 5566 u8 payload_length[16]; 5567 u8 next_header[8]; 5568 u8 hop_limit[8]; 5569 u8 sgid[128]; 5570 u8 dgid[128]; 5571 }; 5572 5573 struct mlx5_ifc_bth_bits { 5574 u8 opcode[8]; 5575 u8 se[1]; 5576 u8 migreq[1]; 5577 u8 pad_count[2]; 5578 u8 tver[4]; 5579 u8 p_key[16]; 5580 u8 reserved8[8]; 5581 u8 dest_qp[24]; 5582 u8 ack_req[1]; 5583 u8 reserved7[7]; 5584 u8 psn[24]; 5585 }; 5586 5587 struct mlx5_ifc_aeth_bits { 5588 u8 syndrome[8]; 5589 u8 msn[24]; 5590 }; 5591 5592 struct mlx5_ifc_dceth_bits { 5593 u8 reserved0[8]; 5594 u8 session_id[24]; 5595 u8 reserved1[8]; 5596 u8 dci_dct[24]; 5597 }; 5598 5599 struct mlx5_ifc_modify_hca_vport_context_in_bits { 5600 u8 opcode[0x10]; 5601 u8 reserved_0[0x10]; 5602 5603 u8 reserved_1[0x10]; 5604 u8 op_mod[0x10]; 5605 5606 u8 other_vport[0x1]; 5607 u8 reserved_2[0xb]; 5608 u8 port_num[0x4]; 5609 u8 vport_number[0x10]; 5610 5611 u8 reserved_3[0x20]; 5612 5613 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5614 }; 5615 5616 struct mlx5_ifc_modify_flow_table_out_bits { 5617 u8 status[0x8]; 5618 u8 reserved_at_8[0x18]; 5619 5620 u8 syndrome[0x20]; 5621 5622 u8 reserved_at_40[0x40]; 5623 }; 5624 5625 enum { 5626 MLX5_MODIFY_FLOW_TABLE_SELECT_MISS_ACTION_AND_ID = 0x1, 5627 MLX5_MODIFY_FLOW_TABLE_SELECT_LAG_MASTER_NEXT_TABLE_ID = 0x8000, 5628 }; 5629 5630 struct mlx5_ifc_modify_flow_table_in_bits { 5631 u8 opcode[0x10]; 5632 u8 reserved_at_10[0x10]; 5633 5634 u8 reserved_at_20[0x10]; 5635 u8 op_mod[0x10]; 5636 5637 u8 other_vport[0x1]; 5638 u8 reserved_at_41[0xf]; 5639 u8 vport_number[0x10]; 5640 5641 u8 reserved_at_60[0x10]; 5642 u8 modify_field_select[0x10]; 5643 5644 u8 table_type[0x8]; 5645 u8 reserved_at_88[0x18]; 5646 5647 u8 reserved_at_a0[0x8]; 5648 u8 table_id[0x18]; 5649 5650 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5651 }; 5652 5653 struct mlx5_ifc_modify_esw_vport_context_out_bits { 5654 u8 status[0x8]; 5655 u8 reserved_0[0x18]; 5656 5657 u8 syndrome[0x20]; 5658 5659 u8 reserved_1[0x40]; 5660 }; 5661 5662 struct mlx5_ifc_esw_vport_context_fields_select_bits { 5663 u8 reserved[0x1c]; 5664 u8 vport_cvlan_insert[0x1]; 5665 u8 vport_svlan_insert[0x1]; 5666 u8 vport_cvlan_strip[0x1]; 5667 u8 vport_svlan_strip[0x1]; 5668 }; 5669 5670 struct mlx5_ifc_modify_esw_vport_context_in_bits { 5671 u8 opcode[0x10]; 5672 u8 reserved_0[0x10]; 5673 5674 u8 reserved_1[0x10]; 5675 u8 op_mod[0x10]; 5676 5677 u8 other_vport[0x1]; 5678 u8 reserved_2[0xf]; 5679 u8 vport_number[0x10]; 5680 5681 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 5682 5683 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5684 }; 5685 5686 struct mlx5_ifc_modify_cq_out_bits { 5687 u8 status[0x8]; 5688 u8 reserved_0[0x18]; 5689 5690 u8 syndrome[0x20]; 5691 5692 u8 reserved_1[0x40]; 5693 }; 5694 5695 enum { 5696 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 5697 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 5698 }; 5699 5700 struct mlx5_ifc_modify_cq_in_bits { 5701 u8 opcode[0x10]; 5702 u8 reserved_0[0x10]; 5703 5704 u8 reserved_1[0x10]; 5705 u8 op_mod[0x10]; 5706 5707 u8 reserved_2[0x8]; 5708 u8 cqn[0x18]; 5709 5710 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 5711 5712 struct mlx5_ifc_cqc_bits cq_context; 5713 5714 u8 reserved_3[0x600]; 5715 5716 u8 pas[0][0x40]; 5717 }; 5718 5719 struct mlx5_ifc_modify_cong_status_out_bits { 5720 u8 status[0x8]; 5721 u8 reserved_0[0x18]; 5722 5723 u8 syndrome[0x20]; 5724 5725 u8 reserved_1[0x40]; 5726 }; 5727 5728 struct mlx5_ifc_modify_cong_status_in_bits { 5729 u8 opcode[0x10]; 5730 u8 reserved_0[0x10]; 5731 5732 u8 reserved_1[0x10]; 5733 u8 op_mod[0x10]; 5734 5735 u8 reserved_2[0x18]; 5736 u8 priority[0x4]; 5737 u8 cong_protocol[0x4]; 5738 5739 u8 enable[0x1]; 5740 u8 tag_enable[0x1]; 5741 u8 reserved_3[0x1e]; 5742 }; 5743 5744 struct mlx5_ifc_modify_cong_params_out_bits { 5745 u8 status[0x8]; 5746 u8 reserved_0[0x18]; 5747 5748 u8 syndrome[0x20]; 5749 5750 u8 reserved_1[0x40]; 5751 }; 5752 5753 struct mlx5_ifc_modify_cong_params_in_bits { 5754 u8 opcode[0x10]; 5755 u8 reserved_0[0x10]; 5756 5757 u8 reserved_1[0x10]; 5758 u8 op_mod[0x10]; 5759 5760 u8 reserved_2[0x1c]; 5761 u8 cong_protocol[0x4]; 5762 5763 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 5764 5765 u8 reserved_3[0x80]; 5766 5767 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5768 }; 5769 5770 struct mlx5_ifc_manage_pages_out_bits { 5771 u8 status[0x8]; 5772 u8 reserved_0[0x18]; 5773 5774 u8 syndrome[0x20]; 5775 5776 u8 output_num_entries[0x20]; 5777 5778 u8 reserved_1[0x20]; 5779 5780 u8 pas[0][0x40]; 5781 }; 5782 5783 enum { 5784 MLX5_PAGES_CANT_GIVE = 0x0, 5785 MLX5_PAGES_GIVE = 0x1, 5786 MLX5_PAGES_TAKE = 0x2, 5787 }; 5788 5789 struct mlx5_ifc_manage_pages_in_bits { 5790 u8 opcode[0x10]; 5791 u8 reserved_0[0x10]; 5792 5793 u8 reserved_1[0x10]; 5794 u8 op_mod[0x10]; 5795 5796 u8 reserved_2[0x10]; 5797 u8 function_id[0x10]; 5798 5799 u8 input_num_entries[0x20]; 5800 5801 u8 pas[0][0x40]; 5802 }; 5803 5804 struct mlx5_ifc_mad_ifc_out_bits { 5805 u8 status[0x8]; 5806 u8 reserved_0[0x18]; 5807 5808 u8 syndrome[0x20]; 5809 5810 u8 reserved_1[0x40]; 5811 5812 u8 response_mad_packet[256][0x8]; 5813 }; 5814 5815 struct mlx5_ifc_mad_ifc_in_bits { 5816 u8 opcode[0x10]; 5817 u8 reserved_0[0x10]; 5818 5819 u8 reserved_1[0x10]; 5820 u8 op_mod[0x10]; 5821 5822 u8 remote_lid[0x10]; 5823 u8 reserved_2[0x8]; 5824 u8 port[0x8]; 5825 5826 u8 reserved_3[0x20]; 5827 5828 u8 mad[256][0x8]; 5829 }; 5830 5831 struct mlx5_ifc_init_hca_out_bits { 5832 u8 status[0x8]; 5833 u8 reserved_0[0x18]; 5834 5835 u8 syndrome[0x20]; 5836 5837 u8 reserved_1[0x40]; 5838 }; 5839 5840 enum { 5841 MLX5_INIT_HCA_IN_OP_MOD_INIT = 0x0, 5842 MLX5_INIT_HCA_IN_OP_MOD_PRE_INIT = 0x1, 5843 }; 5844 5845 struct mlx5_ifc_init_hca_in_bits { 5846 u8 opcode[0x10]; 5847 u8 reserved_0[0x10]; 5848 5849 u8 reserved_1[0x10]; 5850 u8 op_mod[0x10]; 5851 5852 u8 reserved_2[0x40]; 5853 }; 5854 5855 struct mlx5_ifc_init2rtr_qp_out_bits { 5856 u8 status[0x8]; 5857 u8 reserved_0[0x18]; 5858 5859 u8 syndrome[0x20]; 5860 5861 u8 reserved_1[0x40]; 5862 }; 5863 5864 struct mlx5_ifc_init2rtr_qp_in_bits { 5865 u8 opcode[0x10]; 5866 u8 reserved_0[0x10]; 5867 5868 u8 reserved_1[0x10]; 5869 u8 op_mod[0x10]; 5870 5871 u8 reserved_2[0x8]; 5872 u8 qpn[0x18]; 5873 5874 u8 reserved_3[0x20]; 5875 5876 u8 opt_param_mask[0x20]; 5877 5878 u8 reserved_4[0x20]; 5879 5880 struct mlx5_ifc_qpc_bits qpc; 5881 5882 u8 reserved_5[0x80]; 5883 }; 5884 5885 struct mlx5_ifc_init2init_qp_out_bits { 5886 u8 status[0x8]; 5887 u8 reserved_0[0x18]; 5888 5889 u8 syndrome[0x20]; 5890 5891 u8 reserved_1[0x40]; 5892 }; 5893 5894 struct mlx5_ifc_init2init_qp_in_bits { 5895 u8 opcode[0x10]; 5896 u8 reserved_0[0x10]; 5897 5898 u8 reserved_1[0x10]; 5899 u8 op_mod[0x10]; 5900 5901 u8 reserved_2[0x8]; 5902 u8 qpn[0x18]; 5903 5904 u8 reserved_3[0x20]; 5905 5906 u8 opt_param_mask[0x20]; 5907 5908 u8 reserved_4[0x20]; 5909 5910 struct mlx5_ifc_qpc_bits qpc; 5911 5912 u8 reserved_5[0x80]; 5913 }; 5914 5915 struct mlx5_ifc_get_dropped_packet_log_out_bits { 5916 u8 status[0x8]; 5917 u8 reserved_0[0x18]; 5918 5919 u8 syndrome[0x20]; 5920 5921 u8 reserved_1[0x40]; 5922 5923 u8 packet_headers_log[128][0x8]; 5924 5925 u8 packet_syndrome[64][0x8]; 5926 }; 5927 5928 struct mlx5_ifc_get_dropped_packet_log_in_bits { 5929 u8 opcode[0x10]; 5930 u8 reserved_0[0x10]; 5931 5932 u8 reserved_1[0x10]; 5933 u8 op_mod[0x10]; 5934 5935 u8 reserved_2[0x40]; 5936 }; 5937 5938 struct mlx5_ifc_gen_eqe_in_bits { 5939 u8 opcode[0x10]; 5940 u8 reserved_0[0x10]; 5941 5942 u8 reserved_1[0x10]; 5943 u8 op_mod[0x10]; 5944 5945 u8 reserved_2[0x18]; 5946 u8 eq_number[0x8]; 5947 5948 u8 reserved_3[0x20]; 5949 5950 u8 eqe[64][0x8]; 5951 }; 5952 5953 struct mlx5_ifc_gen_eq_out_bits { 5954 u8 status[0x8]; 5955 u8 reserved_0[0x18]; 5956 5957 u8 syndrome[0x20]; 5958 5959 u8 reserved_1[0x40]; 5960 }; 5961 5962 struct mlx5_ifc_enable_hca_out_bits { 5963 u8 status[0x8]; 5964 u8 reserved_0[0x18]; 5965 5966 u8 syndrome[0x20]; 5967 5968 u8 reserved_1[0x20]; 5969 }; 5970 5971 struct mlx5_ifc_enable_hca_in_bits { 5972 u8 opcode[0x10]; 5973 u8 reserved_0[0x10]; 5974 5975 u8 reserved_1[0x10]; 5976 u8 op_mod[0x10]; 5977 5978 u8 reserved_2[0x10]; 5979 u8 function_id[0x10]; 5980 5981 u8 reserved_3[0x20]; 5982 }; 5983 5984 struct mlx5_ifc_drain_dct_out_bits { 5985 u8 status[0x8]; 5986 u8 reserved_0[0x18]; 5987 5988 u8 syndrome[0x20]; 5989 5990 u8 reserved_1[0x40]; 5991 }; 5992 5993 struct mlx5_ifc_drain_dct_in_bits { 5994 u8 opcode[0x10]; 5995 u8 reserved_0[0x10]; 5996 5997 u8 reserved_1[0x10]; 5998 u8 op_mod[0x10]; 5999 6000 u8 reserved_2[0x8]; 6001 u8 dctn[0x18]; 6002 6003 u8 reserved_3[0x20]; 6004 }; 6005 6006 struct mlx5_ifc_disable_hca_out_bits { 6007 u8 status[0x8]; 6008 u8 reserved_0[0x18]; 6009 6010 u8 syndrome[0x20]; 6011 6012 u8 reserved_1[0x20]; 6013 }; 6014 6015 struct mlx5_ifc_disable_hca_in_bits { 6016 u8 opcode[0x10]; 6017 u8 reserved_0[0x10]; 6018 6019 u8 reserved_1[0x10]; 6020 u8 op_mod[0x10]; 6021 6022 u8 reserved_2[0x10]; 6023 u8 function_id[0x10]; 6024 6025 u8 reserved_3[0x20]; 6026 }; 6027 6028 struct mlx5_ifc_detach_from_mcg_out_bits { 6029 u8 status[0x8]; 6030 u8 reserved_0[0x18]; 6031 6032 u8 syndrome[0x20]; 6033 6034 u8 reserved_1[0x40]; 6035 }; 6036 6037 struct mlx5_ifc_detach_from_mcg_in_bits { 6038 u8 opcode[0x10]; 6039 u8 reserved_0[0x10]; 6040 6041 u8 reserved_1[0x10]; 6042 u8 op_mod[0x10]; 6043 6044 u8 reserved_2[0x8]; 6045 u8 qpn[0x18]; 6046 6047 u8 reserved_3[0x20]; 6048 6049 u8 multicast_gid[16][0x8]; 6050 }; 6051 6052 struct mlx5_ifc_destroy_xrc_srq_out_bits { 6053 u8 status[0x8]; 6054 u8 reserved_0[0x18]; 6055 6056 u8 syndrome[0x20]; 6057 6058 u8 reserved_1[0x40]; 6059 }; 6060 6061 struct mlx5_ifc_destroy_xrc_srq_in_bits { 6062 u8 opcode[0x10]; 6063 u8 reserved_0[0x10]; 6064 6065 u8 reserved_1[0x10]; 6066 u8 op_mod[0x10]; 6067 6068 u8 reserved_2[0x8]; 6069 u8 xrc_srqn[0x18]; 6070 6071 u8 reserved_3[0x20]; 6072 }; 6073 6074 struct mlx5_ifc_destroy_tis_out_bits { 6075 u8 status[0x8]; 6076 u8 reserved_0[0x18]; 6077 6078 u8 syndrome[0x20]; 6079 6080 u8 reserved_1[0x40]; 6081 }; 6082 6083 struct mlx5_ifc_destroy_tis_in_bits { 6084 u8 opcode[0x10]; 6085 u8 reserved_0[0x10]; 6086 6087 u8 reserved_1[0x10]; 6088 u8 op_mod[0x10]; 6089 6090 u8 reserved_2[0x8]; 6091 u8 tisn[0x18]; 6092 6093 u8 reserved_3[0x20]; 6094 }; 6095 6096 struct mlx5_ifc_destroy_tir_out_bits { 6097 u8 status[0x8]; 6098 u8 reserved_0[0x18]; 6099 6100 u8 syndrome[0x20]; 6101 6102 u8 reserved_1[0x40]; 6103 }; 6104 6105 struct mlx5_ifc_destroy_tir_in_bits { 6106 u8 opcode[0x10]; 6107 u8 reserved_0[0x10]; 6108 6109 u8 reserved_1[0x10]; 6110 u8 op_mod[0x10]; 6111 6112 u8 reserved_2[0x8]; 6113 u8 tirn[0x18]; 6114 6115 u8 reserved_3[0x20]; 6116 }; 6117 6118 struct mlx5_ifc_destroy_srq_out_bits { 6119 u8 status[0x8]; 6120 u8 reserved_0[0x18]; 6121 6122 u8 syndrome[0x20]; 6123 6124 u8 reserved_1[0x40]; 6125 }; 6126 6127 struct mlx5_ifc_destroy_srq_in_bits { 6128 u8 opcode[0x10]; 6129 u8 reserved_0[0x10]; 6130 6131 u8 reserved_1[0x10]; 6132 u8 op_mod[0x10]; 6133 6134 u8 reserved_2[0x8]; 6135 u8 srqn[0x18]; 6136 6137 u8 reserved_3[0x20]; 6138 }; 6139 6140 struct mlx5_ifc_destroy_sq_out_bits { 6141 u8 status[0x8]; 6142 u8 reserved_0[0x18]; 6143 6144 u8 syndrome[0x20]; 6145 6146 u8 reserved_1[0x40]; 6147 }; 6148 6149 struct mlx5_ifc_destroy_sq_in_bits { 6150 u8 opcode[0x10]; 6151 u8 reserved_0[0x10]; 6152 6153 u8 reserved_1[0x10]; 6154 u8 op_mod[0x10]; 6155 6156 u8 reserved_2[0x8]; 6157 u8 sqn[0x18]; 6158 6159 u8 reserved_3[0x20]; 6160 }; 6161 6162 struct mlx5_ifc_destroy_scheduling_element_out_bits { 6163 u8 status[0x8]; 6164 u8 reserved_at_8[0x18]; 6165 6166 u8 syndrome[0x20]; 6167 6168 u8 reserved_at_40[0x1c0]; 6169 }; 6170 6171 enum { 6172 MLX5_DESTROY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 6173 }; 6174 6175 struct mlx5_ifc_destroy_scheduling_element_in_bits { 6176 u8 opcode[0x10]; 6177 u8 reserved_at_10[0x10]; 6178 6179 u8 reserved_at_20[0x10]; 6180 u8 op_mod[0x10]; 6181 6182 u8 scheduling_hierarchy[0x8]; 6183 u8 reserved_at_48[0x18]; 6184 6185 u8 scheduling_element_id[0x20]; 6186 6187 u8 reserved_at_80[0x180]; 6188 }; 6189 6190 struct mlx5_ifc_destroy_rqt_out_bits { 6191 u8 status[0x8]; 6192 u8 reserved_0[0x18]; 6193 6194 u8 syndrome[0x20]; 6195 6196 u8 reserved_1[0x40]; 6197 }; 6198 6199 struct mlx5_ifc_destroy_rqt_in_bits { 6200 u8 opcode[0x10]; 6201 u8 reserved_0[0x10]; 6202 6203 u8 reserved_1[0x10]; 6204 u8 op_mod[0x10]; 6205 6206 u8 reserved_2[0x8]; 6207 u8 rqtn[0x18]; 6208 6209 u8 reserved_3[0x20]; 6210 }; 6211 6212 struct mlx5_ifc_destroy_rq_out_bits { 6213 u8 status[0x8]; 6214 u8 reserved_0[0x18]; 6215 6216 u8 syndrome[0x20]; 6217 6218 u8 reserved_1[0x40]; 6219 }; 6220 6221 struct mlx5_ifc_destroy_rq_in_bits { 6222 u8 opcode[0x10]; 6223 u8 reserved_0[0x10]; 6224 6225 u8 reserved_1[0x10]; 6226 u8 op_mod[0x10]; 6227 6228 u8 reserved_2[0x8]; 6229 u8 rqn[0x18]; 6230 6231 u8 reserved_3[0x20]; 6232 }; 6233 6234 struct mlx5_ifc_destroy_rmp_out_bits { 6235 u8 status[0x8]; 6236 u8 reserved_0[0x18]; 6237 6238 u8 syndrome[0x20]; 6239 6240 u8 reserved_1[0x40]; 6241 }; 6242 6243 struct mlx5_ifc_destroy_rmp_in_bits { 6244 u8 opcode[0x10]; 6245 u8 reserved_0[0x10]; 6246 6247 u8 reserved_1[0x10]; 6248 u8 op_mod[0x10]; 6249 6250 u8 reserved_2[0x8]; 6251 u8 rmpn[0x18]; 6252 6253 u8 reserved_3[0x20]; 6254 }; 6255 6256 struct mlx5_ifc_destroy_qp_out_bits { 6257 u8 status[0x8]; 6258 u8 reserved_0[0x18]; 6259 6260 u8 syndrome[0x20]; 6261 6262 u8 reserved_1[0x40]; 6263 }; 6264 6265 struct mlx5_ifc_destroy_qp_in_bits { 6266 u8 opcode[0x10]; 6267 u8 reserved_0[0x10]; 6268 6269 u8 reserved_1[0x10]; 6270 u8 op_mod[0x10]; 6271 6272 u8 reserved_2[0x8]; 6273 u8 qpn[0x18]; 6274 6275 u8 reserved_3[0x20]; 6276 }; 6277 6278 struct mlx5_ifc_destroy_qos_para_vport_out_bits { 6279 u8 status[0x8]; 6280 u8 reserved_at_8[0x18]; 6281 6282 u8 syndrome[0x20]; 6283 6284 u8 reserved_at_40[0x1c0]; 6285 }; 6286 6287 struct mlx5_ifc_destroy_qos_para_vport_in_bits { 6288 u8 opcode[0x10]; 6289 u8 reserved_at_10[0x10]; 6290 6291 u8 reserved_at_20[0x10]; 6292 u8 op_mod[0x10]; 6293 6294 u8 reserved_at_40[0x20]; 6295 6296 u8 reserved_at_60[0x10]; 6297 u8 qos_para_vport_number[0x10]; 6298 6299 u8 reserved_at_80[0x180]; 6300 }; 6301 6302 struct mlx5_ifc_destroy_psv_out_bits { 6303 u8 status[0x8]; 6304 u8 reserved_0[0x18]; 6305 6306 u8 syndrome[0x20]; 6307 6308 u8 reserved_1[0x40]; 6309 }; 6310 6311 struct mlx5_ifc_destroy_psv_in_bits { 6312 u8 opcode[0x10]; 6313 u8 reserved_0[0x10]; 6314 6315 u8 reserved_1[0x10]; 6316 u8 op_mod[0x10]; 6317 6318 u8 reserved_2[0x8]; 6319 u8 psvn[0x18]; 6320 6321 u8 reserved_3[0x20]; 6322 }; 6323 6324 struct mlx5_ifc_destroy_mkey_out_bits { 6325 u8 status[0x8]; 6326 u8 reserved_0[0x18]; 6327 6328 u8 syndrome[0x20]; 6329 6330 u8 reserved_1[0x40]; 6331 }; 6332 6333 struct mlx5_ifc_destroy_mkey_in_bits { 6334 u8 opcode[0x10]; 6335 u8 reserved_0[0x10]; 6336 6337 u8 reserved_1[0x10]; 6338 u8 op_mod[0x10]; 6339 6340 u8 reserved_2[0x8]; 6341 u8 mkey_index[0x18]; 6342 6343 u8 reserved_3[0x20]; 6344 }; 6345 6346 struct mlx5_ifc_destroy_flow_table_out_bits { 6347 u8 status[0x8]; 6348 u8 reserved_0[0x18]; 6349 6350 u8 syndrome[0x20]; 6351 6352 u8 reserved_1[0x40]; 6353 }; 6354 6355 struct mlx5_ifc_destroy_flow_table_in_bits { 6356 u8 opcode[0x10]; 6357 u8 reserved_0[0x10]; 6358 6359 u8 reserved_1[0x10]; 6360 u8 op_mod[0x10]; 6361 6362 u8 other_vport[0x1]; 6363 u8 reserved_2[0xf]; 6364 u8 vport_number[0x10]; 6365 6366 u8 reserved_3[0x20]; 6367 6368 u8 table_type[0x8]; 6369 u8 reserved_4[0x18]; 6370 6371 u8 reserved_5[0x8]; 6372 u8 table_id[0x18]; 6373 6374 u8 reserved_6[0x140]; 6375 }; 6376 6377 struct mlx5_ifc_destroy_flow_group_out_bits { 6378 u8 status[0x8]; 6379 u8 reserved_0[0x18]; 6380 6381 u8 syndrome[0x20]; 6382 6383 u8 reserved_1[0x40]; 6384 }; 6385 6386 struct mlx5_ifc_destroy_flow_group_in_bits { 6387 u8 opcode[0x10]; 6388 u8 reserved_0[0x10]; 6389 6390 u8 reserved_1[0x10]; 6391 u8 op_mod[0x10]; 6392 6393 u8 other_vport[0x1]; 6394 u8 reserved_2[0xf]; 6395 u8 vport_number[0x10]; 6396 6397 u8 reserved_3[0x20]; 6398 6399 u8 table_type[0x8]; 6400 u8 reserved_4[0x18]; 6401 6402 u8 reserved_5[0x8]; 6403 u8 table_id[0x18]; 6404 6405 u8 group_id[0x20]; 6406 6407 u8 reserved_6[0x120]; 6408 }; 6409 6410 struct mlx5_ifc_destroy_eq_out_bits { 6411 u8 status[0x8]; 6412 u8 reserved_0[0x18]; 6413 6414 u8 syndrome[0x20]; 6415 6416 u8 reserved_1[0x40]; 6417 }; 6418 6419 struct mlx5_ifc_destroy_eq_in_bits { 6420 u8 opcode[0x10]; 6421 u8 reserved_0[0x10]; 6422 6423 u8 reserved_1[0x10]; 6424 u8 op_mod[0x10]; 6425 6426 u8 reserved_2[0x18]; 6427 u8 eq_number[0x8]; 6428 6429 u8 reserved_3[0x20]; 6430 }; 6431 6432 struct mlx5_ifc_destroy_dct_out_bits { 6433 u8 status[0x8]; 6434 u8 reserved_0[0x18]; 6435 6436 u8 syndrome[0x20]; 6437 6438 u8 reserved_1[0x40]; 6439 }; 6440 6441 struct mlx5_ifc_destroy_dct_in_bits { 6442 u8 opcode[0x10]; 6443 u8 reserved_0[0x10]; 6444 6445 u8 reserved_1[0x10]; 6446 u8 op_mod[0x10]; 6447 6448 u8 reserved_2[0x8]; 6449 u8 dctn[0x18]; 6450 6451 u8 reserved_3[0x20]; 6452 }; 6453 6454 struct mlx5_ifc_destroy_cq_out_bits { 6455 u8 status[0x8]; 6456 u8 reserved_0[0x18]; 6457 6458 u8 syndrome[0x20]; 6459 6460 u8 reserved_1[0x40]; 6461 }; 6462 6463 struct mlx5_ifc_destroy_cq_in_bits { 6464 u8 opcode[0x10]; 6465 u8 reserved_0[0x10]; 6466 6467 u8 reserved_1[0x10]; 6468 u8 op_mod[0x10]; 6469 6470 u8 reserved_2[0x8]; 6471 u8 cqn[0x18]; 6472 6473 u8 reserved_3[0x20]; 6474 }; 6475 6476 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 6477 u8 status[0x8]; 6478 u8 reserved_0[0x18]; 6479 6480 u8 syndrome[0x20]; 6481 6482 u8 reserved_1[0x40]; 6483 }; 6484 6485 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 6486 u8 opcode[0x10]; 6487 u8 reserved_0[0x10]; 6488 6489 u8 reserved_1[0x10]; 6490 u8 op_mod[0x10]; 6491 6492 u8 reserved_2[0x20]; 6493 6494 u8 reserved_3[0x10]; 6495 u8 vxlan_udp_port[0x10]; 6496 }; 6497 6498 struct mlx5_ifc_delete_l2_table_entry_out_bits { 6499 u8 status[0x8]; 6500 u8 reserved_0[0x18]; 6501 6502 u8 syndrome[0x20]; 6503 6504 u8 reserved_1[0x40]; 6505 }; 6506 6507 struct mlx5_ifc_delete_l2_table_entry_in_bits { 6508 u8 opcode[0x10]; 6509 u8 reserved_0[0x10]; 6510 6511 u8 reserved_1[0x10]; 6512 u8 op_mod[0x10]; 6513 6514 u8 reserved_2[0x60]; 6515 6516 u8 reserved_3[0x8]; 6517 u8 table_index[0x18]; 6518 6519 u8 reserved_4[0x140]; 6520 }; 6521 6522 struct mlx5_ifc_delete_fte_out_bits { 6523 u8 status[0x8]; 6524 u8 reserved_0[0x18]; 6525 6526 u8 syndrome[0x20]; 6527 6528 u8 reserved_1[0x40]; 6529 }; 6530 6531 struct mlx5_ifc_delete_fte_in_bits { 6532 u8 opcode[0x10]; 6533 u8 reserved_0[0x10]; 6534 6535 u8 reserved_1[0x10]; 6536 u8 op_mod[0x10]; 6537 6538 u8 other_vport[0x1]; 6539 u8 reserved_2[0xf]; 6540 u8 vport_number[0x10]; 6541 6542 u8 reserved_3[0x20]; 6543 6544 u8 table_type[0x8]; 6545 u8 reserved_4[0x18]; 6546 6547 u8 reserved_5[0x8]; 6548 u8 table_id[0x18]; 6549 6550 u8 reserved_6[0x40]; 6551 6552 u8 flow_index[0x20]; 6553 6554 u8 reserved_7[0xe0]; 6555 }; 6556 6557 struct mlx5_ifc_dealloc_xrcd_out_bits { 6558 u8 status[0x8]; 6559 u8 reserved_0[0x18]; 6560 6561 u8 syndrome[0x20]; 6562 6563 u8 reserved_1[0x40]; 6564 }; 6565 6566 struct mlx5_ifc_dealloc_xrcd_in_bits { 6567 u8 opcode[0x10]; 6568 u8 reserved_0[0x10]; 6569 6570 u8 reserved_1[0x10]; 6571 u8 op_mod[0x10]; 6572 6573 u8 reserved_2[0x8]; 6574 u8 xrcd[0x18]; 6575 6576 u8 reserved_3[0x20]; 6577 }; 6578 6579 struct mlx5_ifc_dealloc_uar_out_bits { 6580 u8 status[0x8]; 6581 u8 reserved_0[0x18]; 6582 6583 u8 syndrome[0x20]; 6584 6585 u8 reserved_1[0x40]; 6586 }; 6587 6588 struct mlx5_ifc_dealloc_uar_in_bits { 6589 u8 opcode[0x10]; 6590 u8 reserved_0[0x10]; 6591 6592 u8 reserved_1[0x10]; 6593 u8 op_mod[0x10]; 6594 6595 u8 reserved_2[0x8]; 6596 u8 uar[0x18]; 6597 6598 u8 reserved_3[0x20]; 6599 }; 6600 6601 struct mlx5_ifc_dealloc_transport_domain_out_bits { 6602 u8 status[0x8]; 6603 u8 reserved_0[0x18]; 6604 6605 u8 syndrome[0x20]; 6606 6607 u8 reserved_1[0x40]; 6608 }; 6609 6610 struct mlx5_ifc_dealloc_transport_domain_in_bits { 6611 u8 opcode[0x10]; 6612 u8 reserved_0[0x10]; 6613 6614 u8 reserved_1[0x10]; 6615 u8 op_mod[0x10]; 6616 6617 u8 reserved_2[0x8]; 6618 u8 transport_domain[0x18]; 6619 6620 u8 reserved_3[0x20]; 6621 }; 6622 6623 struct mlx5_ifc_dealloc_q_counter_out_bits { 6624 u8 status[0x8]; 6625 u8 reserved_0[0x18]; 6626 6627 u8 syndrome[0x20]; 6628 6629 u8 reserved_1[0x40]; 6630 }; 6631 6632 struct mlx5_ifc_counter_id_bits { 6633 u8 reserved[0x10]; 6634 u8 counter_id[0x10]; 6635 }; 6636 6637 struct mlx5_ifc_diagnostic_params_context_bits { 6638 u8 num_of_counters[0x10]; 6639 u8 reserved_2[0x8]; 6640 u8 log_num_of_samples[0x8]; 6641 6642 u8 single[0x1]; 6643 u8 repetitive[0x1]; 6644 u8 sync[0x1]; 6645 u8 clear[0x1]; 6646 u8 on_demand[0x1]; 6647 u8 enable[0x1]; 6648 u8 reserved_3[0x12]; 6649 u8 log_sample_period[0x8]; 6650 6651 u8 reserved_4[0x80]; 6652 6653 struct mlx5_ifc_counter_id_bits counter_id[0]; 6654 }; 6655 6656 struct mlx5_ifc_set_diagnostic_params_in_bits { 6657 u8 opcode[0x10]; 6658 u8 reserved_0[0x10]; 6659 6660 u8 reserved_1[0x10]; 6661 u8 op_mod[0x10]; 6662 6663 struct mlx5_ifc_diagnostic_params_context_bits diagnostic_params_ctx; 6664 }; 6665 6666 struct mlx5_ifc_set_diagnostic_params_out_bits { 6667 u8 status[0x8]; 6668 u8 reserved_0[0x18]; 6669 6670 u8 syndrome[0x20]; 6671 6672 u8 reserved_1[0x40]; 6673 }; 6674 6675 struct mlx5_ifc_query_diagnostic_counters_in_bits { 6676 u8 opcode[0x10]; 6677 u8 reserved_0[0x10]; 6678 6679 u8 reserved_1[0x10]; 6680 u8 op_mod[0x10]; 6681 6682 u8 num_of_samples[0x10]; 6683 u8 sample_index[0x10]; 6684 6685 u8 reserved_2[0x20]; 6686 }; 6687 6688 struct mlx5_ifc_diagnostic_counter_bits { 6689 u8 counter_id[0x10]; 6690 u8 sample_id[0x10]; 6691 6692 u8 time_stamp_31_0[0x20]; 6693 6694 u8 counter_value_h[0x20]; 6695 6696 u8 counter_value_l[0x20]; 6697 }; 6698 6699 struct mlx5_ifc_query_diagnostic_counters_out_bits { 6700 u8 status[0x8]; 6701 u8 reserved_0[0x18]; 6702 6703 u8 syndrome[0x20]; 6704 6705 u8 reserved_1[0x40]; 6706 6707 struct mlx5_ifc_diagnostic_counter_bits diag_counter[0]; 6708 }; 6709 6710 struct mlx5_ifc_dealloc_q_counter_in_bits { 6711 u8 opcode[0x10]; 6712 u8 reserved_0[0x10]; 6713 6714 u8 reserved_1[0x10]; 6715 u8 op_mod[0x10]; 6716 6717 u8 reserved_2[0x18]; 6718 u8 counter_set_id[0x8]; 6719 6720 u8 reserved_3[0x20]; 6721 }; 6722 6723 struct mlx5_ifc_dealloc_pd_out_bits { 6724 u8 status[0x8]; 6725 u8 reserved_0[0x18]; 6726 6727 u8 syndrome[0x20]; 6728 6729 u8 reserved_1[0x40]; 6730 }; 6731 6732 struct mlx5_ifc_dealloc_pd_in_bits { 6733 u8 opcode[0x10]; 6734 u8 reserved_0[0x10]; 6735 6736 u8 reserved_1[0x10]; 6737 u8 op_mod[0x10]; 6738 6739 u8 reserved_2[0x8]; 6740 u8 pd[0x18]; 6741 6742 u8 reserved_3[0x20]; 6743 }; 6744 6745 struct mlx5_ifc_dealloc_flow_counter_out_bits { 6746 u8 status[0x8]; 6747 u8 reserved_0[0x18]; 6748 6749 u8 syndrome[0x20]; 6750 6751 u8 reserved_1[0x40]; 6752 }; 6753 6754 struct mlx5_ifc_dealloc_flow_counter_in_bits { 6755 u8 opcode[0x10]; 6756 u8 reserved_0[0x10]; 6757 6758 u8 reserved_1[0x10]; 6759 u8 op_mod[0x10]; 6760 6761 u8 reserved_2[0x10]; 6762 u8 flow_counter_id[0x10]; 6763 6764 u8 reserved_3[0x20]; 6765 }; 6766 6767 struct mlx5_ifc_deactivate_tracer_out_bits { 6768 u8 status[0x8]; 6769 u8 reserved_0[0x18]; 6770 6771 u8 syndrome[0x20]; 6772 6773 u8 reserved_1[0x40]; 6774 }; 6775 6776 struct mlx5_ifc_deactivate_tracer_in_bits { 6777 u8 opcode[0x10]; 6778 u8 reserved_0[0x10]; 6779 6780 u8 reserved_1[0x10]; 6781 u8 op_mod[0x10]; 6782 6783 u8 mkey[0x20]; 6784 6785 u8 reserved_2[0x20]; 6786 }; 6787 6788 struct mlx5_ifc_create_xrc_srq_out_bits { 6789 u8 status[0x8]; 6790 u8 reserved_0[0x18]; 6791 6792 u8 syndrome[0x20]; 6793 6794 u8 reserved_1[0x8]; 6795 u8 xrc_srqn[0x18]; 6796 6797 u8 reserved_2[0x20]; 6798 }; 6799 6800 struct mlx5_ifc_create_xrc_srq_in_bits { 6801 u8 opcode[0x10]; 6802 u8 reserved_0[0x10]; 6803 6804 u8 reserved_1[0x10]; 6805 u8 op_mod[0x10]; 6806 6807 u8 reserved_2[0x40]; 6808 6809 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 6810 6811 u8 reserved_3[0x600]; 6812 6813 u8 pas[0][0x40]; 6814 }; 6815 6816 struct mlx5_ifc_create_tis_out_bits { 6817 u8 status[0x8]; 6818 u8 reserved_0[0x18]; 6819 6820 u8 syndrome[0x20]; 6821 6822 u8 reserved_1[0x8]; 6823 u8 tisn[0x18]; 6824 6825 u8 reserved_2[0x20]; 6826 }; 6827 6828 struct mlx5_ifc_create_tis_in_bits { 6829 u8 opcode[0x10]; 6830 u8 reserved_0[0x10]; 6831 6832 u8 reserved_1[0x10]; 6833 u8 op_mod[0x10]; 6834 6835 u8 reserved_2[0xc0]; 6836 6837 struct mlx5_ifc_tisc_bits ctx; 6838 }; 6839 6840 struct mlx5_ifc_create_tir_out_bits { 6841 u8 status[0x8]; 6842 u8 reserved_0[0x18]; 6843 6844 u8 syndrome[0x20]; 6845 6846 u8 reserved_1[0x8]; 6847 u8 tirn[0x18]; 6848 6849 u8 reserved_2[0x20]; 6850 }; 6851 6852 struct mlx5_ifc_create_tir_in_bits { 6853 u8 opcode[0x10]; 6854 u8 reserved_0[0x10]; 6855 6856 u8 reserved_1[0x10]; 6857 u8 op_mod[0x10]; 6858 6859 u8 reserved_2[0xc0]; 6860 6861 struct mlx5_ifc_tirc_bits tir_context; 6862 }; 6863 6864 struct mlx5_ifc_create_srq_out_bits { 6865 u8 status[0x8]; 6866 u8 reserved_0[0x18]; 6867 6868 u8 syndrome[0x20]; 6869 6870 u8 reserved_1[0x8]; 6871 u8 srqn[0x18]; 6872 6873 u8 reserved_2[0x20]; 6874 }; 6875 6876 struct mlx5_ifc_create_srq_in_bits { 6877 u8 opcode[0x10]; 6878 u8 reserved_0[0x10]; 6879 6880 u8 reserved_1[0x10]; 6881 u8 op_mod[0x10]; 6882 6883 u8 reserved_2[0x40]; 6884 6885 struct mlx5_ifc_srqc_bits srq_context_entry; 6886 6887 u8 reserved_3[0x600]; 6888 6889 u8 pas[0][0x40]; 6890 }; 6891 6892 struct mlx5_ifc_create_sq_out_bits { 6893 u8 status[0x8]; 6894 u8 reserved_0[0x18]; 6895 6896 u8 syndrome[0x20]; 6897 6898 u8 reserved_1[0x8]; 6899 u8 sqn[0x18]; 6900 6901 u8 reserved_2[0x20]; 6902 }; 6903 6904 struct mlx5_ifc_create_sq_in_bits { 6905 u8 opcode[0x10]; 6906 u8 reserved_0[0x10]; 6907 6908 u8 reserved_1[0x10]; 6909 u8 op_mod[0x10]; 6910 6911 u8 reserved_2[0xc0]; 6912 6913 struct mlx5_ifc_sqc_bits ctx; 6914 }; 6915 6916 struct mlx5_ifc_create_scheduling_element_out_bits { 6917 u8 status[0x8]; 6918 u8 reserved_at_8[0x18]; 6919 6920 u8 syndrome[0x20]; 6921 6922 u8 reserved_at_40[0x40]; 6923 6924 u8 scheduling_element_id[0x20]; 6925 6926 u8 reserved_at_a0[0x160]; 6927 }; 6928 6929 enum { 6930 MLX5_CREATE_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 6931 }; 6932 6933 struct mlx5_ifc_create_scheduling_element_in_bits { 6934 u8 opcode[0x10]; 6935 u8 reserved_at_10[0x10]; 6936 6937 u8 reserved_at_20[0x10]; 6938 u8 op_mod[0x10]; 6939 6940 u8 scheduling_hierarchy[0x8]; 6941 u8 reserved_at_48[0x18]; 6942 6943 u8 reserved_at_60[0xa0]; 6944 6945 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6946 6947 u8 reserved_at_300[0x100]; 6948 }; 6949 6950 struct mlx5_ifc_create_rqt_out_bits { 6951 u8 status[0x8]; 6952 u8 reserved_0[0x18]; 6953 6954 u8 syndrome[0x20]; 6955 6956 u8 reserved_1[0x8]; 6957 u8 rqtn[0x18]; 6958 6959 u8 reserved_2[0x20]; 6960 }; 6961 6962 struct mlx5_ifc_create_rqt_in_bits { 6963 u8 opcode[0x10]; 6964 u8 reserved_0[0x10]; 6965 6966 u8 reserved_1[0x10]; 6967 u8 op_mod[0x10]; 6968 6969 u8 reserved_2[0xc0]; 6970 6971 struct mlx5_ifc_rqtc_bits rqt_context; 6972 }; 6973 6974 struct mlx5_ifc_create_rq_out_bits { 6975 u8 status[0x8]; 6976 u8 reserved_0[0x18]; 6977 6978 u8 syndrome[0x20]; 6979 6980 u8 reserved_1[0x8]; 6981 u8 rqn[0x18]; 6982 6983 u8 reserved_2[0x20]; 6984 }; 6985 6986 struct mlx5_ifc_create_rq_in_bits { 6987 u8 opcode[0x10]; 6988 u8 reserved_0[0x10]; 6989 6990 u8 reserved_1[0x10]; 6991 u8 op_mod[0x10]; 6992 6993 u8 reserved_2[0xc0]; 6994 6995 struct mlx5_ifc_rqc_bits ctx; 6996 }; 6997 6998 struct mlx5_ifc_create_rmp_out_bits { 6999 u8 status[0x8]; 7000 u8 reserved_0[0x18]; 7001 7002 u8 syndrome[0x20]; 7003 7004 u8 reserved_1[0x8]; 7005 u8 rmpn[0x18]; 7006 7007 u8 reserved_2[0x20]; 7008 }; 7009 7010 struct mlx5_ifc_create_rmp_in_bits { 7011 u8 opcode[0x10]; 7012 u8 reserved_0[0x10]; 7013 7014 u8 reserved_1[0x10]; 7015 u8 op_mod[0x10]; 7016 7017 u8 reserved_2[0xc0]; 7018 7019 struct mlx5_ifc_rmpc_bits ctx; 7020 }; 7021 7022 struct mlx5_ifc_create_qp_out_bits { 7023 u8 status[0x8]; 7024 u8 reserved_0[0x18]; 7025 7026 u8 syndrome[0x20]; 7027 7028 u8 reserved_1[0x8]; 7029 u8 qpn[0x18]; 7030 7031 u8 reserved_2[0x20]; 7032 }; 7033 7034 struct mlx5_ifc_create_qp_in_bits { 7035 u8 opcode[0x10]; 7036 u8 reserved_0[0x10]; 7037 7038 u8 reserved_1[0x10]; 7039 u8 op_mod[0x10]; 7040 7041 u8 reserved_2[0x8]; 7042 u8 input_qpn[0x18]; 7043 7044 u8 reserved_3[0x20]; 7045 7046 u8 opt_param_mask[0x20]; 7047 7048 u8 reserved_4[0x20]; 7049 7050 struct mlx5_ifc_qpc_bits qpc; 7051 7052 u8 reserved_5[0x80]; 7053 7054 u8 pas[0][0x40]; 7055 }; 7056 7057 struct mlx5_ifc_create_qos_para_vport_out_bits { 7058 u8 status[0x8]; 7059 u8 reserved_at_8[0x18]; 7060 7061 u8 syndrome[0x20]; 7062 7063 u8 reserved_at_40[0x20]; 7064 7065 u8 reserved_at_60[0x10]; 7066 u8 qos_para_vport_number[0x10]; 7067 7068 u8 reserved_at_80[0x180]; 7069 }; 7070 7071 struct mlx5_ifc_create_qos_para_vport_in_bits { 7072 u8 opcode[0x10]; 7073 u8 reserved_at_10[0x10]; 7074 7075 u8 reserved_at_20[0x10]; 7076 u8 op_mod[0x10]; 7077 7078 u8 reserved_at_40[0x1c0]; 7079 }; 7080 7081 struct mlx5_ifc_create_psv_out_bits { 7082 u8 status[0x8]; 7083 u8 reserved_0[0x18]; 7084 7085 u8 syndrome[0x20]; 7086 7087 u8 reserved_1[0x40]; 7088 7089 u8 reserved_2[0x8]; 7090 u8 psv0_index[0x18]; 7091 7092 u8 reserved_3[0x8]; 7093 u8 psv1_index[0x18]; 7094 7095 u8 reserved_4[0x8]; 7096 u8 psv2_index[0x18]; 7097 7098 u8 reserved_5[0x8]; 7099 u8 psv3_index[0x18]; 7100 }; 7101 7102 struct mlx5_ifc_create_psv_in_bits { 7103 u8 opcode[0x10]; 7104 u8 reserved_0[0x10]; 7105 7106 u8 reserved_1[0x10]; 7107 u8 op_mod[0x10]; 7108 7109 u8 num_psv[0x4]; 7110 u8 reserved_2[0x4]; 7111 u8 pd[0x18]; 7112 7113 u8 reserved_3[0x20]; 7114 }; 7115 7116 struct mlx5_ifc_create_mkey_out_bits { 7117 u8 status[0x8]; 7118 u8 reserved_0[0x18]; 7119 7120 u8 syndrome[0x20]; 7121 7122 u8 reserved_1[0x8]; 7123 u8 mkey_index[0x18]; 7124 7125 u8 reserved_2[0x20]; 7126 }; 7127 7128 struct mlx5_ifc_create_mkey_in_bits { 7129 u8 opcode[0x10]; 7130 u8 reserved_0[0x10]; 7131 7132 u8 reserved_1[0x10]; 7133 u8 op_mod[0x10]; 7134 7135 u8 reserved_2[0x20]; 7136 7137 u8 pg_access[0x1]; 7138 u8 reserved_3[0x1f]; 7139 7140 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 7141 7142 u8 reserved_4[0x80]; 7143 7144 u8 translations_octword_actual_size[0x20]; 7145 7146 u8 reserved_5[0x560]; 7147 7148 u8 klm_pas_mtt[0][0x20]; 7149 }; 7150 7151 struct mlx5_ifc_create_flow_table_out_bits { 7152 u8 status[0x8]; 7153 u8 reserved_0[0x18]; 7154 7155 u8 syndrome[0x20]; 7156 7157 u8 reserved_1[0x8]; 7158 u8 table_id[0x18]; 7159 7160 u8 reserved_2[0x20]; 7161 }; 7162 7163 struct mlx5_ifc_create_flow_table_in_bits { 7164 u8 opcode[0x10]; 7165 u8 reserved_at_10[0x10]; 7166 7167 u8 reserved_at_20[0x10]; 7168 u8 op_mod[0x10]; 7169 7170 u8 other_vport[0x1]; 7171 u8 reserved_at_41[0xf]; 7172 u8 vport_number[0x10]; 7173 7174 u8 reserved_at_60[0x20]; 7175 7176 u8 table_type[0x8]; 7177 u8 reserved_at_88[0x18]; 7178 7179 u8 reserved_at_a0[0x20]; 7180 7181 struct mlx5_ifc_flow_table_context_bits flow_table_context; 7182 }; 7183 7184 struct mlx5_ifc_create_flow_group_out_bits { 7185 u8 status[0x8]; 7186 u8 reserved_0[0x18]; 7187 7188 u8 syndrome[0x20]; 7189 7190 u8 reserved_1[0x8]; 7191 u8 group_id[0x18]; 7192 7193 u8 reserved_2[0x20]; 7194 }; 7195 7196 enum { 7197 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 7198 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 7199 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 7200 }; 7201 7202 struct mlx5_ifc_create_flow_group_in_bits { 7203 u8 opcode[0x10]; 7204 u8 reserved_0[0x10]; 7205 7206 u8 reserved_1[0x10]; 7207 u8 op_mod[0x10]; 7208 7209 u8 other_vport[0x1]; 7210 u8 reserved_2[0xf]; 7211 u8 vport_number[0x10]; 7212 7213 u8 reserved_3[0x20]; 7214 7215 u8 table_type[0x8]; 7216 u8 reserved_4[0x18]; 7217 7218 u8 reserved_5[0x8]; 7219 u8 table_id[0x18]; 7220 7221 u8 reserved_6[0x20]; 7222 7223 u8 start_flow_index[0x20]; 7224 7225 u8 reserved_7[0x20]; 7226 7227 u8 end_flow_index[0x20]; 7228 7229 u8 reserved_8[0xa0]; 7230 7231 u8 reserved_9[0x18]; 7232 u8 match_criteria_enable[0x8]; 7233 7234 struct mlx5_ifc_fte_match_param_bits match_criteria; 7235 7236 u8 reserved_10[0xe00]; 7237 }; 7238 7239 struct mlx5_ifc_create_eq_out_bits { 7240 u8 status[0x8]; 7241 u8 reserved_0[0x18]; 7242 7243 u8 syndrome[0x20]; 7244 7245 u8 reserved_1[0x18]; 7246 u8 eq_number[0x8]; 7247 7248 u8 reserved_2[0x20]; 7249 }; 7250 7251 struct mlx5_ifc_create_eq_in_bits { 7252 u8 opcode[0x10]; 7253 u8 reserved_0[0x10]; 7254 7255 u8 reserved_1[0x10]; 7256 u8 op_mod[0x10]; 7257 7258 u8 reserved_2[0x40]; 7259 7260 struct mlx5_ifc_eqc_bits eq_context_entry; 7261 7262 u8 reserved_3[0x40]; 7263 7264 u8 event_bitmask[0x40]; 7265 7266 u8 reserved_4[0x580]; 7267 7268 u8 pas[0][0x40]; 7269 }; 7270 7271 struct mlx5_ifc_create_dct_out_bits { 7272 u8 status[0x8]; 7273 u8 reserved_0[0x18]; 7274 7275 u8 syndrome[0x20]; 7276 7277 u8 reserved_1[0x8]; 7278 u8 dctn[0x18]; 7279 7280 u8 reserved_2[0x20]; 7281 }; 7282 7283 struct mlx5_ifc_create_dct_in_bits { 7284 u8 opcode[0x10]; 7285 u8 reserved_0[0x10]; 7286 7287 u8 reserved_1[0x10]; 7288 u8 op_mod[0x10]; 7289 7290 u8 reserved_2[0x40]; 7291 7292 struct mlx5_ifc_dctc_bits dct_context_entry; 7293 7294 u8 reserved_3[0x180]; 7295 }; 7296 7297 struct mlx5_ifc_create_cq_out_bits { 7298 u8 status[0x8]; 7299 u8 reserved_0[0x18]; 7300 7301 u8 syndrome[0x20]; 7302 7303 u8 reserved_1[0x8]; 7304 u8 cqn[0x18]; 7305 7306 u8 reserved_2[0x20]; 7307 }; 7308 7309 struct mlx5_ifc_create_cq_in_bits { 7310 u8 opcode[0x10]; 7311 u8 reserved_0[0x10]; 7312 7313 u8 reserved_1[0x10]; 7314 u8 op_mod[0x10]; 7315 7316 u8 reserved_2[0x40]; 7317 7318 struct mlx5_ifc_cqc_bits cq_context; 7319 7320 u8 reserved_3[0x600]; 7321 7322 u8 pas[0][0x40]; 7323 }; 7324 7325 struct mlx5_ifc_config_int_moderation_out_bits { 7326 u8 status[0x8]; 7327 u8 reserved_0[0x18]; 7328 7329 u8 syndrome[0x20]; 7330 7331 u8 reserved_1[0x4]; 7332 u8 min_delay[0xc]; 7333 u8 int_vector[0x10]; 7334 7335 u8 reserved_2[0x20]; 7336 }; 7337 7338 enum { 7339 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 7340 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 7341 }; 7342 7343 struct mlx5_ifc_config_int_moderation_in_bits { 7344 u8 opcode[0x10]; 7345 u8 reserved_0[0x10]; 7346 7347 u8 reserved_1[0x10]; 7348 u8 op_mod[0x10]; 7349 7350 u8 reserved_2[0x4]; 7351 u8 min_delay[0xc]; 7352 u8 int_vector[0x10]; 7353 7354 u8 reserved_3[0x20]; 7355 }; 7356 7357 struct mlx5_ifc_attach_to_mcg_out_bits { 7358 u8 status[0x8]; 7359 u8 reserved_0[0x18]; 7360 7361 u8 syndrome[0x20]; 7362 7363 u8 reserved_1[0x40]; 7364 }; 7365 7366 struct mlx5_ifc_attach_to_mcg_in_bits { 7367 u8 opcode[0x10]; 7368 u8 reserved_0[0x10]; 7369 7370 u8 reserved_1[0x10]; 7371 u8 op_mod[0x10]; 7372 7373 u8 reserved_2[0x8]; 7374 u8 qpn[0x18]; 7375 7376 u8 reserved_3[0x20]; 7377 7378 u8 multicast_gid[16][0x8]; 7379 }; 7380 7381 struct mlx5_ifc_arm_xrc_srq_out_bits { 7382 u8 status[0x8]; 7383 u8 reserved_0[0x18]; 7384 7385 u8 syndrome[0x20]; 7386 7387 u8 reserved_1[0x40]; 7388 }; 7389 7390 enum { 7391 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 7392 }; 7393 7394 struct mlx5_ifc_arm_xrc_srq_in_bits { 7395 u8 opcode[0x10]; 7396 u8 reserved_0[0x10]; 7397 7398 u8 reserved_1[0x10]; 7399 u8 op_mod[0x10]; 7400 7401 u8 reserved_2[0x8]; 7402 u8 xrc_srqn[0x18]; 7403 7404 u8 reserved_3[0x10]; 7405 u8 lwm[0x10]; 7406 }; 7407 7408 struct mlx5_ifc_arm_rq_out_bits { 7409 u8 status[0x8]; 7410 u8 reserved_0[0x18]; 7411 7412 u8 syndrome[0x20]; 7413 7414 u8 reserved_1[0x40]; 7415 }; 7416 7417 enum { 7418 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 7419 }; 7420 7421 struct mlx5_ifc_arm_rq_in_bits { 7422 u8 opcode[0x10]; 7423 u8 reserved_0[0x10]; 7424 7425 u8 reserved_1[0x10]; 7426 u8 op_mod[0x10]; 7427 7428 u8 reserved_2[0x8]; 7429 u8 srq_number[0x18]; 7430 7431 u8 reserved_3[0x10]; 7432 u8 lwm[0x10]; 7433 }; 7434 7435 struct mlx5_ifc_arm_dct_out_bits { 7436 u8 status[0x8]; 7437 u8 reserved_0[0x18]; 7438 7439 u8 syndrome[0x20]; 7440 7441 u8 reserved_1[0x40]; 7442 }; 7443 7444 struct mlx5_ifc_arm_dct_in_bits { 7445 u8 opcode[0x10]; 7446 u8 reserved_0[0x10]; 7447 7448 u8 reserved_1[0x10]; 7449 u8 op_mod[0x10]; 7450 7451 u8 reserved_2[0x8]; 7452 u8 dctn[0x18]; 7453 7454 u8 reserved_3[0x20]; 7455 }; 7456 7457 struct mlx5_ifc_alloc_xrcd_out_bits { 7458 u8 status[0x8]; 7459 u8 reserved_0[0x18]; 7460 7461 u8 syndrome[0x20]; 7462 7463 u8 reserved_1[0x8]; 7464 u8 xrcd[0x18]; 7465 7466 u8 reserved_2[0x20]; 7467 }; 7468 7469 struct mlx5_ifc_alloc_xrcd_in_bits { 7470 u8 opcode[0x10]; 7471 u8 reserved_0[0x10]; 7472 7473 u8 reserved_1[0x10]; 7474 u8 op_mod[0x10]; 7475 7476 u8 reserved_2[0x40]; 7477 }; 7478 7479 struct mlx5_ifc_alloc_uar_out_bits { 7480 u8 status[0x8]; 7481 u8 reserved_0[0x18]; 7482 7483 u8 syndrome[0x20]; 7484 7485 u8 reserved_1[0x8]; 7486 u8 uar[0x18]; 7487 7488 u8 reserved_2[0x20]; 7489 }; 7490 7491 struct mlx5_ifc_alloc_uar_in_bits { 7492 u8 opcode[0x10]; 7493 u8 reserved_0[0x10]; 7494 7495 u8 reserved_1[0x10]; 7496 u8 op_mod[0x10]; 7497 7498 u8 reserved_2[0x40]; 7499 }; 7500 7501 struct mlx5_ifc_alloc_transport_domain_out_bits { 7502 u8 status[0x8]; 7503 u8 reserved_0[0x18]; 7504 7505 u8 syndrome[0x20]; 7506 7507 u8 reserved_1[0x8]; 7508 u8 transport_domain[0x18]; 7509 7510 u8 reserved_2[0x20]; 7511 }; 7512 7513 struct mlx5_ifc_alloc_transport_domain_in_bits { 7514 u8 opcode[0x10]; 7515 u8 reserved_0[0x10]; 7516 7517 u8 reserved_1[0x10]; 7518 u8 op_mod[0x10]; 7519 7520 u8 reserved_2[0x40]; 7521 }; 7522 7523 struct mlx5_ifc_alloc_q_counter_out_bits { 7524 u8 status[0x8]; 7525 u8 reserved_0[0x18]; 7526 7527 u8 syndrome[0x20]; 7528 7529 u8 reserved_1[0x18]; 7530 u8 counter_set_id[0x8]; 7531 7532 u8 reserved_2[0x20]; 7533 }; 7534 7535 struct mlx5_ifc_alloc_q_counter_in_bits { 7536 u8 opcode[0x10]; 7537 u8 reserved_0[0x10]; 7538 7539 u8 reserved_1[0x10]; 7540 u8 op_mod[0x10]; 7541 7542 u8 reserved_2[0x40]; 7543 }; 7544 7545 struct mlx5_ifc_alloc_pd_out_bits { 7546 u8 status[0x8]; 7547 u8 reserved_0[0x18]; 7548 7549 u8 syndrome[0x20]; 7550 7551 u8 reserved_1[0x8]; 7552 u8 pd[0x18]; 7553 7554 u8 reserved_2[0x20]; 7555 }; 7556 7557 struct mlx5_ifc_alloc_pd_in_bits { 7558 u8 opcode[0x10]; 7559 u8 reserved_0[0x10]; 7560 7561 u8 reserved_1[0x10]; 7562 u8 op_mod[0x10]; 7563 7564 u8 reserved_2[0x40]; 7565 }; 7566 7567 struct mlx5_ifc_alloc_flow_counter_out_bits { 7568 u8 status[0x8]; 7569 u8 reserved_0[0x18]; 7570 7571 u8 syndrome[0x20]; 7572 7573 u8 reserved_1[0x10]; 7574 u8 flow_counter_id[0x10]; 7575 7576 u8 reserved_2[0x20]; 7577 }; 7578 7579 struct mlx5_ifc_alloc_flow_counter_in_bits { 7580 u8 opcode[0x10]; 7581 u8 reserved_0[0x10]; 7582 7583 u8 reserved_1[0x10]; 7584 u8 op_mod[0x10]; 7585 7586 u8 reserved_2[0x40]; 7587 }; 7588 7589 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 7590 u8 status[0x8]; 7591 u8 reserved_0[0x18]; 7592 7593 u8 syndrome[0x20]; 7594 7595 u8 reserved_1[0x40]; 7596 }; 7597 7598 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 7599 u8 opcode[0x10]; 7600 u8 reserved_0[0x10]; 7601 7602 u8 reserved_1[0x10]; 7603 u8 op_mod[0x10]; 7604 7605 u8 reserved_2[0x20]; 7606 7607 u8 reserved_3[0x10]; 7608 u8 vxlan_udp_port[0x10]; 7609 }; 7610 7611 struct mlx5_ifc_activate_tracer_out_bits { 7612 u8 status[0x8]; 7613 u8 reserved_0[0x18]; 7614 7615 u8 syndrome[0x20]; 7616 7617 u8 reserved_1[0x40]; 7618 }; 7619 7620 struct mlx5_ifc_activate_tracer_in_bits { 7621 u8 opcode[0x10]; 7622 u8 reserved_0[0x10]; 7623 7624 u8 reserved_1[0x10]; 7625 u8 op_mod[0x10]; 7626 7627 u8 mkey[0x20]; 7628 7629 u8 reserved_2[0x20]; 7630 }; 7631 7632 struct mlx5_ifc_set_rate_limit_out_bits { 7633 u8 status[0x8]; 7634 u8 reserved_at_8[0x18]; 7635 7636 u8 syndrome[0x20]; 7637 7638 u8 reserved_at_40[0x40]; 7639 }; 7640 7641 struct mlx5_ifc_set_rate_limit_in_bits { 7642 u8 opcode[0x10]; 7643 u8 reserved_at_10[0x10]; 7644 7645 u8 reserved_at_20[0x10]; 7646 u8 op_mod[0x10]; 7647 7648 u8 reserved_at_40[0x10]; 7649 u8 rate_limit_index[0x10]; 7650 7651 u8 reserved_at_60[0x20]; 7652 7653 u8 rate_limit[0x20]; 7654 u8 burst_upper_bound[0x20]; 7655 }; 7656 7657 struct mlx5_ifc_access_register_out_bits { 7658 u8 status[0x8]; 7659 u8 reserved_0[0x18]; 7660 7661 u8 syndrome[0x20]; 7662 7663 u8 reserved_1[0x40]; 7664 7665 u8 register_data[0][0x20]; 7666 }; 7667 7668 enum { 7669 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 7670 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 7671 }; 7672 7673 struct mlx5_ifc_access_register_in_bits { 7674 u8 opcode[0x10]; 7675 u8 reserved_0[0x10]; 7676 7677 u8 reserved_1[0x10]; 7678 u8 op_mod[0x10]; 7679 7680 u8 reserved_2[0x10]; 7681 u8 register_id[0x10]; 7682 7683 u8 argument[0x20]; 7684 7685 u8 register_data[0][0x20]; 7686 }; 7687 7688 struct mlx5_ifc_sltp_reg_bits { 7689 u8 status[0x4]; 7690 u8 version[0x4]; 7691 u8 local_port[0x8]; 7692 u8 pnat[0x2]; 7693 u8 reserved_0[0x2]; 7694 u8 lane[0x4]; 7695 u8 reserved_1[0x8]; 7696 7697 u8 reserved_2[0x20]; 7698 7699 u8 reserved_3[0x7]; 7700 u8 polarity[0x1]; 7701 u8 ob_tap0[0x8]; 7702 u8 ob_tap1[0x8]; 7703 u8 ob_tap2[0x8]; 7704 7705 u8 reserved_4[0xc]; 7706 u8 ob_preemp_mode[0x4]; 7707 u8 ob_reg[0x8]; 7708 u8 ob_bias[0x8]; 7709 7710 u8 reserved_5[0x20]; 7711 }; 7712 7713 struct mlx5_ifc_slrp_reg_bits { 7714 u8 status[0x4]; 7715 u8 version[0x4]; 7716 u8 local_port[0x8]; 7717 u8 pnat[0x2]; 7718 u8 reserved_0[0x2]; 7719 u8 lane[0x4]; 7720 u8 reserved_1[0x8]; 7721 7722 u8 ib_sel[0x2]; 7723 u8 reserved_2[0x11]; 7724 u8 dp_sel[0x1]; 7725 u8 dp90sel[0x4]; 7726 u8 mix90phase[0x8]; 7727 7728 u8 ffe_tap0[0x8]; 7729 u8 ffe_tap1[0x8]; 7730 u8 ffe_tap2[0x8]; 7731 u8 ffe_tap3[0x8]; 7732 7733 u8 ffe_tap4[0x8]; 7734 u8 ffe_tap5[0x8]; 7735 u8 ffe_tap6[0x8]; 7736 u8 ffe_tap7[0x8]; 7737 7738 u8 ffe_tap8[0x8]; 7739 u8 mixerbias_tap_amp[0x8]; 7740 u8 reserved_3[0x7]; 7741 u8 ffe_tap_en[0x9]; 7742 7743 u8 ffe_tap_offset0[0x8]; 7744 u8 ffe_tap_offset1[0x8]; 7745 u8 slicer_offset0[0x10]; 7746 7747 u8 mixer_offset0[0x10]; 7748 u8 mixer_offset1[0x10]; 7749 7750 u8 mixerbgn_inp[0x8]; 7751 u8 mixerbgn_inn[0x8]; 7752 u8 mixerbgn_refp[0x8]; 7753 u8 mixerbgn_refn[0x8]; 7754 7755 u8 sel_slicer_lctrl_h[0x1]; 7756 u8 sel_slicer_lctrl_l[0x1]; 7757 u8 reserved_4[0x1]; 7758 u8 ref_mixer_vreg[0x5]; 7759 u8 slicer_gctrl[0x8]; 7760 u8 lctrl_input[0x8]; 7761 u8 mixer_offset_cm1[0x8]; 7762 7763 u8 common_mode[0x6]; 7764 u8 reserved_5[0x1]; 7765 u8 mixer_offset_cm0[0x9]; 7766 u8 reserved_6[0x7]; 7767 u8 slicer_offset_cm[0x9]; 7768 }; 7769 7770 struct mlx5_ifc_slrg_reg_bits { 7771 u8 status[0x4]; 7772 u8 version[0x4]; 7773 u8 local_port[0x8]; 7774 u8 pnat[0x2]; 7775 u8 reserved_0[0x2]; 7776 u8 lane[0x4]; 7777 u8 reserved_1[0x8]; 7778 7779 u8 time_to_link_up[0x10]; 7780 u8 reserved_2[0xc]; 7781 u8 grade_lane_speed[0x4]; 7782 7783 u8 grade_version[0x8]; 7784 u8 grade[0x18]; 7785 7786 u8 reserved_3[0x4]; 7787 u8 height_grade_type[0x4]; 7788 u8 height_grade[0x18]; 7789 7790 u8 height_dz[0x10]; 7791 u8 height_dv[0x10]; 7792 7793 u8 reserved_4[0x10]; 7794 u8 height_sigma[0x10]; 7795 7796 u8 reserved_5[0x20]; 7797 7798 u8 reserved_6[0x4]; 7799 u8 phase_grade_type[0x4]; 7800 u8 phase_grade[0x18]; 7801 7802 u8 reserved_7[0x8]; 7803 u8 phase_eo_pos[0x8]; 7804 u8 reserved_8[0x8]; 7805 u8 phase_eo_neg[0x8]; 7806 7807 u8 ffe_set_tested[0x10]; 7808 u8 test_errors_per_lane[0x10]; 7809 }; 7810 7811 struct mlx5_ifc_pvlc_reg_bits { 7812 u8 reserved_0[0x8]; 7813 u8 local_port[0x8]; 7814 u8 reserved_1[0x10]; 7815 7816 u8 reserved_2[0x1c]; 7817 u8 vl_hw_cap[0x4]; 7818 7819 u8 reserved_3[0x1c]; 7820 u8 vl_admin[0x4]; 7821 7822 u8 reserved_4[0x1c]; 7823 u8 vl_operational[0x4]; 7824 }; 7825 7826 struct mlx5_ifc_pude_reg_bits { 7827 u8 swid[0x8]; 7828 u8 local_port[0x8]; 7829 u8 reserved_0[0x4]; 7830 u8 admin_status[0x4]; 7831 u8 reserved_1[0x4]; 7832 u8 oper_status[0x4]; 7833 7834 u8 reserved_2[0x60]; 7835 }; 7836 7837 enum { 7838 MLX5_PTYS_REG_PROTO_MASK_INFINIBAND = 0x1, 7839 MLX5_PTYS_REG_PROTO_MASK_ETHERNET = 0x4, 7840 }; 7841 7842 struct mlx5_ifc_ptys_reg_bits { 7843 u8 reserved_0[0x1]; 7844 u8 an_disable_admin[0x1]; 7845 u8 an_disable_cap[0x1]; 7846 u8 reserved_1[0x4]; 7847 u8 force_tx_aba_param[0x1]; 7848 u8 local_port[0x8]; 7849 u8 reserved_2[0xd]; 7850 u8 proto_mask[0x3]; 7851 7852 u8 an_status[0x4]; 7853 u8 reserved_3[0xc]; 7854 u8 data_rate_oper[0x10]; 7855 7856 u8 ext_eth_proto_capability[0x20]; 7857 7858 u8 eth_proto_capability[0x20]; 7859 7860 u8 ib_link_width_capability[0x10]; 7861 u8 ib_proto_capability[0x10]; 7862 7863 u8 ext_eth_proto_admin[0x20]; 7864 7865 u8 eth_proto_admin[0x20]; 7866 7867 u8 ib_link_width_admin[0x10]; 7868 u8 ib_proto_admin[0x10]; 7869 7870 u8 ext_eth_proto_oper[0x20]; 7871 7872 u8 eth_proto_oper[0x20]; 7873 7874 u8 ib_link_width_oper[0x10]; 7875 u8 ib_proto_oper[0x10]; 7876 7877 u8 reserved_4[0x1c]; 7878 u8 connector_type[0x4]; 7879 7880 u8 eth_proto_lp_advertise[0x20]; 7881 7882 u8 reserved_5[0x60]; 7883 }; 7884 7885 struct mlx5_ifc_ptas_reg_bits { 7886 u8 reserved_0[0x20]; 7887 7888 u8 algorithm_options[0x10]; 7889 u8 reserved_1[0x4]; 7890 u8 repetitions_mode[0x4]; 7891 u8 num_of_repetitions[0x8]; 7892 7893 u8 grade_version[0x8]; 7894 u8 height_grade_type[0x4]; 7895 u8 phase_grade_type[0x4]; 7896 u8 height_grade_weight[0x8]; 7897 u8 phase_grade_weight[0x8]; 7898 7899 u8 gisim_measure_bits[0x10]; 7900 u8 adaptive_tap_measure_bits[0x10]; 7901 7902 u8 ber_bath_high_error_threshold[0x10]; 7903 u8 ber_bath_mid_error_threshold[0x10]; 7904 7905 u8 ber_bath_low_error_threshold[0x10]; 7906 u8 one_ratio_high_threshold[0x10]; 7907 7908 u8 one_ratio_high_mid_threshold[0x10]; 7909 u8 one_ratio_low_mid_threshold[0x10]; 7910 7911 u8 one_ratio_low_threshold[0x10]; 7912 u8 ndeo_error_threshold[0x10]; 7913 7914 u8 mixer_offset_step_size[0x10]; 7915 u8 reserved_2[0x8]; 7916 u8 mix90_phase_for_voltage_bath[0x8]; 7917 7918 u8 mixer_offset_start[0x10]; 7919 u8 mixer_offset_end[0x10]; 7920 7921 u8 reserved_3[0x15]; 7922 u8 ber_test_time[0xb]; 7923 }; 7924 7925 struct mlx5_ifc_pspa_reg_bits { 7926 u8 swid[0x8]; 7927 u8 local_port[0x8]; 7928 u8 sub_port[0x8]; 7929 u8 reserved_0[0x8]; 7930 7931 u8 reserved_1[0x20]; 7932 }; 7933 7934 struct mlx5_ifc_ppsc_reg_bits { 7935 u8 reserved_0[0x8]; 7936 u8 local_port[0x8]; 7937 u8 reserved_1[0x10]; 7938 7939 u8 reserved_2[0x60]; 7940 7941 u8 reserved_3[0x1c]; 7942 u8 wrps_admin[0x4]; 7943 7944 u8 reserved_4[0x1c]; 7945 u8 wrps_status[0x4]; 7946 7947 u8 up_th_vld[0x1]; 7948 u8 down_th_vld[0x1]; 7949 u8 reserved_5[0x6]; 7950 u8 up_threshold[0x8]; 7951 u8 reserved_6[0x8]; 7952 u8 down_threshold[0x8]; 7953 7954 u8 reserved_7[0x20]; 7955 7956 u8 reserved_8[0x1c]; 7957 u8 srps_admin[0x4]; 7958 7959 u8 reserved_9[0x60]; 7960 }; 7961 7962 struct mlx5_ifc_pplr_reg_bits { 7963 u8 reserved_0[0x8]; 7964 u8 local_port[0x8]; 7965 u8 reserved_1[0x10]; 7966 7967 u8 reserved_2[0x8]; 7968 u8 lb_cap[0x8]; 7969 u8 reserved_3[0x8]; 7970 u8 lb_en[0x8]; 7971 }; 7972 7973 struct mlx5_ifc_pplm_reg_bits { 7974 u8 reserved_at_0[0x8]; 7975 u8 local_port[0x8]; 7976 u8 reserved_at_10[0x10]; 7977 7978 u8 reserved_at_20[0x20]; 7979 7980 u8 port_profile_mode[0x8]; 7981 u8 static_port_profile[0x8]; 7982 u8 active_port_profile[0x8]; 7983 u8 reserved_at_58[0x8]; 7984 7985 u8 retransmission_active[0x8]; 7986 u8 fec_mode_active[0x18]; 7987 7988 u8 rs_fec_correction_bypass_cap[0x4]; 7989 u8 reserved_at_84[0x8]; 7990 u8 fec_override_cap_56g[0x4]; 7991 u8 fec_override_cap_100g[0x4]; 7992 u8 fec_override_cap_50g[0x4]; 7993 u8 fec_override_cap_25g[0x4]; 7994 u8 fec_override_cap_10g_40g[0x4]; 7995 7996 u8 rs_fec_correction_bypass_admin[0x4]; 7997 u8 reserved_at_a4[0x8]; 7998 u8 fec_override_admin_56g[0x4]; 7999 u8 fec_override_admin_100g[0x4]; 8000 u8 fec_override_admin_50g[0x4]; 8001 u8 fec_override_admin_25g[0x4]; 8002 u8 fec_override_admin_10g_40g[0x4]; 8003 8004 u8 fec_override_cap_400g_8x[0x10]; 8005 u8 fec_override_cap_200g_4x[0x10]; 8006 u8 fec_override_cap_100g_2x[0x10]; 8007 u8 fec_override_cap_50g_1x[0x10]; 8008 8009 u8 fec_override_admin_400g_8x[0x10]; 8010 u8 fec_override_admin_200g_4x[0x10]; 8011 u8 fec_override_admin_100g_2x[0x10]; 8012 u8 fec_override_admin_50g_1x[0x10]; 8013 8014 u8 reserved_at_140[0xC0]; 8015 }; 8016 8017 struct mlx5_ifc_ppll_reg_bits { 8018 u8 num_pll_groups[0x8]; 8019 u8 pll_group[0x8]; 8020 u8 reserved_0[0x4]; 8021 u8 num_plls[0x4]; 8022 u8 reserved_1[0x8]; 8023 8024 u8 reserved_2[0x1f]; 8025 u8 ae[0x1]; 8026 8027 u8 pll_status[4][0x40]; 8028 }; 8029 8030 struct mlx5_ifc_ppad_reg_bits { 8031 u8 reserved_0[0x3]; 8032 u8 single_mac[0x1]; 8033 u8 reserved_1[0x4]; 8034 u8 local_port[0x8]; 8035 u8 mac_47_32[0x10]; 8036 8037 u8 mac_31_0[0x20]; 8038 8039 u8 reserved_2[0x40]; 8040 }; 8041 8042 struct mlx5_ifc_pmtu_reg_bits { 8043 u8 reserved_0[0x8]; 8044 u8 local_port[0x8]; 8045 u8 reserved_1[0x10]; 8046 8047 u8 max_mtu[0x10]; 8048 u8 reserved_2[0x10]; 8049 8050 u8 admin_mtu[0x10]; 8051 u8 reserved_3[0x10]; 8052 8053 u8 oper_mtu[0x10]; 8054 u8 reserved_4[0x10]; 8055 }; 8056 8057 struct mlx5_ifc_pmpr_reg_bits { 8058 u8 reserved_0[0x8]; 8059 u8 module[0x8]; 8060 u8 reserved_1[0x10]; 8061 8062 u8 reserved_2[0x18]; 8063 u8 attenuation_5g[0x8]; 8064 8065 u8 reserved_3[0x18]; 8066 u8 attenuation_7g[0x8]; 8067 8068 u8 reserved_4[0x18]; 8069 u8 attenuation_12g[0x8]; 8070 }; 8071 8072 struct mlx5_ifc_pmpe_reg_bits { 8073 u8 reserved_0[0x8]; 8074 u8 module[0x8]; 8075 u8 reserved_1[0xc]; 8076 u8 module_status[0x4]; 8077 8078 u8 reserved_2[0x14]; 8079 u8 error_type[0x4]; 8080 u8 reserved_3[0x8]; 8081 8082 u8 reserved_4[0x40]; 8083 }; 8084 8085 struct mlx5_ifc_pmpc_reg_bits { 8086 u8 module_state_updated[32][0x8]; 8087 }; 8088 8089 struct mlx5_ifc_pmlpn_reg_bits { 8090 u8 reserved_0[0x4]; 8091 u8 mlpn_status[0x4]; 8092 u8 local_port[0x8]; 8093 u8 reserved_1[0x10]; 8094 8095 u8 e[0x1]; 8096 u8 reserved_2[0x1f]; 8097 }; 8098 8099 struct mlx5_ifc_pmlp_reg_bits { 8100 u8 rxtx[0x1]; 8101 u8 reserved_0[0x7]; 8102 u8 local_port[0x8]; 8103 u8 reserved_1[0x8]; 8104 u8 width[0x8]; 8105 8106 u8 lane0_module_mapping[0x20]; 8107 8108 u8 lane1_module_mapping[0x20]; 8109 8110 u8 lane2_module_mapping[0x20]; 8111 8112 u8 lane3_module_mapping[0x20]; 8113 8114 u8 reserved_2[0x160]; 8115 }; 8116 8117 struct mlx5_ifc_pmaos_reg_bits { 8118 u8 reserved_0[0x8]; 8119 u8 module[0x8]; 8120 u8 reserved_1[0x4]; 8121 u8 admin_status[0x4]; 8122 u8 reserved_2[0x4]; 8123 u8 oper_status[0x4]; 8124 8125 u8 ase[0x1]; 8126 u8 ee[0x1]; 8127 u8 reserved_3[0x12]; 8128 u8 error_type[0x4]; 8129 u8 reserved_4[0x6]; 8130 u8 e[0x2]; 8131 8132 u8 reserved_5[0x40]; 8133 }; 8134 8135 struct mlx5_ifc_plpc_reg_bits { 8136 u8 reserved_0[0x4]; 8137 u8 profile_id[0xc]; 8138 u8 reserved_1[0x4]; 8139 u8 proto_mask[0x4]; 8140 u8 reserved_2[0x8]; 8141 8142 u8 reserved_3[0x10]; 8143 u8 lane_speed[0x10]; 8144 8145 u8 reserved_4[0x17]; 8146 u8 lpbf[0x1]; 8147 u8 fec_mode_policy[0x8]; 8148 8149 u8 retransmission_capability[0x8]; 8150 u8 fec_mode_capability[0x18]; 8151 8152 u8 retransmission_support_admin[0x8]; 8153 u8 fec_mode_support_admin[0x18]; 8154 8155 u8 retransmission_request_admin[0x8]; 8156 u8 fec_mode_request_admin[0x18]; 8157 8158 u8 reserved_5[0x80]; 8159 }; 8160 8161 struct mlx5_ifc_pll_status_data_bits { 8162 u8 reserved_0[0x1]; 8163 u8 lock_cal[0x1]; 8164 u8 lock_status[0x2]; 8165 u8 reserved_1[0x2]; 8166 u8 algo_f_ctrl[0xa]; 8167 u8 analog_algo_num_var[0x6]; 8168 u8 f_ctrl_measure[0xa]; 8169 8170 u8 reserved_2[0x2]; 8171 u8 analog_var[0x6]; 8172 u8 reserved_3[0x2]; 8173 u8 high_var[0x6]; 8174 u8 reserved_4[0x2]; 8175 u8 low_var[0x6]; 8176 u8 reserved_5[0x2]; 8177 u8 mid_val[0x6]; 8178 }; 8179 8180 struct mlx5_ifc_plib_reg_bits { 8181 u8 reserved_0[0x8]; 8182 u8 local_port[0x8]; 8183 u8 reserved_1[0x8]; 8184 u8 ib_port[0x8]; 8185 8186 u8 reserved_2[0x60]; 8187 }; 8188 8189 struct mlx5_ifc_plbf_reg_bits { 8190 u8 reserved_0[0x8]; 8191 u8 local_port[0x8]; 8192 u8 reserved_1[0xd]; 8193 u8 lbf_mode[0x3]; 8194 8195 u8 reserved_2[0x20]; 8196 }; 8197 8198 struct mlx5_ifc_pipg_reg_bits { 8199 u8 reserved_0[0x8]; 8200 u8 local_port[0x8]; 8201 u8 reserved_1[0x10]; 8202 8203 u8 dic[0x1]; 8204 u8 reserved_2[0x19]; 8205 u8 ipg[0x4]; 8206 u8 reserved_3[0x2]; 8207 }; 8208 8209 struct mlx5_ifc_pifr_reg_bits { 8210 u8 reserved_0[0x8]; 8211 u8 local_port[0x8]; 8212 u8 reserved_1[0x10]; 8213 8214 u8 reserved_2[0xe0]; 8215 8216 u8 port_filter[8][0x20]; 8217 8218 u8 port_filter_update_en[8][0x20]; 8219 }; 8220 8221 struct mlx5_ifc_phys_layer_cntrs_bits { 8222 u8 time_since_last_clear_high[0x20]; 8223 8224 u8 time_since_last_clear_low[0x20]; 8225 8226 u8 symbol_errors_high[0x20]; 8227 8228 u8 symbol_errors_low[0x20]; 8229 8230 u8 sync_headers_errors_high[0x20]; 8231 8232 u8 sync_headers_errors_low[0x20]; 8233 8234 u8 edpl_bip_errors_lane0_high[0x20]; 8235 8236 u8 edpl_bip_errors_lane0_low[0x20]; 8237 8238 u8 edpl_bip_errors_lane1_high[0x20]; 8239 8240 u8 edpl_bip_errors_lane1_low[0x20]; 8241 8242 u8 edpl_bip_errors_lane2_high[0x20]; 8243 8244 u8 edpl_bip_errors_lane2_low[0x20]; 8245 8246 u8 edpl_bip_errors_lane3_high[0x20]; 8247 8248 u8 edpl_bip_errors_lane3_low[0x20]; 8249 8250 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 8251 8252 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 8253 8254 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 8255 8256 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 8257 8258 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 8259 8260 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 8261 8262 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 8263 8264 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 8265 8266 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 8267 8268 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 8269 8270 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 8271 8272 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 8273 8274 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 8275 8276 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 8277 8278 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 8279 8280 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 8281 8282 u8 rs_fec_corrected_blocks_high[0x20]; 8283 8284 u8 rs_fec_corrected_blocks_low[0x20]; 8285 8286 u8 rs_fec_uncorrectable_blocks_high[0x20]; 8287 8288 u8 rs_fec_uncorrectable_blocks_low[0x20]; 8289 8290 u8 rs_fec_no_errors_blocks_high[0x20]; 8291 8292 u8 rs_fec_no_errors_blocks_low[0x20]; 8293 8294 u8 rs_fec_single_error_blocks_high[0x20]; 8295 8296 u8 rs_fec_single_error_blocks_low[0x20]; 8297 8298 u8 rs_fec_corrected_symbols_total_high[0x20]; 8299 8300 u8 rs_fec_corrected_symbols_total_low[0x20]; 8301 8302 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 8303 8304 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 8305 8306 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 8307 8308 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 8309 8310 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 8311 8312 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 8313 8314 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 8315 8316 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 8317 8318 u8 link_down_events[0x20]; 8319 8320 u8 successful_recovery_events[0x20]; 8321 8322 u8 reserved_0[0x180]; 8323 }; 8324 8325 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 8326 u8 symbol_error_counter[0x10]; 8327 8328 u8 link_error_recovery_counter[0x8]; 8329 8330 u8 link_downed_counter[0x8]; 8331 8332 u8 port_rcv_errors[0x10]; 8333 8334 u8 port_rcv_remote_physical_errors[0x10]; 8335 8336 u8 port_rcv_switch_relay_errors[0x10]; 8337 8338 u8 port_xmit_discards[0x10]; 8339 8340 u8 port_xmit_constraint_errors[0x8]; 8341 8342 u8 port_rcv_constraint_errors[0x8]; 8343 8344 u8 reserved_at_70[0x8]; 8345 8346 u8 link_overrun_errors[0x8]; 8347 8348 u8 reserved_at_80[0x10]; 8349 8350 u8 vl_15_dropped[0x10]; 8351 8352 u8 reserved_at_a0[0xa0]; 8353 }; 8354 8355 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 8356 u8 time_since_last_clear_high[0x20]; 8357 8358 u8 time_since_last_clear_low[0x20]; 8359 8360 u8 phy_received_bits_high[0x20]; 8361 8362 u8 phy_received_bits_low[0x20]; 8363 8364 u8 phy_symbol_errors_high[0x20]; 8365 8366 u8 phy_symbol_errors_low[0x20]; 8367 8368 u8 phy_corrected_bits_high[0x20]; 8369 8370 u8 phy_corrected_bits_low[0x20]; 8371 8372 u8 phy_corrected_bits_lane0_high[0x20]; 8373 8374 u8 phy_corrected_bits_lane0_low[0x20]; 8375 8376 u8 phy_corrected_bits_lane1_high[0x20]; 8377 8378 u8 phy_corrected_bits_lane1_low[0x20]; 8379 8380 u8 phy_corrected_bits_lane2_high[0x20]; 8381 8382 u8 phy_corrected_bits_lane2_low[0x20]; 8383 8384 u8 phy_corrected_bits_lane3_high[0x20]; 8385 8386 u8 phy_corrected_bits_lane3_low[0x20]; 8387 8388 u8 reserved_at_200[0x5c0]; 8389 }; 8390 8391 struct mlx5_ifc_infiniband_port_cntrs_bits { 8392 u8 symbol_error_counter[0x10]; 8393 u8 link_error_recovery_counter[0x8]; 8394 u8 link_downed_counter[0x8]; 8395 8396 u8 port_rcv_errors[0x10]; 8397 u8 port_rcv_remote_physical_errors[0x10]; 8398 8399 u8 port_rcv_switch_relay_errors[0x10]; 8400 u8 port_xmit_discards[0x10]; 8401 8402 u8 port_xmit_constraint_errors[0x8]; 8403 u8 port_rcv_constraint_errors[0x8]; 8404 u8 reserved_0[0x8]; 8405 u8 local_link_integrity_errors[0x4]; 8406 u8 excessive_buffer_overrun_errors[0x4]; 8407 8408 u8 reserved_1[0x10]; 8409 u8 vl_15_dropped[0x10]; 8410 8411 u8 port_xmit_data[0x20]; 8412 8413 u8 port_rcv_data[0x20]; 8414 8415 u8 port_xmit_pkts[0x20]; 8416 8417 u8 port_rcv_pkts[0x20]; 8418 8419 u8 port_xmit_wait[0x20]; 8420 8421 u8 reserved_2[0x680]; 8422 }; 8423 8424 struct mlx5_ifc_phrr_reg_bits { 8425 u8 clr[0x1]; 8426 u8 reserved_0[0x7]; 8427 u8 local_port[0x8]; 8428 u8 reserved_1[0x10]; 8429 8430 u8 hist_group[0x8]; 8431 u8 reserved_2[0x10]; 8432 u8 hist_id[0x8]; 8433 8434 u8 reserved_3[0x40]; 8435 8436 u8 time_since_last_clear_high[0x20]; 8437 8438 u8 time_since_last_clear_low[0x20]; 8439 8440 u8 bin[10][0x20]; 8441 }; 8442 8443 struct mlx5_ifc_phbr_for_prio_reg_bits { 8444 u8 reserved_0[0x18]; 8445 u8 prio[0x8]; 8446 }; 8447 8448 struct mlx5_ifc_phbr_for_port_tclass_reg_bits { 8449 u8 reserved_0[0x18]; 8450 u8 tclass[0x8]; 8451 }; 8452 8453 struct mlx5_ifc_phbr_binding_reg_bits { 8454 u8 opcode[0x4]; 8455 u8 reserved_0[0x4]; 8456 u8 local_port[0x8]; 8457 u8 pnat[0x2]; 8458 u8 reserved_1[0xe]; 8459 8460 u8 hist_group[0x8]; 8461 u8 reserved_2[0x10]; 8462 u8 hist_id[0x8]; 8463 8464 u8 reserved_3[0x10]; 8465 u8 hist_type[0x10]; 8466 8467 u8 hist_parameters[0x20]; 8468 8469 u8 hist_min_value[0x20]; 8470 8471 u8 hist_max_value[0x20]; 8472 8473 u8 sample_time[0x20]; 8474 }; 8475 8476 enum { 8477 MLX5_PFCC_REG_PPAN_DISABLED = 0x0, 8478 MLX5_PFCC_REG_PPAN_ENABLED = 0x1, 8479 }; 8480 8481 struct mlx5_ifc_pfcc_reg_bits { 8482 u8 dcbx_operation_type[0x2]; 8483 u8 cap_local_admin[0x1]; 8484 u8 cap_remote_admin[0x1]; 8485 u8 reserved_0[0x4]; 8486 u8 local_port[0x8]; 8487 u8 pnat[0x2]; 8488 u8 reserved_1[0xc]; 8489 u8 shl_cap[0x1]; 8490 u8 shl_opr[0x1]; 8491 8492 u8 ppan[0x4]; 8493 u8 reserved_2[0x4]; 8494 u8 prio_mask_tx[0x8]; 8495 u8 reserved_3[0x8]; 8496 u8 prio_mask_rx[0x8]; 8497 8498 u8 pptx[0x1]; 8499 u8 aptx[0x1]; 8500 u8 reserved_4[0x6]; 8501 u8 pfctx[0x8]; 8502 u8 reserved_5[0x8]; 8503 u8 cbftx[0x8]; 8504 8505 u8 pprx[0x1]; 8506 u8 aprx[0x1]; 8507 u8 reserved_6[0x6]; 8508 u8 pfcrx[0x8]; 8509 u8 reserved_7[0x8]; 8510 u8 cbfrx[0x8]; 8511 8512 u8 device_stall_minor_watermark[0x10]; 8513 u8 device_stall_critical_watermark[0x10]; 8514 8515 u8 reserved_8[0x60]; 8516 }; 8517 8518 struct mlx5_ifc_pelc_reg_bits { 8519 u8 op[0x4]; 8520 u8 reserved_0[0x4]; 8521 u8 local_port[0x8]; 8522 u8 reserved_1[0x10]; 8523 8524 u8 op_admin[0x8]; 8525 u8 op_capability[0x8]; 8526 u8 op_request[0x8]; 8527 u8 op_active[0x8]; 8528 8529 u8 admin[0x40]; 8530 8531 u8 capability[0x40]; 8532 8533 u8 request[0x40]; 8534 8535 u8 active[0x40]; 8536 8537 u8 reserved_2[0x80]; 8538 }; 8539 8540 struct mlx5_ifc_peir_reg_bits { 8541 u8 reserved_0[0x8]; 8542 u8 local_port[0x8]; 8543 u8 reserved_1[0x10]; 8544 8545 u8 reserved_2[0xc]; 8546 u8 error_count[0x4]; 8547 u8 reserved_3[0x10]; 8548 8549 u8 reserved_4[0xc]; 8550 u8 lane[0x4]; 8551 u8 reserved_5[0x8]; 8552 u8 error_type[0x8]; 8553 }; 8554 8555 struct mlx5_ifc_qcam_access_reg_cap_mask { 8556 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 8557 u8 qpdpm[0x1]; 8558 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 8559 u8 qdpm[0x1]; 8560 u8 qpts[0x1]; 8561 u8 qcap[0x1]; 8562 u8 qcam_access_reg_cap_mask_0[0x1]; 8563 }; 8564 8565 struct mlx5_ifc_qcam_qos_feature_cap_mask { 8566 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 8567 u8 qpts_trust_both[0x1]; 8568 }; 8569 8570 struct mlx5_ifc_qcam_reg_bits { 8571 u8 reserved_at_0[0x8]; 8572 u8 feature_group[0x8]; 8573 u8 reserved_at_10[0x8]; 8574 u8 access_reg_group[0x8]; 8575 u8 reserved_at_20[0x20]; 8576 8577 union { 8578 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 8579 u8 reserved_at_0[0x80]; 8580 } qos_access_reg_cap_mask; 8581 8582 u8 reserved_at_c0[0x80]; 8583 8584 union { 8585 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 8586 u8 reserved_at_0[0x80]; 8587 } qos_feature_cap_mask; 8588 8589 u8 reserved_at_1c0[0x80]; 8590 }; 8591 8592 struct mlx5_ifc_pcam_enhanced_features_bits { 8593 u8 reserved_at_0[0x6d]; 8594 u8 rx_icrc_encapsulated_counter[0x1]; 8595 u8 reserved_at_6e[0x4]; 8596 u8 ptys_extended_ethernet[0x1]; 8597 u8 reserved_at_73[0x3]; 8598 u8 pfcc_mask[0x1]; 8599 u8 reserved_at_77[0x3]; 8600 u8 per_lane_error_counters[0x1]; 8601 u8 rx_buffer_fullness_counters[0x1]; 8602 u8 ptys_connector_type[0x1]; 8603 u8 reserved_at_7d[0x1]; 8604 u8 ppcnt_discard_group[0x1]; 8605 u8 ppcnt_statistical_group[0x1]; 8606 }; 8607 8608 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 8609 u8 port_access_reg_cap_mask_127_to_96[0x20]; 8610 u8 port_access_reg_cap_mask_95_to_64[0x20]; 8611 8612 u8 reserved_at_40[0xe]; 8613 u8 pddr[0x1]; 8614 u8 reserved_at_4f[0xd]; 8615 8616 u8 pplm[0x1]; 8617 u8 port_access_reg_cap_mask_34_to_32[0x3]; 8618 8619 u8 port_access_reg_cap_mask_31_to_13[0x13]; 8620 u8 pbmc[0x1]; 8621 u8 pptb[0x1]; 8622 u8 port_access_reg_cap_mask_10_to_09[0x2]; 8623 u8 ppcnt[0x1]; 8624 u8 port_access_reg_cap_mask_07_to_00[0x8]; 8625 }; 8626 8627 struct mlx5_ifc_pcam_reg_bits { 8628 u8 reserved_at_0[0x8]; 8629 u8 feature_group[0x8]; 8630 u8 reserved_at_10[0x8]; 8631 u8 access_reg_group[0x8]; 8632 8633 u8 reserved_at_20[0x20]; 8634 8635 union { 8636 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 8637 u8 reserved_at_0[0x80]; 8638 } port_access_reg_cap_mask; 8639 8640 u8 reserved_at_c0[0x80]; 8641 8642 union { 8643 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 8644 u8 reserved_at_0[0x80]; 8645 } feature_cap_mask; 8646 8647 u8 reserved_at_1c0[0xc0]; 8648 }; 8649 8650 struct mlx5_ifc_mcam_enhanced_features_bits { 8651 u8 reserved_at_0[0x6e]; 8652 u8 pcie_status_and_power[0x1]; 8653 u8 reserved_at_111[0x10]; 8654 u8 pcie_performance_group[0x1]; 8655 }; 8656 8657 struct mlx5_ifc_mcam_access_reg_bits { 8658 u8 reserved_at_0[0x1c]; 8659 u8 mcda[0x1]; 8660 u8 mcc[0x1]; 8661 u8 mcqi[0x1]; 8662 u8 reserved_at_1f[0x1]; 8663 8664 u8 regs_95_to_64[0x20]; 8665 u8 regs_63_to_32[0x20]; 8666 u8 regs_31_to_0[0x20]; 8667 }; 8668 8669 struct mlx5_ifc_mcam_reg_bits { 8670 u8 reserved_at_0[0x8]; 8671 u8 feature_group[0x8]; 8672 u8 reserved_at_10[0x8]; 8673 u8 access_reg_group[0x8]; 8674 8675 u8 reserved_at_20[0x20]; 8676 8677 union { 8678 struct mlx5_ifc_mcam_access_reg_bits access_regs; 8679 u8 reserved_at_0[0x80]; 8680 } mng_access_reg_cap_mask; 8681 8682 u8 reserved_at_c0[0x80]; 8683 8684 union { 8685 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 8686 u8 reserved_at_0[0x80]; 8687 } mng_feature_cap_mask; 8688 8689 u8 reserved_at_1c0[0x80]; 8690 }; 8691 8692 struct mlx5_ifc_pcap_reg_bits { 8693 u8 reserved_0[0x8]; 8694 u8 local_port[0x8]; 8695 u8 reserved_1[0x10]; 8696 8697 u8 port_capability_mask[4][0x20]; 8698 }; 8699 8700 struct mlx5_ifc_pbmc_reg_bits { 8701 u8 reserved_at_0[0x8]; 8702 u8 local_port[0x8]; 8703 u8 reserved_at_10[0x10]; 8704 8705 u8 xoff_timer_value[0x10]; 8706 u8 xoff_refresh[0x10]; 8707 8708 u8 reserved_at_40[0x9]; 8709 u8 fullness_threshold[0x7]; 8710 u8 port_buffer_size[0x10]; 8711 8712 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 8713 8714 u8 reserved_at_2e0[0x40]; 8715 }; 8716 8717 struct mlx5_ifc_paos_reg_bits { 8718 u8 swid[0x8]; 8719 u8 local_port[0x8]; 8720 u8 reserved_0[0x4]; 8721 u8 admin_status[0x4]; 8722 u8 reserved_1[0x4]; 8723 u8 oper_status[0x4]; 8724 8725 u8 ase[0x1]; 8726 u8 ee[0x1]; 8727 u8 reserved_2[0x1c]; 8728 u8 e[0x2]; 8729 8730 u8 reserved_3[0x40]; 8731 }; 8732 8733 struct mlx5_ifc_pamp_reg_bits { 8734 u8 reserved_0[0x8]; 8735 u8 opamp_group[0x8]; 8736 u8 reserved_1[0xc]; 8737 u8 opamp_group_type[0x4]; 8738 8739 u8 start_index[0x10]; 8740 u8 reserved_2[0x4]; 8741 u8 num_of_indices[0xc]; 8742 8743 u8 index_data[18][0x10]; 8744 }; 8745 8746 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits { 8747 u8 llr_rx_cells_high[0x20]; 8748 8749 u8 llr_rx_cells_low[0x20]; 8750 8751 u8 llr_rx_error_high[0x20]; 8752 8753 u8 llr_rx_error_low[0x20]; 8754 8755 u8 llr_rx_crc_error_high[0x20]; 8756 8757 u8 llr_rx_crc_error_low[0x20]; 8758 8759 u8 llr_tx_cells_high[0x20]; 8760 8761 u8 llr_tx_cells_low[0x20]; 8762 8763 u8 llr_tx_ret_cells_high[0x20]; 8764 8765 u8 llr_tx_ret_cells_low[0x20]; 8766 8767 u8 llr_tx_ret_events_high[0x20]; 8768 8769 u8 llr_tx_ret_events_low[0x20]; 8770 8771 u8 reserved_0[0x640]; 8772 }; 8773 8774 struct mlx5_ifc_mtmp_reg_bits { 8775 u8 i[0x1]; 8776 u8 reserved_at_1[0x18]; 8777 u8 sensor_index[0x7]; 8778 8779 u8 reserved_at_20[0x10]; 8780 u8 temperature[0x10]; 8781 8782 u8 mte[0x1]; 8783 u8 mtr[0x1]; 8784 u8 reserved_at_42[0x0e]; 8785 u8 max_temperature[0x10]; 8786 8787 u8 tee[0x2]; 8788 u8 reserved_at_62[0x0e]; 8789 u8 temperature_threshold_hi[0x10]; 8790 8791 u8 reserved_at_80[0x10]; 8792 u8 temperature_threshold_lo[0x10]; 8793 8794 u8 reserved_at_100[0x20]; 8795 8796 u8 sensor_name[0x40]; 8797 }; 8798 8799 struct mlx5_ifc_lane_2_module_mapping_bits { 8800 u8 reserved_0[0x6]; 8801 u8 rx_lane[0x2]; 8802 u8 reserved_1[0x6]; 8803 u8 tx_lane[0x2]; 8804 u8 reserved_2[0x8]; 8805 u8 module[0x8]; 8806 }; 8807 8808 struct mlx5_ifc_eth_per_traffic_class_layout_bits { 8809 u8 transmit_queue_high[0x20]; 8810 8811 u8 transmit_queue_low[0x20]; 8812 8813 u8 reserved_0[0x780]; 8814 }; 8815 8816 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits { 8817 u8 no_buffer_discard_uc_high[0x20]; 8818 8819 u8 no_buffer_discard_uc_low[0x20]; 8820 8821 u8 wred_discard_high[0x20]; 8822 8823 u8 wred_discard_low[0x20]; 8824 8825 u8 reserved_0[0x740]; 8826 }; 8827 8828 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 8829 u8 rx_octets_high[0x20]; 8830 8831 u8 rx_octets_low[0x20]; 8832 8833 u8 reserved_0[0xc0]; 8834 8835 u8 rx_frames_high[0x20]; 8836 8837 u8 rx_frames_low[0x20]; 8838 8839 u8 tx_octets_high[0x20]; 8840 8841 u8 tx_octets_low[0x20]; 8842 8843 u8 reserved_1[0xc0]; 8844 8845 u8 tx_frames_high[0x20]; 8846 8847 u8 tx_frames_low[0x20]; 8848 8849 u8 rx_pause_high[0x20]; 8850 8851 u8 rx_pause_low[0x20]; 8852 8853 u8 rx_pause_duration_high[0x20]; 8854 8855 u8 rx_pause_duration_low[0x20]; 8856 8857 u8 tx_pause_high[0x20]; 8858 8859 u8 tx_pause_low[0x20]; 8860 8861 u8 tx_pause_duration_high[0x20]; 8862 8863 u8 tx_pause_duration_low[0x20]; 8864 8865 u8 rx_pause_transition_high[0x20]; 8866 8867 u8 rx_pause_transition_low[0x20]; 8868 8869 u8 rx_discards_high[0x20]; 8870 8871 u8 rx_discards_low[0x20]; 8872 8873 u8 device_stall_minor_watermark_cnt_high[0x20]; 8874 8875 u8 device_stall_minor_watermark_cnt_low[0x20]; 8876 8877 u8 device_stall_critical_watermark_cnt_high[0x20]; 8878 8879 u8 device_stall_critical_watermark_cnt_low[0x20]; 8880 8881 u8 reserved_2[0x340]; 8882 }; 8883 8884 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 8885 u8 port_transmit_wait_high[0x20]; 8886 8887 u8 port_transmit_wait_low[0x20]; 8888 8889 u8 ecn_marked_high[0x20]; 8890 8891 u8 ecn_marked_low[0x20]; 8892 8893 u8 no_buffer_discard_mc_high[0x20]; 8894 8895 u8 no_buffer_discard_mc_low[0x20]; 8896 8897 u8 rx_ebp_high[0x20]; 8898 8899 u8 rx_ebp_low[0x20]; 8900 8901 u8 tx_ebp_high[0x20]; 8902 8903 u8 tx_ebp_low[0x20]; 8904 8905 u8 rx_buffer_almost_full_high[0x20]; 8906 8907 u8 rx_buffer_almost_full_low[0x20]; 8908 8909 u8 rx_buffer_full_high[0x20]; 8910 8911 u8 rx_buffer_full_low[0x20]; 8912 8913 u8 rx_icrc_encapsulated_high[0x20]; 8914 8915 u8 rx_icrc_encapsulated_low[0x20]; 8916 8917 u8 reserved_0[0x80]; 8918 8919 u8 tx_stats_pkts64octets_high[0x20]; 8920 8921 u8 tx_stats_pkts64octets_low[0x20]; 8922 8923 u8 tx_stats_pkts65to127octets_high[0x20]; 8924 8925 u8 tx_stats_pkts65to127octets_low[0x20]; 8926 8927 u8 tx_stats_pkts128to255octets_high[0x20]; 8928 8929 u8 tx_stats_pkts128to255octets_low[0x20]; 8930 8931 u8 tx_stats_pkts256to511octets_high[0x20]; 8932 8933 u8 tx_stats_pkts256to511octets_low[0x20]; 8934 8935 u8 tx_stats_pkts512to1023octets_high[0x20]; 8936 8937 u8 tx_stats_pkts512to1023octets_low[0x20]; 8938 8939 u8 tx_stats_pkts1024to1518octets_high[0x20]; 8940 8941 u8 tx_stats_pkts1024to1518octets_low[0x20]; 8942 8943 u8 tx_stats_pkts1519to2047octets_high[0x20]; 8944 8945 u8 tx_stats_pkts1519to2047octets_low[0x20]; 8946 8947 u8 tx_stats_pkts2048to4095octets_high[0x20]; 8948 8949 u8 tx_stats_pkts2048to4095octets_low[0x20]; 8950 8951 u8 tx_stats_pkts4096to8191octets_high[0x20]; 8952 8953 u8 tx_stats_pkts4096to8191octets_low[0x20]; 8954 8955 u8 tx_stats_pkts8192to10239octets_high[0x20]; 8956 8957 u8 tx_stats_pkts8192to10239octets_low[0x20]; 8958 8959 u8 reserved_1[0x2C0]; 8960 }; 8961 8962 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 8963 u8 a_frames_transmitted_ok_high[0x20]; 8964 8965 u8 a_frames_transmitted_ok_low[0x20]; 8966 8967 u8 a_frames_received_ok_high[0x20]; 8968 8969 u8 a_frames_received_ok_low[0x20]; 8970 8971 u8 a_frame_check_sequence_errors_high[0x20]; 8972 8973 u8 a_frame_check_sequence_errors_low[0x20]; 8974 8975 u8 a_alignment_errors_high[0x20]; 8976 8977 u8 a_alignment_errors_low[0x20]; 8978 8979 u8 a_octets_transmitted_ok_high[0x20]; 8980 8981 u8 a_octets_transmitted_ok_low[0x20]; 8982 8983 u8 a_octets_received_ok_high[0x20]; 8984 8985 u8 a_octets_received_ok_low[0x20]; 8986 8987 u8 a_multicast_frames_xmitted_ok_high[0x20]; 8988 8989 u8 a_multicast_frames_xmitted_ok_low[0x20]; 8990 8991 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 8992 8993 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 8994 8995 u8 a_multicast_frames_received_ok_high[0x20]; 8996 8997 u8 a_multicast_frames_received_ok_low[0x20]; 8998 8999 u8 a_broadcast_frames_recieved_ok_high[0x20]; 9000 9001 u8 a_broadcast_frames_recieved_ok_low[0x20]; 9002 9003 u8 a_in_range_length_errors_high[0x20]; 9004 9005 u8 a_in_range_length_errors_low[0x20]; 9006 9007 u8 a_out_of_range_length_field_high[0x20]; 9008 9009 u8 a_out_of_range_length_field_low[0x20]; 9010 9011 u8 a_frame_too_long_errors_high[0x20]; 9012 9013 u8 a_frame_too_long_errors_low[0x20]; 9014 9015 u8 a_symbol_error_during_carrier_high[0x20]; 9016 9017 u8 a_symbol_error_during_carrier_low[0x20]; 9018 9019 u8 a_mac_control_frames_transmitted_high[0x20]; 9020 9021 u8 a_mac_control_frames_transmitted_low[0x20]; 9022 9023 u8 a_mac_control_frames_received_high[0x20]; 9024 9025 u8 a_mac_control_frames_received_low[0x20]; 9026 9027 u8 a_unsupported_opcodes_received_high[0x20]; 9028 9029 u8 a_unsupported_opcodes_received_low[0x20]; 9030 9031 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 9032 9033 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 9034 9035 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 9036 9037 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 9038 9039 u8 reserved_0[0x300]; 9040 }; 9041 9042 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 9043 u8 dot3stats_alignment_errors_high[0x20]; 9044 9045 u8 dot3stats_alignment_errors_low[0x20]; 9046 9047 u8 dot3stats_fcs_errors_high[0x20]; 9048 9049 u8 dot3stats_fcs_errors_low[0x20]; 9050 9051 u8 dot3stats_single_collision_frames_high[0x20]; 9052 9053 u8 dot3stats_single_collision_frames_low[0x20]; 9054 9055 u8 dot3stats_multiple_collision_frames_high[0x20]; 9056 9057 u8 dot3stats_multiple_collision_frames_low[0x20]; 9058 9059 u8 dot3stats_sqe_test_errors_high[0x20]; 9060 9061 u8 dot3stats_sqe_test_errors_low[0x20]; 9062 9063 u8 dot3stats_deferred_transmissions_high[0x20]; 9064 9065 u8 dot3stats_deferred_transmissions_low[0x20]; 9066 9067 u8 dot3stats_late_collisions_high[0x20]; 9068 9069 u8 dot3stats_late_collisions_low[0x20]; 9070 9071 u8 dot3stats_excessive_collisions_high[0x20]; 9072 9073 u8 dot3stats_excessive_collisions_low[0x20]; 9074 9075 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 9076 9077 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 9078 9079 u8 dot3stats_carrier_sense_errors_high[0x20]; 9080 9081 u8 dot3stats_carrier_sense_errors_low[0x20]; 9082 9083 u8 dot3stats_frame_too_longs_high[0x20]; 9084 9085 u8 dot3stats_frame_too_longs_low[0x20]; 9086 9087 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 9088 9089 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 9090 9091 u8 dot3stats_symbol_errors_high[0x20]; 9092 9093 u8 dot3stats_symbol_errors_low[0x20]; 9094 9095 u8 dot3control_in_unknown_opcodes_high[0x20]; 9096 9097 u8 dot3control_in_unknown_opcodes_low[0x20]; 9098 9099 u8 dot3in_pause_frames_high[0x20]; 9100 9101 u8 dot3in_pause_frames_low[0x20]; 9102 9103 u8 dot3out_pause_frames_high[0x20]; 9104 9105 u8 dot3out_pause_frames_low[0x20]; 9106 9107 u8 reserved_0[0x3c0]; 9108 }; 9109 9110 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 9111 u8 if_in_octets_high[0x20]; 9112 9113 u8 if_in_octets_low[0x20]; 9114 9115 u8 if_in_ucast_pkts_high[0x20]; 9116 9117 u8 if_in_ucast_pkts_low[0x20]; 9118 9119 u8 if_in_discards_high[0x20]; 9120 9121 u8 if_in_discards_low[0x20]; 9122 9123 u8 if_in_errors_high[0x20]; 9124 9125 u8 if_in_errors_low[0x20]; 9126 9127 u8 if_in_unknown_protos_high[0x20]; 9128 9129 u8 if_in_unknown_protos_low[0x20]; 9130 9131 u8 if_out_octets_high[0x20]; 9132 9133 u8 if_out_octets_low[0x20]; 9134 9135 u8 if_out_ucast_pkts_high[0x20]; 9136 9137 u8 if_out_ucast_pkts_low[0x20]; 9138 9139 u8 if_out_discards_high[0x20]; 9140 9141 u8 if_out_discards_low[0x20]; 9142 9143 u8 if_out_errors_high[0x20]; 9144 9145 u8 if_out_errors_low[0x20]; 9146 9147 u8 if_in_multicast_pkts_high[0x20]; 9148 9149 u8 if_in_multicast_pkts_low[0x20]; 9150 9151 u8 if_in_broadcast_pkts_high[0x20]; 9152 9153 u8 if_in_broadcast_pkts_low[0x20]; 9154 9155 u8 if_out_multicast_pkts_high[0x20]; 9156 9157 u8 if_out_multicast_pkts_low[0x20]; 9158 9159 u8 if_out_broadcast_pkts_high[0x20]; 9160 9161 u8 if_out_broadcast_pkts_low[0x20]; 9162 9163 u8 reserved_0[0x480]; 9164 }; 9165 9166 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 9167 u8 ether_stats_drop_events_high[0x20]; 9168 9169 u8 ether_stats_drop_events_low[0x20]; 9170 9171 u8 ether_stats_octets_high[0x20]; 9172 9173 u8 ether_stats_octets_low[0x20]; 9174 9175 u8 ether_stats_pkts_high[0x20]; 9176 9177 u8 ether_stats_pkts_low[0x20]; 9178 9179 u8 ether_stats_broadcast_pkts_high[0x20]; 9180 9181 u8 ether_stats_broadcast_pkts_low[0x20]; 9182 9183 u8 ether_stats_multicast_pkts_high[0x20]; 9184 9185 u8 ether_stats_multicast_pkts_low[0x20]; 9186 9187 u8 ether_stats_crc_align_errors_high[0x20]; 9188 9189 u8 ether_stats_crc_align_errors_low[0x20]; 9190 9191 u8 ether_stats_undersize_pkts_high[0x20]; 9192 9193 u8 ether_stats_undersize_pkts_low[0x20]; 9194 9195 u8 ether_stats_oversize_pkts_high[0x20]; 9196 9197 u8 ether_stats_oversize_pkts_low[0x20]; 9198 9199 u8 ether_stats_fragments_high[0x20]; 9200 9201 u8 ether_stats_fragments_low[0x20]; 9202 9203 u8 ether_stats_jabbers_high[0x20]; 9204 9205 u8 ether_stats_jabbers_low[0x20]; 9206 9207 u8 ether_stats_collisions_high[0x20]; 9208 9209 u8 ether_stats_collisions_low[0x20]; 9210 9211 u8 ether_stats_pkts64octets_high[0x20]; 9212 9213 u8 ether_stats_pkts64octets_low[0x20]; 9214 9215 u8 ether_stats_pkts65to127octets_high[0x20]; 9216 9217 u8 ether_stats_pkts65to127octets_low[0x20]; 9218 9219 u8 ether_stats_pkts128to255octets_high[0x20]; 9220 9221 u8 ether_stats_pkts128to255octets_low[0x20]; 9222 9223 u8 ether_stats_pkts256to511octets_high[0x20]; 9224 9225 u8 ether_stats_pkts256to511octets_low[0x20]; 9226 9227 u8 ether_stats_pkts512to1023octets_high[0x20]; 9228 9229 u8 ether_stats_pkts512to1023octets_low[0x20]; 9230 9231 u8 ether_stats_pkts1024to1518octets_high[0x20]; 9232 9233 u8 ether_stats_pkts1024to1518octets_low[0x20]; 9234 9235 u8 ether_stats_pkts1519to2047octets_high[0x20]; 9236 9237 u8 ether_stats_pkts1519to2047octets_low[0x20]; 9238 9239 u8 ether_stats_pkts2048to4095octets_high[0x20]; 9240 9241 u8 ether_stats_pkts2048to4095octets_low[0x20]; 9242 9243 u8 ether_stats_pkts4096to8191octets_high[0x20]; 9244 9245 u8 ether_stats_pkts4096to8191octets_low[0x20]; 9246 9247 u8 ether_stats_pkts8192to10239octets_high[0x20]; 9248 9249 u8 ether_stats_pkts8192to10239octets_low[0x20]; 9250 9251 u8 reserved_0[0x280]; 9252 }; 9253 9254 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits { 9255 u8 symbol_error_counter[0x10]; 9256 u8 link_error_recovery_counter[0x8]; 9257 u8 link_downed_counter[0x8]; 9258 9259 u8 port_rcv_errors[0x10]; 9260 u8 port_rcv_remote_physical_errors[0x10]; 9261 9262 u8 port_rcv_switch_relay_errors[0x10]; 9263 u8 port_xmit_discards[0x10]; 9264 9265 u8 port_xmit_constraint_errors[0x8]; 9266 u8 port_rcv_constraint_errors[0x8]; 9267 u8 reserved_0[0x8]; 9268 u8 local_link_integrity_errors[0x4]; 9269 u8 excessive_buffer_overrun_errors[0x4]; 9270 9271 u8 reserved_1[0x10]; 9272 u8 vl_15_dropped[0x10]; 9273 9274 u8 port_xmit_data[0x20]; 9275 9276 u8 port_rcv_data[0x20]; 9277 9278 u8 port_xmit_pkts[0x20]; 9279 9280 u8 port_rcv_pkts[0x20]; 9281 9282 u8 port_xmit_wait[0x20]; 9283 9284 u8 reserved_2[0x680]; 9285 }; 9286 9287 struct mlx5_ifc_trc_tlb_reg_bits { 9288 u8 reserved_0[0x80]; 9289 9290 u8 tlb_addr[0][0x40]; 9291 }; 9292 9293 struct mlx5_ifc_trc_read_fifo_reg_bits { 9294 u8 reserved_0[0x10]; 9295 u8 requested_event_num[0x10]; 9296 9297 u8 reserved_1[0x20]; 9298 9299 u8 reserved_2[0x10]; 9300 u8 acual_event_num[0x10]; 9301 9302 u8 reserved_3[0x20]; 9303 9304 u8 event[0][0x40]; 9305 }; 9306 9307 struct mlx5_ifc_trc_lock_reg_bits { 9308 u8 reserved_0[0x1f]; 9309 u8 lock[0x1]; 9310 9311 u8 reserved_1[0x60]; 9312 }; 9313 9314 struct mlx5_ifc_trc_filter_reg_bits { 9315 u8 status[0x1]; 9316 u8 reserved_0[0xf]; 9317 u8 filter_index[0x10]; 9318 9319 u8 reserved_1[0x20]; 9320 9321 u8 filter_val[0x20]; 9322 9323 u8 reserved_2[0x1a0]; 9324 }; 9325 9326 struct mlx5_ifc_trc_event_reg_bits { 9327 u8 status[0x1]; 9328 u8 reserved_0[0xf]; 9329 u8 event_index[0x10]; 9330 9331 u8 reserved_1[0x20]; 9332 9333 u8 event_id[0x20]; 9334 9335 u8 event_selector_val[0x10]; 9336 u8 event_selector_size[0x10]; 9337 9338 u8 reserved_2[0x180]; 9339 }; 9340 9341 struct mlx5_ifc_trc_conf_reg_bits { 9342 u8 limit_en[0x1]; 9343 u8 reserved_0[0x3]; 9344 u8 dump_mode[0x4]; 9345 u8 reserved_1[0x15]; 9346 u8 state[0x3]; 9347 9348 u8 reserved_2[0x20]; 9349 9350 u8 limit_event_index[0x20]; 9351 9352 u8 mkey[0x20]; 9353 9354 u8 fifo_ready_ev_num[0x20]; 9355 9356 u8 reserved_3[0x160]; 9357 }; 9358 9359 struct mlx5_ifc_trc_cap_reg_bits { 9360 u8 reserved_0[0x18]; 9361 u8 dump_mode[0x8]; 9362 9363 u8 reserved_1[0x20]; 9364 9365 u8 num_of_events[0x10]; 9366 u8 num_of_filters[0x10]; 9367 9368 u8 fifo_size[0x20]; 9369 9370 u8 tlb_size[0x10]; 9371 u8 event_size[0x10]; 9372 9373 u8 reserved_2[0x160]; 9374 }; 9375 9376 struct mlx5_ifc_set_node_in_bits { 9377 u8 node_description[64][0x8]; 9378 }; 9379 9380 struct mlx5_ifc_register_power_settings_bits { 9381 u8 reserved_0[0x18]; 9382 u8 power_settings_level[0x8]; 9383 9384 u8 reserved_1[0x60]; 9385 }; 9386 9387 struct mlx5_ifc_register_host_endianess_bits { 9388 u8 he[0x1]; 9389 u8 reserved_0[0x1f]; 9390 9391 u8 reserved_1[0x60]; 9392 }; 9393 9394 struct mlx5_ifc_register_diag_buffer_ctrl_bits { 9395 u8 physical_address[0x40]; 9396 }; 9397 9398 struct mlx5_ifc_qtct_reg_bits { 9399 u8 operation_type[0x2]; 9400 u8 cap_local_admin[0x1]; 9401 u8 cap_remote_admin[0x1]; 9402 u8 reserved_0[0x4]; 9403 u8 port_number[0x8]; 9404 u8 reserved_1[0xd]; 9405 u8 prio[0x3]; 9406 9407 u8 reserved_2[0x1d]; 9408 u8 tclass[0x3]; 9409 }; 9410 9411 struct mlx5_ifc_qpdp_reg_bits { 9412 u8 reserved_0[0x8]; 9413 u8 port_number[0x8]; 9414 u8 reserved_1[0x10]; 9415 9416 u8 reserved_2[0x1d]; 9417 u8 pprio[0x3]; 9418 }; 9419 9420 struct mlx5_ifc_port_info_ro_fields_param_bits { 9421 u8 reserved_0[0x8]; 9422 u8 port[0x8]; 9423 u8 max_gid[0x10]; 9424 9425 u8 reserved_1[0x20]; 9426 9427 u8 port_guid[0x40]; 9428 }; 9429 9430 struct mlx5_ifc_nvqc_reg_bits { 9431 u8 type[0x20]; 9432 9433 u8 reserved_0[0x18]; 9434 u8 version[0x4]; 9435 u8 reserved_1[0x2]; 9436 u8 support_wr[0x1]; 9437 u8 support_rd[0x1]; 9438 }; 9439 9440 struct mlx5_ifc_nvia_reg_bits { 9441 u8 reserved_0[0x1d]; 9442 u8 target[0x3]; 9443 9444 u8 reserved_1[0x20]; 9445 }; 9446 9447 struct mlx5_ifc_nvdi_reg_bits { 9448 struct mlx5_ifc_config_item_bits configuration_item_header; 9449 }; 9450 9451 struct mlx5_ifc_nvda_reg_bits { 9452 struct mlx5_ifc_config_item_bits configuration_item_header; 9453 9454 u8 configuration_item_data[0x20]; 9455 }; 9456 9457 struct mlx5_ifc_node_info_ro_fields_param_bits { 9458 u8 system_image_guid[0x40]; 9459 9460 u8 reserved_0[0x40]; 9461 9462 u8 node_guid[0x40]; 9463 9464 u8 reserved_1[0x10]; 9465 u8 max_pkey[0x10]; 9466 9467 u8 reserved_2[0x20]; 9468 }; 9469 9470 struct mlx5_ifc_ets_tcn_config_reg_bits { 9471 u8 g[0x1]; 9472 u8 b[0x1]; 9473 u8 r[0x1]; 9474 u8 reserved_0[0x9]; 9475 u8 group[0x4]; 9476 u8 reserved_1[0x9]; 9477 u8 bw_allocation[0x7]; 9478 9479 u8 reserved_2[0xc]; 9480 u8 max_bw_units[0x4]; 9481 u8 reserved_3[0x8]; 9482 u8 max_bw_value[0x8]; 9483 }; 9484 9485 struct mlx5_ifc_ets_global_config_reg_bits { 9486 u8 reserved_0[0x2]; 9487 u8 r[0x1]; 9488 u8 reserved_1[0x1d]; 9489 9490 u8 reserved_2[0xc]; 9491 u8 max_bw_units[0x4]; 9492 u8 reserved_3[0x8]; 9493 u8 max_bw_value[0x8]; 9494 }; 9495 9496 struct mlx5_ifc_qetc_reg_bits { 9497 u8 reserved_at_0[0x8]; 9498 u8 port_number[0x8]; 9499 u8 reserved_at_10[0x30]; 9500 9501 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 9502 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 9503 }; 9504 9505 struct mlx5_ifc_nodnic_mac_filters_bits { 9506 struct mlx5_ifc_mac_address_layout_bits mac_filter0; 9507 9508 struct mlx5_ifc_mac_address_layout_bits mac_filter1; 9509 9510 struct mlx5_ifc_mac_address_layout_bits mac_filter2; 9511 9512 struct mlx5_ifc_mac_address_layout_bits mac_filter3; 9513 9514 struct mlx5_ifc_mac_address_layout_bits mac_filter4; 9515 9516 u8 reserved_0[0xc0]; 9517 }; 9518 9519 struct mlx5_ifc_nodnic_gid_filters_bits { 9520 u8 mgid_filter0[16][0x8]; 9521 9522 u8 mgid_filter1[16][0x8]; 9523 9524 u8 mgid_filter2[16][0x8]; 9525 9526 u8 mgid_filter3[16][0x8]; 9527 }; 9528 9529 enum { 9530 MLX5_NODNIC_CONFIG_REG_NUM_PORTS_SINGLE_PORT = 0x0, 9531 MLX5_NODNIC_CONFIG_REG_NUM_PORTS_DUAL_PORT = 0x1, 9532 }; 9533 9534 enum { 9535 MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_LEGACY_CQE = 0x0, 9536 MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_NEW_CQE = 0x1, 9537 }; 9538 9539 struct mlx5_ifc_nodnic_config_reg_bits { 9540 u8 no_dram_nic_revision[0x8]; 9541 u8 hardware_format[0x8]; 9542 u8 support_receive_filter[0x1]; 9543 u8 support_promisc_filter[0x1]; 9544 u8 support_promisc_multicast_filter[0x1]; 9545 u8 reserved_0[0x2]; 9546 u8 log_working_buffer_size[0x3]; 9547 u8 log_pkey_table_size[0x4]; 9548 u8 reserved_1[0x3]; 9549 u8 num_ports[0x1]; 9550 9551 u8 reserved_2[0x2]; 9552 u8 log_max_ring_size[0x6]; 9553 u8 reserved_3[0x18]; 9554 9555 u8 lkey[0x20]; 9556 9557 u8 cqe_format[0x4]; 9558 u8 reserved_4[0x1c]; 9559 9560 u8 node_guid[0x40]; 9561 9562 u8 reserved_5[0x740]; 9563 9564 struct mlx5_ifc_nodnic_port_config_reg_bits port1_settings; 9565 9566 struct mlx5_ifc_nodnic_port_config_reg_bits port2_settings; 9567 }; 9568 9569 struct mlx5_ifc_vlan_layout_bits { 9570 u8 reserved_0[0x14]; 9571 u8 vlan[0xc]; 9572 9573 u8 reserved_1[0x20]; 9574 }; 9575 9576 struct mlx5_ifc_umr_pointer_desc_argument_bits { 9577 u8 reserved_0[0x20]; 9578 9579 u8 mkey[0x20]; 9580 9581 u8 addressh_63_32[0x20]; 9582 9583 u8 addressl_31_0[0x20]; 9584 }; 9585 9586 struct mlx5_ifc_ud_adrs_vector_bits { 9587 u8 dc_key[0x40]; 9588 9589 u8 ext[0x1]; 9590 u8 reserved_0[0x7]; 9591 u8 destination_qp_dct[0x18]; 9592 9593 u8 static_rate[0x4]; 9594 u8 sl_eth_prio[0x4]; 9595 u8 fl[0x1]; 9596 u8 mlid[0x7]; 9597 u8 rlid_udp_sport[0x10]; 9598 9599 u8 reserved_1[0x20]; 9600 9601 u8 rmac_47_16[0x20]; 9602 9603 u8 rmac_15_0[0x10]; 9604 u8 tclass[0x8]; 9605 u8 hop_limit[0x8]; 9606 9607 u8 reserved_2[0x1]; 9608 u8 grh[0x1]; 9609 u8 reserved_3[0x2]; 9610 u8 src_addr_index[0x8]; 9611 u8 flow_label[0x14]; 9612 9613 u8 rgid_rip[16][0x8]; 9614 }; 9615 9616 struct mlx5_ifc_port_module_event_bits { 9617 u8 reserved_0[0x8]; 9618 u8 module[0x8]; 9619 u8 reserved_1[0xc]; 9620 u8 module_status[0x4]; 9621 9622 u8 reserved_2[0x14]; 9623 u8 error_type[0x4]; 9624 u8 reserved_3[0x8]; 9625 9626 u8 reserved_4[0xa0]; 9627 }; 9628 9629 struct mlx5_ifc_icmd_control_bits { 9630 u8 opcode[0x10]; 9631 u8 status[0x8]; 9632 u8 reserved_0[0x7]; 9633 u8 busy[0x1]; 9634 }; 9635 9636 struct mlx5_ifc_eqe_bits { 9637 u8 reserved_0[0x8]; 9638 u8 event_type[0x8]; 9639 u8 reserved_1[0x8]; 9640 u8 event_sub_type[0x8]; 9641 9642 u8 reserved_2[0xe0]; 9643 9644 union mlx5_ifc_event_auto_bits event_data; 9645 9646 u8 reserved_3[0x10]; 9647 u8 signature[0x8]; 9648 u8 reserved_4[0x7]; 9649 u8 owner[0x1]; 9650 }; 9651 9652 enum { 9653 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 9654 }; 9655 9656 struct mlx5_ifc_cmd_queue_entry_bits { 9657 u8 type[0x8]; 9658 u8 reserved_0[0x18]; 9659 9660 u8 input_length[0x20]; 9661 9662 u8 input_mailbox_pointer_63_32[0x20]; 9663 9664 u8 input_mailbox_pointer_31_9[0x17]; 9665 u8 reserved_1[0x9]; 9666 9667 u8 command_input_inline_data[16][0x8]; 9668 9669 u8 command_output_inline_data[16][0x8]; 9670 9671 u8 output_mailbox_pointer_63_32[0x20]; 9672 9673 u8 output_mailbox_pointer_31_9[0x17]; 9674 u8 reserved_2[0x9]; 9675 9676 u8 output_length[0x20]; 9677 9678 u8 token[0x8]; 9679 u8 signature[0x8]; 9680 u8 reserved_3[0x8]; 9681 u8 status[0x7]; 9682 u8 ownership[0x1]; 9683 }; 9684 9685 struct mlx5_ifc_cmd_out_bits { 9686 u8 status[0x8]; 9687 u8 reserved_0[0x18]; 9688 9689 u8 syndrome[0x20]; 9690 9691 u8 command_output[0x20]; 9692 }; 9693 9694 struct mlx5_ifc_cmd_in_bits { 9695 u8 opcode[0x10]; 9696 u8 reserved_0[0x10]; 9697 9698 u8 reserved_1[0x10]; 9699 u8 op_mod[0x10]; 9700 9701 u8 command[0][0x20]; 9702 }; 9703 9704 struct mlx5_ifc_cmd_if_box_bits { 9705 u8 mailbox_data[512][0x8]; 9706 9707 u8 reserved_0[0x180]; 9708 9709 u8 next_pointer_63_32[0x20]; 9710 9711 u8 next_pointer_31_10[0x16]; 9712 u8 reserved_1[0xa]; 9713 9714 u8 block_number[0x20]; 9715 9716 u8 reserved_2[0x8]; 9717 u8 token[0x8]; 9718 u8 ctrl_signature[0x8]; 9719 u8 signature[0x8]; 9720 }; 9721 9722 struct mlx5_ifc_mtt_bits { 9723 u8 ptag_63_32[0x20]; 9724 9725 u8 ptag_31_8[0x18]; 9726 u8 reserved_0[0x6]; 9727 u8 wr_en[0x1]; 9728 u8 rd_en[0x1]; 9729 }; 9730 9731 /* Vendor Specific Capabilities, VSC */ 9732 enum { 9733 MLX5_VSC_DOMAIN_ICMD = 0x1, 9734 MLX5_VSC_DOMAIN_PROTECTED_CRSPACE = 0x6, 9735 MLX5_VSC_DOMAIN_SCAN_CRSPACE = 0x7, 9736 MLX5_VSC_DOMAIN_SEMAPHORES = 0xA, 9737 }; 9738 9739 struct mlx5_ifc_vendor_specific_cap_bits { 9740 u8 type[0x8]; 9741 u8 length[0x8]; 9742 u8 next_pointer[0x8]; 9743 u8 capability_id[0x8]; 9744 9745 u8 status[0x3]; 9746 u8 reserved_0[0xd]; 9747 u8 space[0x10]; 9748 9749 u8 counter[0x20]; 9750 9751 u8 semaphore[0x20]; 9752 9753 u8 flag[0x1]; 9754 u8 reserved_1[0x1]; 9755 u8 address[0x1e]; 9756 9757 u8 data[0x20]; 9758 }; 9759 9760 struct mlx5_ifc_vsc_space_bits { 9761 u8 status[0x3]; 9762 u8 reserved0[0xd]; 9763 u8 space[0x10]; 9764 }; 9765 9766 struct mlx5_ifc_vsc_addr_bits { 9767 u8 flag[0x1]; 9768 u8 reserved0[0x1]; 9769 u8 address[0x1e]; 9770 }; 9771 9772 enum { 9773 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 9774 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 9775 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 9776 }; 9777 9778 enum { 9779 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 9780 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 9781 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 9782 }; 9783 9784 enum { 9785 MLX5_HEALTH_SYNDR_FW_ERR = 0x1, 9786 MLX5_HEALTH_SYNDR_IRISC_ERR = 0x7, 9787 MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR = 0x8, 9788 MLX5_HEALTH_SYNDR_CRC_ERR = 0x9, 9789 MLX5_HEALTH_SYNDR_FETCH_PCI_ERR = 0xa, 9790 MLX5_HEALTH_SYNDR_HW_FTL_ERR = 0xb, 9791 MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR = 0xc, 9792 MLX5_HEALTH_SYNDR_EQ_ERR = 0xd, 9793 MLX5_HEALTH_SYNDR_EQ_INV = 0xe, 9794 MLX5_HEALTH_SYNDR_FFSER_ERR = 0xf, 9795 MLX5_HEALTH_SYNDR_HIGH_TEMP = 0x10, 9796 }; 9797 9798 struct mlx5_ifc_initial_seg_bits { 9799 u8 fw_rev_minor[0x10]; 9800 u8 fw_rev_major[0x10]; 9801 9802 u8 cmd_interface_rev[0x10]; 9803 u8 fw_rev_subminor[0x10]; 9804 9805 u8 reserved_0[0x40]; 9806 9807 u8 cmdq_phy_addr_63_32[0x20]; 9808 9809 u8 cmdq_phy_addr_31_12[0x14]; 9810 u8 reserved_1[0x2]; 9811 u8 nic_interface[0x2]; 9812 u8 log_cmdq_size[0x4]; 9813 u8 log_cmdq_stride[0x4]; 9814 9815 u8 command_doorbell_vector[0x20]; 9816 9817 u8 reserved_2[0xf00]; 9818 9819 u8 initializing[0x1]; 9820 u8 reserved_3[0x4]; 9821 u8 nic_interface_supported[0x3]; 9822 u8 reserved_4[0x18]; 9823 9824 struct mlx5_ifc_health_buffer_bits health_buffer; 9825 9826 u8 no_dram_nic_offset[0x20]; 9827 9828 u8 reserved_5[0x6de0]; 9829 9830 u8 internal_timer_h[0x20]; 9831 9832 u8 internal_timer_l[0x20]; 9833 9834 u8 reserved_6[0x20]; 9835 9836 u8 reserved_7[0x1f]; 9837 u8 clear_int[0x1]; 9838 9839 u8 health_syndrome[0x8]; 9840 u8 health_counter[0x18]; 9841 9842 u8 reserved_8[0x17fc0]; 9843 }; 9844 9845 union mlx5_ifc_icmd_interface_document_bits { 9846 struct mlx5_ifc_fw_version_bits fw_version; 9847 struct mlx5_ifc_icmd_access_reg_in_bits icmd_access_reg_in; 9848 struct mlx5_ifc_icmd_access_reg_out_bits icmd_access_reg_out; 9849 struct mlx5_ifc_icmd_init_ocsd_in_bits icmd_init_ocsd_in; 9850 struct mlx5_ifc_icmd_ocbb_init_in_bits icmd_ocbb_init_in; 9851 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits icmd_ocbb_query_etoc_stats_out; 9852 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits icmd_ocbb_query_header_stats_out; 9853 struct mlx5_ifc_icmd_query_cap_general_bits icmd_query_cap_general; 9854 struct mlx5_ifc_icmd_query_cap_in_bits icmd_query_cap_in; 9855 struct mlx5_ifc_icmd_query_fw_info_out_bits icmd_query_fw_info_out; 9856 struct mlx5_ifc_icmd_query_virtual_mac_out_bits icmd_query_virtual_mac_out; 9857 struct mlx5_ifc_icmd_set_virtual_mac_in_bits icmd_set_virtual_mac_in; 9858 struct mlx5_ifc_icmd_set_wol_rol_in_bits icmd_set_wol_rol_in; 9859 struct mlx5_ifc_icmd_set_wol_rol_out_bits icmd_set_wol_rol_out; 9860 u8 reserved_0[0x42c0]; 9861 }; 9862 9863 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 9864 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 9865 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 9866 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 9867 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 9868 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 9869 struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp; 9870 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 9871 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 9872 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 9873 struct mlx5_ifc_infiniband_port_cntrs_bits infiniband_port_cntrs; 9874 u8 reserved_0[0x7c0]; 9875 }; 9876 9877 struct mlx5_ifc_ppcnt_reg_bits { 9878 u8 swid[0x8]; 9879 u8 local_port[0x8]; 9880 u8 pnat[0x2]; 9881 u8 reserved_0[0x8]; 9882 u8 grp[0x6]; 9883 9884 u8 clr[0x1]; 9885 u8 reserved_1[0x1c]; 9886 u8 prio_tc[0x3]; 9887 9888 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9889 }; 9890 9891 struct mlx5_ifc_pcie_lanes_counters_bits { 9892 u8 life_time_counter_high[0x20]; 9893 9894 u8 life_time_counter_low[0x20]; 9895 9896 u8 error_counter_lane0[0x20]; 9897 9898 u8 error_counter_lane1[0x20]; 9899 9900 u8 error_counter_lane2[0x20]; 9901 9902 u8 error_counter_lane3[0x20]; 9903 9904 u8 error_counter_lane4[0x20]; 9905 9906 u8 error_counter_lane5[0x20]; 9907 9908 u8 error_counter_lane6[0x20]; 9909 9910 u8 error_counter_lane7[0x20]; 9911 9912 u8 error_counter_lane8[0x20]; 9913 9914 u8 error_counter_lane9[0x20]; 9915 9916 u8 error_counter_lane10[0x20]; 9917 9918 u8 error_counter_lane11[0x20]; 9919 9920 u8 error_counter_lane12[0x20]; 9921 9922 u8 error_counter_lane13[0x20]; 9923 9924 u8 error_counter_lane14[0x20]; 9925 9926 u8 error_counter_lane15[0x20]; 9927 9928 u8 reserved_at_240[0x580]; 9929 }; 9930 9931 struct mlx5_ifc_pcie_lanes_counters_ext_bits { 9932 u8 reserved_at_0[0x40]; 9933 9934 u8 error_counter_lane0[0x20]; 9935 9936 u8 error_counter_lane1[0x20]; 9937 9938 u8 error_counter_lane2[0x20]; 9939 9940 u8 error_counter_lane3[0x20]; 9941 9942 u8 error_counter_lane4[0x20]; 9943 9944 u8 error_counter_lane5[0x20]; 9945 9946 u8 error_counter_lane6[0x20]; 9947 9948 u8 error_counter_lane7[0x20]; 9949 9950 u8 error_counter_lane8[0x20]; 9951 9952 u8 error_counter_lane9[0x20]; 9953 9954 u8 error_counter_lane10[0x20]; 9955 9956 u8 error_counter_lane11[0x20]; 9957 9958 u8 error_counter_lane12[0x20]; 9959 9960 u8 error_counter_lane13[0x20]; 9961 9962 u8 error_counter_lane14[0x20]; 9963 9964 u8 error_counter_lane15[0x20]; 9965 9966 u8 reserved_at_240[0x580]; 9967 }; 9968 9969 struct mlx5_ifc_pcie_perf_counters_bits { 9970 u8 life_time_counter_high[0x20]; 9971 9972 u8 life_time_counter_low[0x20]; 9973 9974 u8 rx_errors[0x20]; 9975 9976 u8 tx_errors[0x20]; 9977 9978 u8 l0_to_recovery_eieos[0x20]; 9979 9980 u8 l0_to_recovery_ts[0x20]; 9981 9982 u8 l0_to_recovery_framing[0x20]; 9983 9984 u8 l0_to_recovery_retrain[0x20]; 9985 9986 u8 crc_error_dllp[0x20]; 9987 9988 u8 crc_error_tlp[0x20]; 9989 9990 u8 tx_overflow_buffer_pkt[0x40]; 9991 9992 u8 outbound_stalled_reads[0x20]; 9993 9994 u8 outbound_stalled_writes[0x20]; 9995 9996 u8 outbound_stalled_reads_events[0x20]; 9997 9998 u8 outbound_stalled_writes_events[0x20]; 9999 10000 u8 tx_overflow_buffer_marked_pkt[0x40]; 10001 10002 u8 reserved_at_240[0x580]; 10003 }; 10004 10005 struct mlx5_ifc_pcie_perf_counters_ext_bits { 10006 u8 reserved_at_0[0x40]; 10007 10008 u8 rx_errors[0x20]; 10009 10010 u8 tx_errors[0x20]; 10011 10012 u8 reserved_at_80[0xc0]; 10013 10014 u8 tx_overflow_buffer_pkt[0x40]; 10015 10016 u8 outbound_stalled_reads[0x20]; 10017 10018 u8 outbound_stalled_writes[0x20]; 10019 10020 u8 outbound_stalled_reads_events[0x20]; 10021 10022 u8 outbound_stalled_writes_events[0x20]; 10023 10024 u8 tx_overflow_buffer_marked_pkt[0x40]; 10025 10026 u8 reserved_at_240[0x580]; 10027 }; 10028 10029 struct mlx5_ifc_pcie_timers_states_bits { 10030 u8 life_time_counter_high[0x20]; 10031 10032 u8 life_time_counter_low[0x20]; 10033 10034 u8 time_to_boot_image_start[0x20]; 10035 10036 u8 time_to_link_image[0x20]; 10037 10038 u8 calibration_time[0x20]; 10039 10040 u8 time_to_first_perst[0x20]; 10041 10042 u8 time_to_detect_state[0x20]; 10043 10044 u8 time_to_l0[0x20]; 10045 10046 u8 time_to_crs_en[0x20]; 10047 10048 u8 time_to_plastic_image_start[0x20]; 10049 10050 u8 time_to_iron_image_start[0x20]; 10051 10052 u8 perst_handler[0x20]; 10053 10054 u8 times_in_l1[0x20]; 10055 10056 u8 times_in_l23[0x20]; 10057 10058 u8 dl_down[0x20]; 10059 10060 u8 config_cycle1usec[0x20]; 10061 10062 u8 config_cycle2to7usec[0x20]; 10063 10064 u8 config_cycle8to15usec[0x20]; 10065 10066 u8 config_cycle16to63usec[0x20]; 10067 10068 u8 config_cycle64usec[0x20]; 10069 10070 u8 correctable_err_msg_sent[0x20]; 10071 10072 u8 non_fatal_err_msg_sent[0x20]; 10073 10074 u8 fatal_err_msg_sent[0x20]; 10075 10076 u8 reserved_at_2e0[0x4e0]; 10077 }; 10078 10079 struct mlx5_ifc_pcie_timers_states_ext_bits { 10080 u8 reserved_at_0[0x40]; 10081 10082 u8 time_to_boot_image_start[0x20]; 10083 10084 u8 time_to_link_image[0x20]; 10085 10086 u8 calibration_time[0x20]; 10087 10088 u8 time_to_first_perst[0x20]; 10089 10090 u8 time_to_detect_state[0x20]; 10091 10092 u8 time_to_l0[0x20]; 10093 10094 u8 time_to_crs_en[0x20]; 10095 10096 u8 time_to_plastic_image_start[0x20]; 10097 10098 u8 time_to_iron_image_start[0x20]; 10099 10100 u8 perst_handler[0x20]; 10101 10102 u8 times_in_l1[0x20]; 10103 10104 u8 times_in_l23[0x20]; 10105 10106 u8 dl_down[0x20]; 10107 10108 u8 config_cycle1usec[0x20]; 10109 10110 u8 config_cycle2to7usec[0x20]; 10111 10112 u8 config_cycle8to15usec[0x20]; 10113 10114 u8 config_cycle16to63usec[0x20]; 10115 10116 u8 config_cycle64usec[0x20]; 10117 10118 u8 correctable_err_msg_sent[0x20]; 10119 10120 u8 non_fatal_err_msg_sent[0x20]; 10121 10122 u8 fatal_err_msg_sent[0x20]; 10123 10124 u8 reserved_at_2e0[0x4e0]; 10125 }; 10126 10127 union mlx5_ifc_mpcnt_reg_counter_set_auto_bits { 10128 struct mlx5_ifc_pcie_perf_counters_bits pcie_perf_counters; 10129 struct mlx5_ifc_pcie_lanes_counters_bits pcie_lanes_counters; 10130 struct mlx5_ifc_pcie_timers_states_bits pcie_timers_states; 10131 u8 reserved_at_0[0x7c0]; 10132 }; 10133 10134 union mlx5_ifc_mpcnt_reg_counter_set_auto_ext_bits { 10135 struct mlx5_ifc_pcie_perf_counters_ext_bits pcie_perf_counters_ext; 10136 struct mlx5_ifc_pcie_lanes_counters_ext_bits pcie_lanes_counters_ext; 10137 struct mlx5_ifc_pcie_timers_states_ext_bits pcie_timers_states_ext; 10138 u8 reserved_at_0[0x7c0]; 10139 }; 10140 10141 struct mlx5_ifc_mpcnt_reg_bits { 10142 u8 reserved_at_0[0x2]; 10143 u8 depth[0x6]; 10144 u8 pcie_index[0x8]; 10145 u8 node[0x8]; 10146 u8 reserved_at_18[0x2]; 10147 u8 grp[0x6]; 10148 10149 u8 clr[0x1]; 10150 u8 reserved_at_21[0x1f]; 10151 10152 union mlx5_ifc_mpcnt_reg_counter_set_auto_bits counter_set; 10153 }; 10154 10155 struct mlx5_ifc_mpcnt_reg_ext_bits { 10156 u8 reserved_at_0[0x2]; 10157 u8 depth[0x6]; 10158 u8 pcie_index[0x8]; 10159 u8 node[0x8]; 10160 u8 reserved_at_18[0x2]; 10161 u8 grp[0x6]; 10162 10163 u8 clr[0x1]; 10164 u8 reserved_at_21[0x1f]; 10165 10166 union mlx5_ifc_mpcnt_reg_counter_set_auto_ext_bits counter_set; 10167 }; 10168 10169 struct mlx5_ifc_monitor_opcodes_layout_bits { 10170 u8 reserved_at_0[0x10]; 10171 u8 monitor_opcode[0x10]; 10172 }; 10173 10174 union mlx5_ifc_pddr_status_opcode_bits { 10175 struct mlx5_ifc_monitor_opcodes_layout_bits monitor_opcodes; 10176 u8 reserved_at_0[0x20]; 10177 }; 10178 10179 struct mlx5_ifc_troubleshooting_info_page_layout_bits { 10180 u8 reserved_at_0[0x10]; 10181 u8 group_opcode[0x10]; 10182 10183 union mlx5_ifc_pddr_status_opcode_bits status_opcode; 10184 10185 u8 user_feedback_data[0x10]; 10186 u8 user_feedback_index[0x10]; 10187 10188 u8 status_message[0x760]; 10189 }; 10190 10191 union mlx5_ifc_pddr_page_data_bits { 10192 struct mlx5_ifc_troubleshooting_info_page_layout_bits troubleshooting_info_page; 10193 struct mlx5_ifc_pddr_module_info_bits pddr_module_info; 10194 u8 reserved_at_0[0x7c0]; 10195 }; 10196 10197 struct mlx5_ifc_pddr_reg_bits { 10198 u8 reserved_at_0[0x8]; 10199 u8 local_port[0x8]; 10200 u8 pnat[0x2]; 10201 u8 reserved_at_12[0xe]; 10202 10203 u8 reserved_at_20[0x18]; 10204 u8 page_select[0x8]; 10205 10206 union mlx5_ifc_pddr_page_data_bits page_data; 10207 }; 10208 10209 enum { 10210 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MPEIN = 0x9050, 10211 MLX5_MPEIN_PWR_STATUS_INVALID = 0, 10212 MLX5_MPEIN_PWR_STATUS_SUFFICIENT = 1, 10213 MLX5_MPEIN_PWR_STATUS_INSUFFICIENT = 2, 10214 }; 10215 10216 struct mlx5_ifc_mpein_reg_bits { 10217 u8 reserved_at_0[0x2]; 10218 u8 depth[0x6]; 10219 u8 pcie_index[0x8]; 10220 u8 node[0x8]; 10221 u8 reserved_at_18[0x8]; 10222 10223 u8 capability_mask[0x20]; 10224 10225 u8 reserved_at_40[0x8]; 10226 u8 link_width_enabled[0x8]; 10227 u8 link_speed_enabled[0x10]; 10228 10229 u8 lane0_physical_position[0x8]; 10230 u8 link_width_active[0x8]; 10231 u8 link_speed_active[0x10]; 10232 10233 u8 num_of_pfs[0x10]; 10234 u8 num_of_vfs[0x10]; 10235 10236 u8 bdf0[0x10]; 10237 u8 reserved_at_b0[0x10]; 10238 10239 u8 max_read_request_size[0x4]; 10240 u8 max_payload_size[0x4]; 10241 u8 reserved_at_c8[0x5]; 10242 u8 pwr_status[0x3]; 10243 u8 port_type[0x4]; 10244 u8 reserved_at_d4[0xb]; 10245 u8 lane_reversal[0x1]; 10246 10247 u8 reserved_at_e0[0x14]; 10248 u8 pci_power[0xc]; 10249 10250 u8 reserved_at_100[0x20]; 10251 10252 u8 device_status[0x10]; 10253 u8 port_state[0x8]; 10254 u8 reserved_at_138[0x8]; 10255 10256 u8 reserved_at_140[0x10]; 10257 u8 receiver_detect_result[0x10]; 10258 10259 u8 reserved_at_160[0x20]; 10260 }; 10261 10262 struct mlx5_ifc_mpein_reg_ext_bits { 10263 u8 reserved_at_0[0x2]; 10264 u8 depth[0x6]; 10265 u8 pcie_index[0x8]; 10266 u8 node[0x8]; 10267 u8 reserved_at_18[0x8]; 10268 10269 u8 reserved_at_20[0x20]; 10270 10271 u8 reserved_at_40[0x8]; 10272 u8 link_width_enabled[0x8]; 10273 u8 link_speed_enabled[0x10]; 10274 10275 u8 lane0_physical_position[0x8]; 10276 u8 link_width_active[0x8]; 10277 u8 link_speed_active[0x10]; 10278 10279 u8 num_of_pfs[0x10]; 10280 u8 num_of_vfs[0x10]; 10281 10282 u8 bdf0[0x10]; 10283 u8 reserved_at_b0[0x10]; 10284 10285 u8 max_read_request_size[0x4]; 10286 u8 max_payload_size[0x4]; 10287 u8 reserved_at_c8[0x5]; 10288 u8 pwr_status[0x3]; 10289 u8 port_type[0x4]; 10290 u8 reserved_at_d4[0xb]; 10291 u8 lane_reversal[0x1]; 10292 }; 10293 10294 struct mlx5_ifc_mcqi_cap_bits { 10295 u8 supported_info_bitmask[0x20]; 10296 10297 u8 component_size[0x20]; 10298 10299 u8 max_component_size[0x20]; 10300 10301 u8 log_mcda_word_size[0x4]; 10302 u8 reserved_at_64[0xc]; 10303 u8 mcda_max_write_size[0x10]; 10304 10305 u8 rd_en[0x1]; 10306 u8 reserved_at_81[0x1]; 10307 u8 match_chip_id[0x1]; 10308 u8 match_psid[0x1]; 10309 u8 check_user_timestamp[0x1]; 10310 u8 match_base_guid_mac[0x1]; 10311 u8 reserved_at_86[0x1a]; 10312 }; 10313 10314 struct mlx5_ifc_mcqi_reg_bits { 10315 u8 read_pending_component[0x1]; 10316 u8 reserved_at_1[0xf]; 10317 u8 component_index[0x10]; 10318 10319 u8 reserved_at_20[0x20]; 10320 10321 u8 reserved_at_40[0x1b]; 10322 u8 info_type[0x5]; 10323 10324 u8 info_size[0x20]; 10325 10326 u8 offset[0x20]; 10327 10328 u8 reserved_at_a0[0x10]; 10329 u8 data_size[0x10]; 10330 10331 u8 data[0][0x20]; 10332 }; 10333 10334 struct mlx5_ifc_mcc_reg_bits { 10335 u8 reserved_at_0[0x4]; 10336 u8 time_elapsed_since_last_cmd[0xc]; 10337 u8 reserved_at_10[0x8]; 10338 u8 instruction[0x8]; 10339 10340 u8 reserved_at_20[0x10]; 10341 u8 component_index[0x10]; 10342 10343 u8 reserved_at_40[0x8]; 10344 u8 update_handle[0x18]; 10345 10346 u8 handle_owner_type[0x4]; 10347 u8 handle_owner_host_id[0x4]; 10348 u8 reserved_at_68[0x1]; 10349 u8 control_progress[0x7]; 10350 u8 error_code[0x8]; 10351 u8 reserved_at_78[0x4]; 10352 u8 control_state[0x4]; 10353 10354 u8 component_size[0x20]; 10355 10356 u8 reserved_at_a0[0x60]; 10357 }; 10358 10359 struct mlx5_ifc_mcda_reg_bits { 10360 u8 reserved_at_0[0x8]; 10361 u8 update_handle[0x18]; 10362 10363 u8 offset[0x20]; 10364 10365 u8 reserved_at_40[0x10]; 10366 u8 size[0x10]; 10367 10368 u8 reserved_at_60[0x20]; 10369 10370 u8 data[0][0x20]; 10371 }; 10372 10373 union mlx5_ifc_ports_control_registers_document_bits { 10374 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits ib_portcntrs_attribute_grp_data; 10375 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 10376 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10377 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10378 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10379 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10380 struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp; 10381 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10382 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10383 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits eth_per_traffic_class_cong_layout; 10384 struct mlx5_ifc_eth_per_traffic_class_layout_bits eth_per_traffic_class_layout; 10385 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 10386 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits link_level_retrans_cntr_grp_date; 10387 struct mlx5_ifc_pamp_reg_bits pamp_reg; 10388 struct mlx5_ifc_paos_reg_bits paos_reg; 10389 struct mlx5_ifc_pbmc_reg_bits pbmc_reg; 10390 struct mlx5_ifc_pcap_reg_bits pcap_reg; 10391 struct mlx5_ifc_peir_reg_bits peir_reg; 10392 struct mlx5_ifc_pelc_reg_bits pelc_reg; 10393 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 10394 struct mlx5_ifc_phbr_binding_reg_bits phbr_binding_reg; 10395 struct mlx5_ifc_phbr_for_port_tclass_reg_bits phbr_for_port_tclass_reg; 10396 struct mlx5_ifc_phbr_for_prio_reg_bits phbr_for_prio_reg; 10397 struct mlx5_ifc_phrr_reg_bits phrr_reg; 10398 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10399 struct mlx5_ifc_pifr_reg_bits pifr_reg; 10400 struct mlx5_ifc_pipg_reg_bits pipg_reg; 10401 struct mlx5_ifc_plbf_reg_bits plbf_reg; 10402 struct mlx5_ifc_plib_reg_bits plib_reg; 10403 struct mlx5_ifc_pll_status_data_bits pll_status_data; 10404 struct mlx5_ifc_plpc_reg_bits plpc_reg; 10405 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 10406 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 10407 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 10408 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 10409 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 10410 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 10411 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 10412 struct mlx5_ifc_ppad_reg_bits ppad_reg; 10413 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 10414 struct mlx5_ifc_ppll_reg_bits ppll_reg; 10415 struct mlx5_ifc_pplm_reg_bits pplm_reg; 10416 struct mlx5_ifc_pplr_reg_bits pplr_reg; 10417 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 10418 struct mlx5_ifc_pspa_reg_bits pspa_reg; 10419 struct mlx5_ifc_ptas_reg_bits ptas_reg; 10420 struct mlx5_ifc_ptys_reg_bits ptys_reg; 10421 struct mlx5_ifc_pude_reg_bits pude_reg; 10422 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 10423 struct mlx5_ifc_slrg_reg_bits slrg_reg; 10424 struct mlx5_ifc_slrp_reg_bits slrp_reg; 10425 struct mlx5_ifc_sltp_reg_bits sltp_reg; 10426 u8 reserved_0[0x7880]; 10427 }; 10428 10429 union mlx5_ifc_debug_enhancements_document_bits { 10430 struct mlx5_ifc_health_buffer_bits health_buffer; 10431 u8 reserved_0[0x200]; 10432 }; 10433 10434 union mlx5_ifc_no_dram_nic_document_bits { 10435 struct mlx5_ifc_nodnic_config_reg_bits nodnic_config_reg; 10436 struct mlx5_ifc_nodnic_cq_arming_word_bits nodnic_cq_arming_word; 10437 struct mlx5_ifc_nodnic_event_word_bits nodnic_event_word; 10438 struct mlx5_ifc_nodnic_gid_filters_bits nodnic_gid_filters; 10439 struct mlx5_ifc_nodnic_mac_filters_bits nodnic_mac_filters; 10440 struct mlx5_ifc_nodnic_port_config_reg_bits nodnic_port_config_reg; 10441 struct mlx5_ifc_nodnic_ring_config_reg_bits nodnic_ring_config_reg; 10442 struct mlx5_ifc_nodnic_ring_doorbell_bits nodnic_ring_doorbell; 10443 u8 reserved_0[0x3160]; 10444 }; 10445 10446 union mlx5_ifc_uplink_pci_interface_document_bits { 10447 struct mlx5_ifc_initial_seg_bits initial_seg; 10448 struct mlx5_ifc_vendor_specific_cap_bits vendor_specific_cap; 10449 u8 reserved_0[0x20120]; 10450 }; 10451 10452 struct mlx5_ifc_qpdpm_dscp_reg_bits { 10453 u8 e[0x1]; 10454 u8 reserved_at_01[0x0b]; 10455 u8 prio[0x04]; 10456 }; 10457 10458 struct mlx5_ifc_qpdpm_reg_bits { 10459 u8 reserved_at_0[0x8]; 10460 u8 local_port[0x8]; 10461 u8 reserved_at_10[0x10]; 10462 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 10463 }; 10464 10465 struct mlx5_ifc_qpts_reg_bits { 10466 u8 reserved_at_0[0x8]; 10467 u8 local_port[0x8]; 10468 u8 reserved_at_10[0x2d]; 10469 u8 trust_state[0x3]; 10470 }; 10471 10472 struct mlx5_ifc_mfrl_reg_bits { 10473 u8 reserved_at_0[0x38]; 10474 u8 reset_level[0x8]; 10475 }; 10476 10477 enum { 10478 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTCAP = 0x9009, 10479 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTECR = 0x9109, 10480 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTMP = 0x900a, 10481 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTWE = 0x900b, 10482 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTBR = 0x900f, 10483 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTEWE = 0x910b, 10484 MLX5_MAX_TEMPERATURE = 16, 10485 }; 10486 10487 struct mlx5_ifc_mtbr_temp_record_bits { 10488 u8 max_temperature[0x10]; 10489 u8 temperature[0x10]; 10490 }; 10491 10492 struct mlx5_ifc_mtbr_reg_bits { 10493 u8 reserved_at_0[0x14]; 10494 u8 base_sensor_index[0xc]; 10495 10496 u8 reserved_at_20[0x18]; 10497 u8 num_rec[0x8]; 10498 10499 u8 reserved_at_40[0x40]; 10500 10501 struct mlx5_ifc_mtbr_temp_record_bits temperature_record[MLX5_MAX_TEMPERATURE]; 10502 }; 10503 10504 struct mlx5_ifc_mtbr_reg_ext_bits { 10505 u8 reserved_at_0[0x14]; 10506 u8 base_sensor_index[0xc]; 10507 10508 u8 reserved_at_20[0x18]; 10509 u8 num_rec[0x8]; 10510 10511 u8 reserved_at_40[0x40]; 10512 10513 struct mlx5_ifc_mtbr_temp_record_bits temperature_record[MLX5_MAX_TEMPERATURE]; 10514 }; 10515 10516 struct mlx5_ifc_mtcap_bits { 10517 u8 reserved_at_0[0x19]; 10518 u8 sensor_count[0x7]; 10519 10520 u8 reserved_at_20[0x19]; 10521 u8 internal_sensor_count[0x7]; 10522 10523 u8 sensor_map[0x40]; 10524 }; 10525 10526 struct mlx5_ifc_mtcap_ext_bits { 10527 u8 reserved_at_0[0x19]; 10528 u8 sensor_count[0x7]; 10529 10530 u8 reserved_at_20[0x20]; 10531 10532 u8 sensor_map[0x40]; 10533 }; 10534 10535 struct mlx5_ifc_mtecr_bits { 10536 u8 reserved_at_0[0x4]; 10537 u8 last_sensor[0xc]; 10538 u8 reserved_at_10[0x4]; 10539 u8 sensor_count[0xc]; 10540 10541 u8 reserved_at_20[0x19]; 10542 u8 internal_sensor_count[0x7]; 10543 10544 u8 sensor_map_0[0x20]; 10545 10546 u8 reserved_at_60[0x2a0]; 10547 }; 10548 10549 struct mlx5_ifc_mtecr_ext_bits { 10550 u8 reserved_at_0[0x4]; 10551 u8 last_sensor[0xc]; 10552 u8 reserved_at_10[0x4]; 10553 u8 sensor_count[0xc]; 10554 10555 u8 reserved_at_20[0x20]; 10556 10557 u8 sensor_map_0[0x20]; 10558 10559 u8 reserved_at_60[0x2a0]; 10560 }; 10561 10562 struct mlx5_ifc_mtewe_bits { 10563 u8 reserved_at_0[0x4]; 10564 u8 last_sensor[0xc]; 10565 u8 reserved_at_10[0x4]; 10566 u8 sensor_count[0xc]; 10567 10568 u8 sensor_warning_0[0x20]; 10569 10570 u8 reserved_at_40[0x2a0]; 10571 }; 10572 10573 struct mlx5_ifc_mtewe_ext_bits { 10574 u8 reserved_at_0[0x4]; 10575 u8 last_sensor[0xc]; 10576 u8 reserved_at_10[0x4]; 10577 u8 sensor_count[0xc]; 10578 10579 u8 sensor_warning_0[0x20]; 10580 10581 u8 reserved_at_40[0x2a0]; 10582 }; 10583 10584 struct mlx5_ifc_mtmp_bits { 10585 u8 reserved_at_0[0x14]; 10586 u8 sensor_index[0xc]; 10587 10588 u8 reserved_at_20[0x10]; 10589 u8 temperature[0x10]; 10590 10591 u8 mte[0x1]; 10592 u8 mtr[0x1]; 10593 u8 reserved_at_42[0xe]; 10594 u8 max_temperature[0x10]; 10595 10596 u8 tee[0x2]; 10597 u8 reserved_at_62[0xe]; 10598 u8 temperature_threshold_hi[0x10]; 10599 10600 u8 reserved_at_80[0x10]; 10601 u8 temperature_threshold_lo[0x10]; 10602 10603 u8 reserved_at_a0[0x20]; 10604 10605 u8 sensor_name_hi[0x20]; 10606 10607 u8 sensor_name_lo[0x20]; 10608 }; 10609 10610 struct mlx5_ifc_mtmp_ext_bits { 10611 u8 reserved_at_0[0x14]; 10612 u8 sensor_index[0xc]; 10613 10614 u8 reserved_at_20[0x10]; 10615 u8 temperature[0x10]; 10616 10617 u8 mte[0x1]; 10618 u8 mtr[0x1]; 10619 u8 reserved_at_42[0xe]; 10620 u8 max_temperature[0x10]; 10621 10622 u8 tee[0x2]; 10623 u8 reserved_at_62[0xe]; 10624 u8 temperature_threshold_hi[0x10]; 10625 10626 u8 reserved_at_80[0x10]; 10627 u8 temperature_threshold_lo[0x10]; 10628 10629 u8 reserved_at_a0[0x20]; 10630 10631 u8 sensor_name_hi[0x20]; 10632 10633 u8 sensor_name_lo[0x20]; 10634 }; 10635 10636 #endif /* MLX5_IFC_H */ 10637