Home
last modified time | relevance | path

Searched refs:Vn (Results 1 – 9 of 9) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
HDARMInstrNEON.td2633 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2634 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2635 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2637 let TwoOperandAliasConstraint = "$Vn = $Vd";
2646 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2647 OpcodeStr, "$Vd, $Vn, $Vm", "",
2648 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>{
2650 let TwoOperandAliasConstraint = "$Vn = $Vd";
2658 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2659 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
[all …]
HDARMInstrFormats.td2422 bits<5> Vn;
2427 let Inst{19-16} = Vn{3-0};
2428 let Inst{7} = Vn{4};
2437 Dt, "$Vd, $Vn, $Vm", "", pattern> {
2439 bits<5> Vn;
2445 let Inst{19-16} = Vn{3-0};
2446 let Inst{7} = Vn{4};
2467 bits<5> Vn;
2473 let Inst{19-16} = Vn{3-0};
2474 let Inst{7} = Vn{4};
[all …]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
HDAArch64InstrFormats.td5936 def : InstAlias<asm # "\t$Vd.4h, $Vn.4h, #0",
5937 (!cast<Instruction>(NAME # v4i16rz) V64:$Vd, V64:$Vn), 0>;
5938 def : InstAlias<asm # "\t$Vd.8h, $Vn.8h, #0",
5939 (!cast<Instruction>(NAME # v8i16rz) V128:$Vd, V128:$Vn), 0>;
5941 def : InstAlias<asm # "\t$Vd.2s, $Vn.2s, #0",
5942 (!cast<Instruction>(NAME # v2i32rz) V64:$Vd, V64:$Vn), 0>;
5943 def : InstAlias<asm # "\t$Vd.4s, $Vn.4s, #0",
5944 (!cast<Instruction>(NAME # v4i32rz) V128:$Vd, V128:$Vn), 0>;
5945 def : InstAlias<asm # "\t$Vd.2d, $Vn.2d, #0",
5946 (!cast<Instruction>(NAME # v2i64rz) V128:$Vd, V128:$Vn), 0>;
[all …]
HDAArch64InstrInfo.td3745 def : InstAlias<"mvn{ $Vd.8b, $Vn.8b|.8b $Vd, $Vn}",
3746 (NOTv8i8 V64:$Vd, V64:$Vn)>;
3747 def : InstAlias<"mvn{ $Vd.16b, $Vn.16b|.16b $Vd, $Vn}",
3748 (NOTv16i8 V128:$Vd, V128:$Vn)>;
5225 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
5230 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
6606 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
6607 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
6608 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
6609 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
[all …]
HDAArch64SchedCyclone.td332 // ORR.16b Vd,Vn,Vn
HDSVEInstrFormats.td5468 : I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, srcRegtype:$Vn),
5469 asm, "\t$Zd, $Pg/m, $Vn",
5473 bits<5> Vn;
5479 let Inst{9-5} = Vn;
5493 def : InstAlias<"mov $Zd, $Pg/m, $Vn",
5494 (!cast<Instruction>(NAME # _B) ZPR8:$Zd, PPR3bAny:$Pg, FPR8:$Vn), 1>;
5495 def : InstAlias<"mov $Zd, $Pg/m, $Vn",
5496 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPR3bAny:$Pg, FPR16:$Vn), 1>;
5497 def : InstAlias<"mov $Zd, $Pg/m, $Vn",
5498 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPR3bAny:$Pg, FPR32:$Vn), 1>;
[all …]
/freebsd-11-stable/contrib/gcc/doc/
HDtree-ssa.texi1668 may-aliases(T) = @{ V1, V2, V3, ..., Vn @}
1680 may-aliases(Vn) = @{ T @}
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
HDARMDisassembler.cpp5785 unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0); in DecodeNEONComplexLane64Instruction() local
5786 Vn |= (fieldFromInstruction(Insn, 7, 1) << 4); in DecodeNEONComplexLane64Instruction()
5800 if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder))) in DecodeNEONComplexLane64Instruction()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
HDSystemZInstrFormats.td173 // bits<5> Vn : vector register input or output for operand n