1 /*-
2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29
30
31 /*
32 * USB phy driver for Tegra SoCs.
33 */
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/bus.h>
37 #include <sys/kernel.h>
38 #include <sys/module.h>
39 #include <sys/malloc.h>
40 #include <sys/rman.h>
41
42 #include <machine/bus.h>
43 #include <machine/fdt.h>
44
45 #include <dev/extres/clk/clk.h>
46 #include <dev/extres/hwreset/hwreset.h>
47 #include <dev/extres/phy/phy.h>
48 #include <dev/extres/regulator/regulator.h>
49 #include <dev/fdt/fdt_common.h>
50 #include <dev/fdt/fdt_pinctrl.h>
51 #include <dev/ofw/openfirm.h>
52 #include <dev/ofw/ofw_bus.h>
53 #include <dev/ofw/ofw_bus_subr.h>
54
55 #include "phynode_if.h"
56
57 #define CTRL_ICUSB_CTRL 0x15c
58 #define ICUSB_CTR_IC_ENB1 (1 << 3)
59
60 #define CTRL_USB_USBMODE 0x1f8
61 #define USB_USBMODE_MASK (3 << 0)
62 #define USB_USBMODE_HOST (3 << 0)
63 #define USB_USBMODE_DEVICE (2 << 0)
64
65 #define CTRL_USB_HOSTPC1_DEVLC 0x1b4
66 #define USB_HOSTPC1_DEVLC_PTS(x) (((x) & 0x7) << 29)
67 #define USB_HOSTPC1_DEVLC_STS (1 << 28)
68 #define USB_HOSTPC1_DEVLC_PHCD (1 << 22)
69
70
71 #define IF_USB_SUSP_CTRL 0x400
72 #define FAST_WAKEUP_RESP (1 << 26)
73 #define UTMIP_SUSPL1_SET (1 << 25)
74 #define USB_WAKEUP_DEBOUNCE_COUNT(x) (((x) & 0x7) << 16)
75 #define USB_SUSP_SET (1 << 14)
76 #define UTMIP_PHY_ENB (1 << 12)
77 #define UTMIP_RESET (1 << 11)
78 #define USB_SUSP_POL (1 << 10)
79 #define USB_PHY_CLK_VALID_INT_ENB (1 << 9)
80 #define USB_PHY_CLK_VALID_INT_STS (1 << 8)
81 #define USB_PHY_CLK_VALID (1 << 7)
82 #define USB_CLKEN (1 << 6)
83 #define USB_SUSP_CLR (1 << 5)
84 #define USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
85 #define USB_WAKE_ON_CNNT_EN_DEV (1 << 3)
86 #define USB_WAKE_ON_RESUME_EN (1 << 2)
87 #define USB_WAKEUP_INT_ENB (1 << 1)
88 #define USB_WAKEUP_INT_STS (1 << 0)
89
90 #define IF_USB_PHY_VBUS_SENSORS 0x404
91 #define B_SESS_END_SW_VALUE (1 << 4)
92 #define B_SESS_END_SW_EN (1 << 3)
93
94
95 #define UTMIP_XCVR_CFG0 0x808
96 #define UTMIP_XCVR_HSSLEW_MSB(x) ((((x) & 0x1fc) >> 2) << 25)
97 #define UTMIP_XCVR_SETUP_MSB(x) ((((x) & 0x70) >> 4) << 22)
98 #define UTMIP_XCVR_LSBIAS_SEL (1 << 21)
99 #define UTMIP_XCVR_DISCON_METHOD (1 << 20)
100 #define UTMIP_FORCE_PDZI_POWERUP (1 << 19)
101 #define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18)
102 #define UTMIP_FORCE_PD2_POWERUP (1 << 17)
103 #define UTMIP_FORCE_PD2_POWERDOWN (1 << 16)
104 #define UTMIP_FORCE_PD_POWERUP (1 << 15)
105 #define UTMIP_FORCE_PD_POWERDOWN (1 << 14)
106 #define UTMIP_XCVR_TERMEN (1 << 13)
107 #define UTMIP_XCVR_HSLOOPBACK (1 << 12)
108 #define UTMIP_XCVR_LSFSLEW(x) (((x) & 0x3) << 10)
109 #define UTMIP_XCVR_LSRSLEW(x) (((x) & 0x3) << 8)
110 #define UTMIP_XCVR_FSSLEW(x) (((x) & 0x3) << 6)
111 #define UTMIP_XCVR_HSSLEW(x) (((x) & 0x3) << 4)
112 #define UTMIP_XCVR_SETUP(x) (((x) & 0xf) << 0)
113
114 #define UTMIP_BIAS_CFG0 0x80C
115 #define UTMIP_IDDIG_C_VAL (1 << 30)
116 #define UTMIP_IDDIG_C_SEL (1 << 29)
117 #define UTMIP_IDDIG_B_VAL (1 << 28)
118 #define UTMIP_IDDIG_B_SEL (1 << 27)
119 #define UTMIP_IDDIG_A_VAL (1 << 26)
120 #define UTMIP_IDDIG_A_SEL (1 << 25)
121 #define UTMIP_HSDISCON_LEVEL_MSB(x) ((((x) & 0x4) >> 2) << 24)
122 #define UTMIP_IDPD_VAL (1 << 23)
123 #define UTMIP_IDPD_SEL (1 << 22)
124 #define UTMIP_IDDIG_VAL (1 << 21)
125 #define UTMIP_IDDIG_SEL (1 << 20)
126 #define UTMIP_GPI_VAL (1 << 19)
127 #define UTMIP_GPI_SEL (1 << 18)
128 #define UTMIP_ACTIVE_TERM_OFFSET(x) (((x) & 0x7) << 15)
129 #define UTMIP_ACTIVE_PULLUP_OFFSET(x) (((x) & 0x7) << 12)
130 #define UTMIP_OTGPD (1 << 11)
131 #define UTMIP_BIASPD (1 << 10)
132 #define UTMIP_VBUS_LEVEL_LEVEL(x) (((x) & 0x3) << 8)
133 #define UTMIP_SESS_LEVEL_LEVEL(x) (((x) & 0x3) << 6)
134 #define UTMIP_HSCHIRP_LEVEL(x) (((x) & 0x3) << 4)
135 #define UTMIP_HSDISCON_LEVEL(x) (((x) & 0x3) << 2)
136 #define UTMIP_HSSQUELCH_LEVEL(x) (((x) & 0x3) << 0)
137
138
139 #define UTMIP_HSRX_CFG0 0x810
140 #define UTMIP_KEEP_PATT_ON_ACTIVE(x) (((x) & 0x3) << 30)
141 #define UTMIP_ALLOW_CONSEC_UPDN (1 << 29)
142 #define UTMIP_REALIGN_ON_NEW_PKT (1 << 28)
143 #define UTMIP_PCOUNT_UPDN_DIV(x) (((x) & 0xf) << 24)
144 #define UTMIP_SQUELCH_EOP_DLY(x) (((x) & 0x7) << 21)
145 #define UTMIP_NO_STRIPPING (1 << 20)
146 #define UTMIP_IDLE_WAIT(x) (((x) & 0x1f) << 15)
147 #define UTMIP_ELASTIC_LIMIT(x) (((x) & 0x1f) << 10)
148 #define UTMIP_ELASTIC_OVERRUN_DISABLE (1 << 9)
149 #define UTMIP_ELASTIC_UNDERRUN_DISABLE (1 << 8)
150 #define UTMIP_PASS_CHIRP (1 << 7)
151 #define UTMIP_PASS_FEEDBACK (1 << 6)
152 #define UTMIP_PCOUNT_INERTIA(x) (((x) & 0x3) << 4)
153 #define UTMIP_PHASE_ADJUST(x) (((x) & 0x3) << 2)
154 #define UTMIP_THREE_SYNCBITS (1 << 1)
155 #define UTMIP_USE4SYNC_TRAN (1 << 0)
156
157 #define UTMIP_HSRX_CFG1 0x814
158 #define UTMIP_HS_SYNC_START_DLY(x) (((x) & 0x1F) << 1)
159 #define UTMIP_HS_ALLOW_KEEP_ALIVE (1 << 0)
160
161 #define UTMIP_TX_CFG0 0x820
162 #define UTMIP_FS_PREAMBLE_J (1 << 19)
163 #define UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE (1 << 18)
164 #define UTMIP_FS_PREAMBLE_OUTPUT_ENABLE (1 << 17)
165 #define UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR (1 << 16)
166 #define UTMIP_HS_READY_WAIT_FOR_VALID (1 << 15)
167 #define UTMIP_HS_TX_IPG_DLY(x) (((x) & 0x1f) << 10)
168 #define UTMIP_HS_DISCON_EOP_ONLY (1 << 9)
169 #define UTMIP_HS_DISCON_DISABLE (1 << 8)
170 #define UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE (1 << 7)
171 #define UTMIP_HS_PREAMBLE_OUTPUT_ENABLE (1 << 6)
172 #define UTMIP_SIE_RESUME_ON_LINESTATE (1 << 5)
173 #define UTMIP_SOF_ON_NO_STUFF (1 << 4)
174 #define UTMIP_SOF_ON_NO_ENCODE (1 << 3)
175 #define UTMIP_NO_STUFFING (1 << 2)
176 #define UTMIP_NO_ENCODING (1 << 1)
177 #define UTMIP_NO_SYNC_NO_EOP (1 << 0)
178
179 #define UTMIP_MISC_CFG0 0x824
180 #define UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
181 #define UTMIP_DPDM_OBSERVE (1 << 26)
182 #define UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON (1 << 25)
183 #define UTMIP_ALLOW_LS_ON_SOFT_DISCON (1 << 24)
184 #define UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP (1 << 23)
185 #define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22)
186 #define UTMIP_LS_TO_FS_SKIP_4MS (1 << 21)
187 #define UTMIP_INJECT_ERROR_TYPE(x) (((x) & 0x3) << 19)
188 #define UTMIP_FORCE_HS_CLOCK_ON (1 << 18)
189 #define UTMIP_DISABLE_HS_TERM (1 << 17)
190 #define UTMIP_FORCE_HS_TERM (1 << 16)
191 #define UTMIP_DISABLE_PULLUP_DP (1 << 15)
192 #define UTMIP_DISABLE_PULLUP_DM (1 << 14)
193 #define UTMIP_DISABLE_PULLDN_DP (1 << 13)
194 #define UTMIP_DISABLE_PULLDN_DM (1 << 12)
195 #define UTMIP_FORCE_PULLUP_DP (1 << 11)
196 #define UTMIP_FORCE_PULLUP_DM (1 << 10)
197 #define UTMIP_FORCE_PULLDN_DP (1 << 9)
198 #define UTMIP_FORCE_PULLDN_DM (1 << 8)
199 #define UTMIP_STABLE_COUNT(x) (((x) & 0x7) << 5)
200 #define UTMIP_STABLE_ALL (1 << 4)
201 #define UTMIP_NO_FREE_ON_SUSPEND (1 << 3)
202 #define UTMIP_NEVER_FREE_RUNNING_TERMS (1 << 2)
203 #define UTMIP_ALWAYS_FREE_RUNNING_TERMS (1 << 1)
204 #define UTMIP_COMB_TERMS (1 << 0)
205
206 #define UTMIP_MISC_CFG1 0x828
207 #define UTMIP_PHY_XTAL_CLOCKEN (1 << 30)
208
209 #define UTMIP_DEBOUNCE_CFG0 0x82C
210 #define UTMIP_BIAS_DEBOUNCE_B(x) (((x) & 0xffff) << 16)
211 #define UTMIP_BIAS_DEBOUNCE_A(x) (((x) & 0xffff) << 0)
212
213 #define UTMIP_BAT_CHRG_CFG0 0x830
214 #define UTMIP_CHRG_DEBOUNCE_TIMESCALE(x) (((x) & 0x1f) << 8)
215 #define UTMIP_OP_I_SRC_ENG (1 << 5)
216 #define UTMIP_ON_SRC_ENG (1 << 4)
217 #define UTMIP_OP_SRC_ENG (1 << 3)
218 #define UTMIP_ON_SINK_ENG (1 << 2)
219 #define UTMIP_OP_SINK_ENG (1 << 1)
220 #define UTMIP_PD_CHRG (1 << 0)
221
222 #define UTMIP_SPARE_CFG0 0x834
223 #define FUSE_HS_IREF_CAP_CFG (1 << 7)
224 #define FUSE_HS_SQUELCH_LEVEL (1 << 6)
225 #define FUSE_SPARE (1 << 5)
226 #define FUSE_TERM_RANGE_ADJ_SEL (1 << 4)
227 #define FUSE_SETUP_SEL (1 << 3)
228 #define HS_RX_LATE_SQUELCH (1 << 2)
229 #define HS_RX_FLUSH_ALAP (1 << 1)
230 #define HS_RX_IPG_ERROR_ENABLE (1 << 0)
231
232 #define UTMIP_XCVR_CFG1 0x838
233 #define UTMIP_XCVR_RPU_RANGE_ADJ(x) (((x) & 0x3) << 26)
234 #define UTMIP_XCVR_HS_IREF_CAP(x) (((x) & 0x3) << 24)
235 #define UTMIP_XCVR_SPARE(x) (((x) & 0x3) << 22)
236 #define UTMIP_XCVR_TERM_RANGE_ADJ(x) (((x) & 0xf) << 18)
237 #define UTMIP_RCTRL_SW_SET (1 << 17)
238 #define UTMIP_RCTRL_SW_VAL(x) (((x) & 0x1f) << 12)
239 #define UTMIP_TCTRL_SW_SET (1 << 11)
240 #define UTMIP_TCTRL_SW_VAL(x) (((x) & 0x1f) << 6)
241 #define UTMIP_FORCE_PDDR_POWERUP (1 << 5)
242 #define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4)
243 #define UTMIP_FORCE_PDCHRP_POWERUP (1 << 3)
244 #define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2)
245 #define UTMIP_FORCE_PDDISC_POWERUP (1 << 1)
246 #define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0)
247
248 #define UTMIP_BIAS_CFG1 0x83c
249 #define UTMIP_BIAS_DEBOUNCE_TIMESCALE(x) (((x) & 0x3f) << 8)
250 #define UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3)
251 #define UTMIP_VBUS_WAKEUP_POWERDOWN (1 << 2)
252 #define UTMIP_FORCE_PDTRK_POWERUP (1 << 1)
253 #define UTMIP_FORCE_PDTRK_POWERDOWN (1 << 0)
254
255 static int usbpby_enable_cnt;
256
257 enum usb_ifc_type {
258 USB_IFC_TYPE_UNKNOWN = 0,
259 USB_IFC_TYPE_UTMI,
260 USB_IFC_TYPE_ULPI
261 };
262
263 enum usb_dr_mode {
264 USB_DR_MODE_UNKNOWN = 0,
265 USB_DR_MODE_DEVICE,
266 USB_DR_MODE_HOST,
267 USB_DR_MODE_OTG
268 };
269
270 struct usbphy_softc {
271 device_t dev;
272 struct resource *mem_res;
273 struct resource *pads_res;
274 clk_t clk_reg;
275 clk_t clk_pads;
276 clk_t clk_pllu;
277 regulator_t supply_vbus;
278 hwreset_t reset_usb;
279 hwreset_t reset_pads;
280 enum usb_ifc_type ifc_type;
281 enum usb_dr_mode dr_mode;
282 bool have_utmi_regs;
283
284 /* UTMI params */
285 int hssync_start_delay;
286 int elastic_limit;
287 int idle_wait_delay;
288 int term_range_adj;
289 int xcvr_lsfslew;
290 int xcvr_lsrslew;
291 int xcvr_hsslew;
292 int hssquelch_level;
293 int hsdiscon_level;
294 int xcvr_setup;
295 int xcvr_setup_use_fuses;
296 };
297
298 static struct ofw_compat_data compat_data[] = {
299 {"nvidia,tegra30-usb-phy", 1},
300 {NULL, 0},
301 };
302
303 /* Phy controller class and methods. */
304 static int usbphy_phy_enable(struct phynode *phy, bool enable);
305 static phynode_method_t usbphy_phynode_methods[] = {
306 PHYNODEMETHOD(phynode_enable, usbphy_phy_enable),
307
308 PHYNODEMETHOD_END
309 };
310 DEFINE_CLASS_1(usbphy_phynode, usbphy_phynode_class, usbphy_phynode_methods,
311 0, phynode_class);
312
313 #define RD4(sc, offs) \
314 bus_read_4(sc->mem_res, offs)
315
316 #define WR4(sc, offs, val) \
317 bus_write_4(sc->mem_res, offs, val)
318
319 static int
reg_wait(struct usbphy_softc * sc,uint32_t reg,uint32_t mask,uint32_t val)320 reg_wait(struct usbphy_softc *sc, uint32_t reg, uint32_t mask, uint32_t val)
321 {
322 int i;
323
324 for (i = 0; i < 1000; i++) {
325 if ((RD4(sc, reg) & mask) == val)
326 return (0);
327 DELAY(10);
328 }
329 return (ETIMEDOUT);
330 }
331
332 static int
usbphy_utmi_phy_clk(struct usbphy_softc * sc,bool enable)333 usbphy_utmi_phy_clk(struct usbphy_softc *sc, bool enable)
334 {
335 uint32_t val;
336 int rv;
337
338 val = RD4(sc, CTRL_USB_HOSTPC1_DEVLC);
339 if (enable)
340 val &= ~USB_HOSTPC1_DEVLC_PHCD;
341 else
342 val |= USB_HOSTPC1_DEVLC_PHCD;
343 WR4(sc, CTRL_USB_HOSTPC1_DEVLC, val);
344
345 rv = reg_wait(sc, IF_USB_SUSP_CTRL, USB_PHY_CLK_VALID,
346 enable ? USB_PHY_CLK_VALID: 0);
347 if (rv != 0) {
348 device_printf(sc->dev, "USB phy clock timeout.\n");
349 return (ETIMEDOUT);
350 }
351 return (0);
352 }
353
354 static int
usbphy_utmi_enable(struct usbphy_softc * sc)355 usbphy_utmi_enable(struct usbphy_softc *sc)
356 {
357 int rv;
358 uint32_t val;
359
360 /* Reset phy */
361 val = RD4(sc, IF_USB_SUSP_CTRL);
362 val |= UTMIP_RESET;
363 WR4(sc, IF_USB_SUSP_CTRL, val);
364
365
366 val = RD4(sc, UTMIP_TX_CFG0);
367 val |= UTMIP_FS_PREAMBLE_J;
368 WR4(sc, UTMIP_TX_CFG0, val);
369
370 val = RD4(sc, UTMIP_HSRX_CFG0);
371 val &= ~UTMIP_IDLE_WAIT(~0);
372 val &= ~UTMIP_ELASTIC_LIMIT(~0);
373 val |= UTMIP_IDLE_WAIT(sc->idle_wait_delay);
374 val |= UTMIP_ELASTIC_LIMIT(sc->elastic_limit);
375 WR4(sc, UTMIP_HSRX_CFG0, val);
376
377 val = RD4(sc, UTMIP_HSRX_CFG1);
378 val &= ~UTMIP_HS_SYNC_START_DLY(~0);
379 val |= UTMIP_HS_SYNC_START_DLY(sc->hssync_start_delay);
380 WR4(sc, UTMIP_HSRX_CFG1, val);
381
382 val = RD4(sc, UTMIP_DEBOUNCE_CFG0);
383 val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
384 val |= UTMIP_BIAS_DEBOUNCE_A(0x7530); /* For 12MHz */
385 WR4(sc, UTMIP_DEBOUNCE_CFG0, val);
386
387 val = RD4(sc, UTMIP_MISC_CFG0);
388 val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
389 WR4(sc, UTMIP_MISC_CFG0, val);
390
391 if (sc->dr_mode == USB_DR_MODE_DEVICE) {
392 val = RD4(sc,IF_USB_SUSP_CTRL);
393 val &= ~USB_WAKE_ON_CNNT_EN_DEV;
394 val &= ~USB_WAKE_ON_DISCON_EN_DEV;
395 WR4(sc, IF_USB_SUSP_CTRL, val);
396
397 val = RD4(sc, UTMIP_BAT_CHRG_CFG0);
398 val &= ~UTMIP_PD_CHRG;
399 WR4(sc, UTMIP_BAT_CHRG_CFG0, val);
400 } else {
401 val = RD4(sc, UTMIP_BAT_CHRG_CFG0);
402 val |= UTMIP_PD_CHRG;
403 WR4(sc, UTMIP_BAT_CHRG_CFG0, val);
404 }
405
406 usbpby_enable_cnt++;
407 if (usbpby_enable_cnt == 1) {
408 rv = hwreset_deassert(sc->reset_pads);
409 if (rv != 0) {
410 device_printf(sc->dev,
411 "Cannot unreset 'utmi-pads' reset\n");
412 return (rv);
413 }
414 rv = clk_enable(sc->clk_pads);
415 if (rv != 0) {
416 device_printf(sc->dev,
417 "Cannot enable 'utmi-pads' clock\n");
418 return (rv);
419 }
420
421 val = bus_read_4(sc->pads_res, UTMIP_BIAS_CFG0);
422 val &= ~UTMIP_OTGPD;
423 val &= ~UTMIP_BIASPD;
424 val &= ~UTMIP_HSSQUELCH_LEVEL(~0);
425 val &= ~UTMIP_HSDISCON_LEVEL(~0);
426 val &= ~UTMIP_HSDISCON_LEVEL_MSB(~0);
427 val |= UTMIP_HSSQUELCH_LEVEL(sc->hssquelch_level);
428 val |= UTMIP_HSDISCON_LEVEL(sc->hsdiscon_level);
429 val |= UTMIP_HSDISCON_LEVEL_MSB(sc->hsdiscon_level);
430 bus_write_4(sc->pads_res, UTMIP_BIAS_CFG0, val);
431
432 rv = clk_disable(sc->clk_pads);
433 if (rv != 0) {
434 device_printf(sc->dev,
435 "Cannot disable 'utmi-pads' clock\n");
436 return (rv);
437 }
438 }
439
440 val = RD4(sc, UTMIP_XCVR_CFG0);
441 val &= ~UTMIP_FORCE_PD_POWERDOWN;
442 val &= ~UTMIP_FORCE_PD2_POWERDOWN ;
443 val &= ~UTMIP_FORCE_PDZI_POWERDOWN;
444 val &= ~UTMIP_XCVR_LSBIAS_SEL;
445 val &= ~UTMIP_XCVR_LSFSLEW(~0);
446 val &= ~UTMIP_XCVR_LSRSLEW(~0);
447 val &= ~UTMIP_XCVR_HSSLEW(~0);
448 val &= ~UTMIP_XCVR_HSSLEW_MSB(~0);
449 val |= UTMIP_XCVR_LSFSLEW(sc->xcvr_lsfslew);
450 val |= UTMIP_XCVR_LSRSLEW(sc->xcvr_lsrslew);
451 val |= UTMIP_XCVR_HSSLEW(sc->xcvr_hsslew);
452 val |= UTMIP_XCVR_HSSLEW_MSB(sc->xcvr_hsslew);
453 if (!sc->xcvr_setup_use_fuses) {
454 val &= ~UTMIP_XCVR_SETUP(~0);
455 val &= ~UTMIP_XCVR_SETUP_MSB(~0);
456 val |= UTMIP_XCVR_SETUP(sc->xcvr_setup);
457 val |= UTMIP_XCVR_SETUP_MSB(sc->xcvr_setup);
458 }
459 WR4(sc, UTMIP_XCVR_CFG0, val);
460
461 val = RD4(sc, UTMIP_XCVR_CFG1);
462 val &= ~UTMIP_FORCE_PDDISC_POWERDOWN;
463 val &= ~UTMIP_FORCE_PDCHRP_POWERDOWN;
464 val &= ~UTMIP_FORCE_PDDR_POWERDOWN;
465 val &= ~UTMIP_XCVR_TERM_RANGE_ADJ(~0);
466 val |= UTMIP_XCVR_TERM_RANGE_ADJ(sc->term_range_adj);
467 WR4(sc, UTMIP_XCVR_CFG1, val);
468
469
470 val = RD4(sc, UTMIP_BIAS_CFG1);
471 val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
472 val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
473 WR4(sc, UTMIP_BIAS_CFG1, val);
474
475 val = RD4(sc, UTMIP_SPARE_CFG0);
476 if (sc->xcvr_setup_use_fuses)
477 val |= FUSE_SETUP_SEL;
478 else
479 val &= ~FUSE_SETUP_SEL;
480 WR4(sc, UTMIP_SPARE_CFG0, val);
481
482 val = RD4(sc, IF_USB_SUSP_CTRL);
483 val |= UTMIP_PHY_ENB;
484 WR4(sc, IF_USB_SUSP_CTRL, val);
485
486 val = RD4(sc, IF_USB_SUSP_CTRL);
487 val &= ~UTMIP_RESET;
488 WR4(sc, IF_USB_SUSP_CTRL, val);
489
490 usbphy_utmi_phy_clk(sc, true);
491
492 val = RD4(sc, CTRL_USB_USBMODE);
493 val &= ~USB_USBMODE_MASK;
494 if (sc->dr_mode == USB_DR_MODE_HOST)
495 val |= USB_USBMODE_HOST;
496 else
497 val |= USB_USBMODE_DEVICE;
498 WR4(sc, CTRL_USB_USBMODE, val);
499
500 val = RD4(sc, CTRL_USB_HOSTPC1_DEVLC);
501 val &= ~USB_HOSTPC1_DEVLC_PTS(~0);
502 val |= USB_HOSTPC1_DEVLC_PTS(0);
503 WR4(sc, CTRL_USB_HOSTPC1_DEVLC, val);
504
505 return (0);
506 }
507
508 static int
usbphy_utmi_disable(struct usbphy_softc * sc)509 usbphy_utmi_disable(struct usbphy_softc *sc)
510 {
511 int rv;
512 uint32_t val;
513
514 usbphy_utmi_phy_clk(sc, false);
515
516 if (sc->dr_mode == USB_DR_MODE_DEVICE) {
517 val = RD4(sc, IF_USB_SUSP_CTRL);
518 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
519 val |= USB_WAKE_ON_CNNT_EN_DEV;
520 val |= USB_WAKEUP_DEBOUNCE_COUNT(5);
521 WR4(sc, IF_USB_SUSP_CTRL, val);
522 }
523
524 val = RD4(sc, IF_USB_SUSP_CTRL);
525 val |= UTMIP_RESET;
526 WR4(sc, IF_USB_SUSP_CTRL, val);
527
528 val = RD4(sc, UTMIP_BAT_CHRG_CFG0);
529 val |= UTMIP_PD_CHRG;
530 WR4(sc, UTMIP_BAT_CHRG_CFG0, val);
531
532 val = RD4(sc, UTMIP_XCVR_CFG0);
533 val |= UTMIP_FORCE_PD_POWERDOWN;
534 val |= UTMIP_FORCE_PD2_POWERDOWN;
535 val |= UTMIP_FORCE_PDZI_POWERDOWN;
536 WR4(sc, UTMIP_XCVR_CFG0, val);
537
538 val = RD4(sc, UTMIP_XCVR_CFG1);
539 val |= UTMIP_FORCE_PDDISC_POWERDOWN;
540 val |= UTMIP_FORCE_PDCHRP_POWERDOWN;
541 val |= UTMIP_FORCE_PDDR_POWERDOWN;
542 WR4(sc, UTMIP_XCVR_CFG1, val);
543
544 usbpby_enable_cnt--;
545 if (usbpby_enable_cnt <= 0) {
546 rv = clk_enable(sc->clk_pads);
547 if (rv != 0) {
548 device_printf(sc->dev,
549 "Cannot enable 'utmi-pads' clock\n");
550 return (rv);
551 }
552 val =bus_read_4(sc->pads_res, UTMIP_BIAS_CFG0);
553 val |= UTMIP_OTGPD;
554 val |= UTMIP_BIASPD;
555 bus_write_4(sc->pads_res, UTMIP_BIAS_CFG0, val);
556
557 rv = clk_disable(sc->clk_pads);
558 if (rv != 0) {
559 device_printf(sc->dev,
560 "Cannot disable 'utmi-pads' clock\n");
561 return (rv);
562 }
563 }
564 return (0);
565 }
566
567 static int
usbphy_phy_enable(struct phynode * phy,bool enable)568 usbphy_phy_enable(struct phynode *phy, bool enable)
569 {
570 device_t dev;
571 struct usbphy_softc *sc;
572 int rv = 0;
573
574 dev = phynode_get_device(phy);
575 sc = device_get_softc(dev);
576
577 if (sc->ifc_type != USB_IFC_TYPE_UTMI) {
578 device_printf(sc->dev,
579 "Only UTMI interface is supported.\n");
580 return (ENXIO);
581 }
582 if (enable)
583 rv = usbphy_utmi_enable(sc);
584 else
585 rv = usbphy_utmi_disable(sc);
586
587 return (rv);
588 }
589
590 static enum usb_ifc_type
usb_get_ifc_mode(device_t dev,phandle_t node,char * name)591 usb_get_ifc_mode(device_t dev, phandle_t node, char *name)
592 {
593 char *tmpstr;
594 int rv;
595 enum usb_ifc_type ret;
596
597 rv = OF_getprop_alloc(node, name, 1, (void **)&tmpstr);
598 if (rv <= 0)
599 return (USB_IFC_TYPE_UNKNOWN);
600
601 ret = USB_IFC_TYPE_UNKNOWN;
602 if (strcmp(tmpstr, "utmi") == 0)
603 ret = USB_IFC_TYPE_UTMI;
604 else if (strcmp(tmpstr, "ulpi") == 0)
605 ret = USB_IFC_TYPE_ULPI;
606 else
607 device_printf(dev, "Unsupported phy type: %s\n", tmpstr);
608 OF_prop_free(tmpstr);
609 return (ret);
610 }
611
612 static enum usb_dr_mode
usb_get_dr_mode(device_t dev,phandle_t node,char * name)613 usb_get_dr_mode(device_t dev, phandle_t node, char *name)
614 {
615 char *tmpstr;
616 int rv;
617 enum usb_dr_mode ret;
618
619 rv = OF_getprop_alloc(node, name, 1, (void **)&tmpstr);
620 if (rv <= 0)
621 return (USB_DR_MODE_UNKNOWN);
622
623 ret = USB_DR_MODE_UNKNOWN;
624 if (strcmp(tmpstr, "device") == 0)
625 ret = USB_DR_MODE_DEVICE;
626 else if (strcmp(tmpstr, "host") == 0)
627 ret = USB_DR_MODE_HOST;
628 else if (strcmp(tmpstr, "otg") == 0)
629 ret = USB_DR_MODE_OTG;
630 else
631 device_printf(dev, "Unknown dr mode: %s\n", tmpstr);
632 OF_prop_free(tmpstr);
633 return (ret);
634 }
635
636 static int
usbphy_utmi_read_params(struct usbphy_softc * sc,phandle_t node)637 usbphy_utmi_read_params(struct usbphy_softc *sc, phandle_t node)
638 {
639 int rv;
640
641 rv = OF_getencprop(node, "nvidia,hssync-start-delay",
642 &sc->hssync_start_delay, sizeof (sc->hssync_start_delay));
643 if (rv <= 0)
644 return (ENXIO);
645
646 rv = OF_getencprop(node, "nvidia,elastic-limit",
647 &sc->elastic_limit, sizeof (sc->elastic_limit));
648 if (rv <= 0)
649 return (ENXIO);
650
651 rv = OF_getencprop(node, "nvidia,idle-wait-delay",
652 &sc->idle_wait_delay, sizeof (sc->idle_wait_delay));
653 if (rv <= 0)
654 return (ENXIO);
655
656 rv = OF_getencprop(node, "nvidia,term-range-adj",
657 &sc->term_range_adj, sizeof (sc->term_range_adj));
658 if (rv <= 0)
659 return (ENXIO);
660
661 rv = OF_getencprop(node, "nvidia,xcvr-lsfslew",
662 &sc->xcvr_lsfslew, sizeof (sc->xcvr_lsfslew));
663 if (rv <= 0)
664 return (ENXIO);
665
666 rv = OF_getencprop(node, "nvidia,xcvr-lsrslew",
667 &sc->xcvr_lsrslew, sizeof (sc->xcvr_lsrslew));
668 if (rv <= 0)
669 return (ENXIO);
670
671 rv = OF_getencprop(node, "nvidia,xcvr-hsslew",
672 &sc->xcvr_hsslew, sizeof (sc->xcvr_hsslew));
673 if (rv <= 0)
674 return (ENXIO);
675
676 rv = OF_getencprop(node, "nvidia,hssquelch-level",
677 &sc->hssquelch_level, sizeof (sc->hssquelch_level));
678 if (rv <= 0)
679 return (ENXIO);
680
681 rv = OF_getencprop(node, "nvidia,hsdiscon-level",
682 &sc->hsdiscon_level, sizeof (sc->hsdiscon_level));
683 if (rv <= 0)
684 return (ENXIO);
685
686 rv = OF_getproplen(node, "nvidia,xcvr-setup-use-fuses");
687 if (rv >= 1) {
688 sc->xcvr_setup_use_fuses = 1;
689 } else {
690 rv = OF_getencprop(node, "nvidia,xcvr-setup",
691 &sc->xcvr_setup, sizeof (sc->xcvr_setup));
692 if (rv <= 0)
693 return (ENXIO);
694 }
695
696 return (0);
697 }
698
699 static int
usbphy_probe(device_t dev)700 usbphy_probe(device_t dev)
701 {
702
703 if (!ofw_bus_status_okay(dev))
704 return (ENXIO);
705
706 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
707 return (ENXIO);
708
709 device_set_desc(dev, "Tegra USB phy");
710 return (BUS_PROBE_DEFAULT);
711 }
712
713 static int
usbphy_attach(device_t dev)714 usbphy_attach(device_t dev)
715 {
716 struct usbphy_softc *sc;
717 int rid, rv;
718 phandle_t node;
719 struct phynode *phynode;
720 struct phynode_init_def phy_init;
721
722 sc = device_get_softc(dev);
723 sc->dev = dev;
724
725 rid = 0;
726 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
727 RF_ACTIVE | RF_SHAREABLE);
728 if (sc->mem_res == NULL) {
729 device_printf(dev, "Cannot allocate memory resources\n");
730 return (ENXIO);
731 }
732
733 rid = 1;
734 sc->pads_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
735 RF_ACTIVE | RF_SHAREABLE);
736 if (sc->mem_res == NULL) {
737 device_printf(dev, "Cannot allocate memory resources\n");
738 return (ENXIO);
739 }
740
741 node = ofw_bus_get_node(dev);
742
743 rv = hwreset_get_by_ofw_name(sc->dev, 0, "usb", &sc->reset_usb);
744 if (rv != 0) {
745 device_printf(dev, "Cannot get 'usb' reset\n");
746 return (ENXIO);
747 }
748 rv = hwreset_get_by_ofw_name(sc->dev, 0, "utmi-pads", &sc->reset_pads);
749 if (rv != 0) {
750 device_printf(dev, "Cannot get 'utmi-pads' reset\n");
751 return (ENXIO);
752 }
753
754 rv = clk_get_by_ofw_name(sc->dev, 0, "reg", &sc->clk_reg);
755 if (rv != 0) {
756 device_printf(sc->dev, "Cannot get 'reg' clock\n");
757 return (ENXIO);
758 }
759 rv = clk_get_by_ofw_name(sc->dev, 0, "pll_u", &sc->clk_pllu);
760 if (rv != 0) {
761 device_printf(sc->dev, "Cannot get 'pll_u' clock\n");
762 return (ENXIO);
763 }
764 rv = clk_get_by_ofw_name(sc->dev, 0, "utmi-pads", &sc->clk_pads);
765 if (rv != 0) {
766 device_printf(sc->dev, "Cannot get 'utmi-pads' clock\n");
767 return (ENXIO);
768 }
769
770 rv = hwreset_deassert(sc->reset_usb);
771 if (rv != 0) {
772 device_printf(dev, "Cannot unreset 'usb' reset\n");
773 return (ENXIO);
774 }
775
776 rv = clk_enable(sc->clk_pllu);
777 if (rv != 0) {
778 device_printf(sc->dev, "Cannot enable 'pllu' clock\n");
779 return (ENXIO);
780 }
781 rv = clk_enable(sc->clk_reg);
782 if (rv != 0) {
783 device_printf(sc->dev, "Cannot enable 'reg' clock\n");
784 return (ENXIO);
785 }
786 if (OF_hasprop(node, "nvidia,has-utmi-pad-registers"))
787 sc->have_utmi_regs = true;
788
789 sc->dr_mode = usb_get_dr_mode(dev, node, "dr_mode");
790 if (sc->dr_mode == USB_DR_MODE_UNKNOWN)
791 sc->dr_mode = USB_DR_MODE_HOST;
792
793 sc->ifc_type = usb_get_ifc_mode(dev, node, "phy_type");
794
795 /* We supports only utmi phy mode for now .... */
796 if (sc->ifc_type != USB_IFC_TYPE_UTMI) {
797 device_printf(dev, "Unsupported phy type\n");
798 return (ENXIO);
799 }
800 rv = usbphy_utmi_read_params(sc, node);
801 if (rv < 0)
802 return rv;
803
804 if (OF_hasprop(node, "vbus-supply")) {
805 rv = regulator_get_by_ofw_property(sc->dev, 0, "vbus-supply",
806 &sc->supply_vbus);
807 if (rv != 0) {
808 device_printf(sc->dev,
809 "Cannot get \"vbus\" regulator\n");
810 return (ENXIO);
811 }
812 rv = regulator_enable(sc->supply_vbus);
813 if (rv != 0) {
814 device_printf(sc->dev,
815 "Cannot enable \"vbus\" regulator\n");
816 return (rv);
817 }
818 }
819
820 /* Create and register phy. */
821 bzero(&phy_init, sizeof(phy_init));
822 phy_init.id = 1;
823 phy_init.ofw_node = node;
824 phynode = phynode_create(dev, &usbphy_phynode_class, &phy_init);
825 if (phynode == NULL) {
826 device_printf(sc->dev, "Cannot create phy\n");
827 return (ENXIO);
828 }
829 if (phynode_register(phynode) == NULL) {
830 device_printf(sc->dev, "Cannot create phy\n");
831 return (ENXIO);
832 }
833
834 return (0);
835 }
836
837 static int
usbphy_detach(device_t dev)838 usbphy_detach(device_t dev)
839 {
840
841 /* This device is always present. */
842 return (EBUSY);
843 }
844
845 static device_method_t tegra_usbphy_methods[] = {
846 /* Device interface */
847 DEVMETHOD(device_probe, usbphy_probe),
848 DEVMETHOD(device_attach, usbphy_attach),
849 DEVMETHOD(device_detach, usbphy_detach),
850
851 DEVMETHOD_END
852 };
853
854 static devclass_t tegra_usbphy_devclass;
855 static DEFINE_CLASS_0(usbphy, tegra_usbphy_driver, tegra_usbphy_methods,
856 sizeof(struct usbphy_softc));
857 EARLY_DRIVER_MODULE(tegra_usbphy, simplebus, tegra_usbphy_driver,
858 tegra_usbphy_devclass, NULL, NULL, 79);
859