| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| HD | X86TargetTransformInfo.cpp | 1932 { ISD::USUBSAT, MVT::v32i16, 1 }, in getIntrinsicInstrCost()
1933 { ISD::USUBSAT, MVT::v64i8, 1 }, in getIntrinsicInstrCost()
1944 { ISD::USUBSAT, MVT::v16i32, 2 }, // pmaxud + psubd in getIntrinsicInstrCost()
1945 { ISD::USUBSAT, MVT::v2i64, 2 }, // pmaxuq + psubq in getIntrinsicInstrCost()
1946 { ISD::USUBSAT, MVT::v4i64, 2 }, // pmaxuq + psubq in getIntrinsicInstrCost()
1947 { ISD::USUBSAT, MVT::v8i64, 2 }, // pmaxuq + psubq in getIntrinsicInstrCost()
1994 { ISD::USUBSAT, MVT::v16i16, 1 }, in getIntrinsicInstrCost()
1995 { ISD::USUBSAT, MVT::v32i8, 1 }, in getIntrinsicInstrCost()
1996 { ISD::USUBSAT, MVT::v8i32, 2 }, // pmaxud + psubd in getIntrinsicInstrCost()
2031 { ISD::USUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert in getIntrinsicInstrCost()
[all …]
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| HD | X86ISelLowering.cpp | 911 setOperationAction(ISD::USUBSAT, MVT::v16i8, Legal); in X86TargetLowering()
915 setOperationAction(ISD::USUBSAT, MVT::v8i16, Legal); in X86TargetLowering()
918 setOperationAction(ISD::USUBSAT, MVT::v4i32, Custom); in X86TargetLowering()
920 setOperationAction(ISD::USUBSAT, MVT::v2i64, Custom); in X86TargetLowering()
1291 setOperationAction(ISD::USUBSAT, MVT::v32i8, HasInt256 ? Legal : Custom); in X86TargetLowering()
1295 setOperationAction(ISD::USUBSAT, MVT::v16i16, HasInt256 ? Legal : Custom); in X86TargetLowering()
1426 setOperationAction(ISD::USUBSAT, VT, Custom); in X86TargetLowering()
1739 setOperationAction(ISD::USUBSAT, VT, Custom); in X86TargetLowering()
1823 setOperationAction(ISD::USUBSAT, VT, Legal); in X86TargetLowering()
21346 SDValue Result = DAG.getNode(ISD::USUBSAT, dl, VT, Op0, Op1); in LowerVSETCCWithSUBUS()
[all …]
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| /freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| HD | ISDOpcodes.h | 274 SSUBSAT, USUBSAT, enumerator
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| HD | LegalizeVectorOps.cpp | 458 case ISD::USUBSAT: in LegalizeOp()
946 case ISD::USUBSAT: in Expand()
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| HD | SelectionDAGDumper.cpp | 308 case ISD::USUBSAT: return "usubsat"; in getOperationName()
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| HD | LegalizeIntegerTypes.cpp | 156 case ISD::USUBSAT: Res = PromoteIntRes_ADDSUBSAT(N); break; in PromoteIntegerResult()
693 if (Opcode == ISD::UADDSAT || Opcode == ISD::USUBSAT) { in PromoteIntRes_ADDSUBSAT()
711 case ISD::USUBSAT: in PromoteIntRes_ADDSUBSAT()
731 if (Opcode == ISD::USUBSAT) { in PromoteIntRes_ADDSUBSAT()
1921 case ISD::USUBSAT: ExpandIntRes_ADDSUBSAT(N, Lo, Hi); break; in ExpandIntegerResult()
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| HD | LegalizeVectorTypes.cpp | 128 case ISD::USUBSAT: in ScalarizeVectorResult()
938 case ISD::USUBSAT: in SplitVectorResult()
2729 case ISD::USUBSAT: in WidenVectorResult()
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| HD | SelectionDAG.cpp | 4806 case ISD::USUBSAT: return C1.usub_sat(C2); in FoldValue()
5203 case ISD::USUBSAT: in getNode()
5472 case ISD::USUBSAT: in getNode()
5497 case ISD::USUBSAT: in getNode()
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| HD | TargetLowering.cpp | 7107 if (Opcode == ISD::USUBSAT && isOperationLegalOrCustom(ISD::UMAX, VT)) { in expandAddSubSat()
7129 case ISD::USUBSAT: in expandAddSubSat()
7154 } else if (Opcode == ISD::USUBSAT) { in expandAddSubSat()
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| HD | LegalizeDAG.cpp | 1125 case ISD::USUBSAT: { in LegalizeOp()
3413 case ISD::USUBSAT: in ExpandNode()
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| HD | DAGCombiner.cpp | 1513 case ISD::USUBSAT: return visitSUBSAT(N); in visit()
2241 if (N0.getOpcode() == ISD::UMAX && hasOperation(ISD::USUBSAT, VT)) { in visitADDLike()
2248 return DAG.getNode(ISD::USUBSAT, DL, VT, N0.getOperand(0), in visitADDLike()
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| HD | SelectionDAGBuilder.cpp | 6428 setValue(&I, DAG.getNode(ISD::USUBSAT, sdl, Op1.getValueType(), Op1, Op2)); in visitIntrinsicCall()
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| HD | TargetLoweringBase.cpp | 656 setOperationAction(ISD::USUBSAT, VT, Expand); in initActions()
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| /freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Target/ |
| HD | TargetSelectionDAG.td | 397 def usubsat : SDNode<"ISD::USUBSAT" , SDTIntBinOp>;
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| HD | AArch64ISelLowering.cpp | 190 setOperationAction(ISD::USUBSAT, VT, Legal); in AArch64TargetLowering()
793 setOperationAction(ISD::USUBSAT, VT, Legal); in AArch64TargetLowering()
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| HD | ARMISelLowering.cpp | 219 for (auto Opcode : {ISD::SADDSAT, ISD::UADDSAT, ISD::SSUBSAT, ISD::USUBSAT}) in addTypeForNEON()
280 setOperationAction(ISD::USUBSAT, VT, Legal); in addMVEVectorTypes()
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