Searched refs:TargetReg (Results 1 – 6 of 6) sorted by relevance
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| HD | MipsNaClELFStreamer.cpp | 186 unsigned TargetReg = Inst.getOperand(1).getReg(); in EmitInstruction() local
187 emitMask(TargetReg, IndirectBranchMaskReg, STI); in EmitInstruction()
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| HD | X86SpeculativeLoadHardening.cpp | 987 unsigned TargetReg; in tracePredStateThroughIndirectBranches() local
1018 TargetReg = TI.getOperand(0).getReg(); in tracePredStateThroughIndirectBranches()
1038 TargetAddrSSA.AddAvailableValue(&MBB, TargetReg); in tracePredStateThroughIndirectBranches()
1105 Register TargetReg = MRI->createVirtualRegister(&X86::GR64RegClass); in tracePredStateThroughIndirectBranches() local
1110 TII->get(X86::MOV64ri32), TargetReg) in tracePredStateThroughIndirectBranches()
1118 TargetReg) in tracePredStateThroughIndirectBranches()
1130 TargetAddrSSA.AddAvailableValue(Pred, TargetReg); in tracePredStateThroughIndirectBranches()
1138 unsigned TargetReg = TargetAddrSSA.GetValueInMiddleOfBlock(&MBB); in tracePredStateThroughIndirectBranches() local
1149 .addReg(TargetReg, RegState::Kill) in tracePredStateThroughIndirectBranches()
1168 .addReg(TargetReg, RegState::Kill) in tracePredStateThroughIndirectBranches()
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| HD | MipsSEInstrInfo.cpp | 882 Register TargetReg = I->getOperand(1).getReg(); in expandEhReturn() local
890 .addReg(TargetReg) in expandEhReturn()
893 .addReg(TargetReg) in expandEhReturn()
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| HD | PPCInstrInfo.cpp | 2101 Register TargetReg = MI.getOperand(0).getReg(); in expandVSXMemPseudo() local
2103 if ((TargetReg >= PPC::F0 && TargetReg <= PPC::F31) || in expandVSXMemPseudo()
2104 (TargetReg >= PPC::VSL0 && TargetReg <= PPC::VSL31)) in expandVSXMemPseudo()
2163 Register TargetReg = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
2164 if (PPC::VSFRCRegClass.contains(TargetReg)) { in expandPostRAPseudo()
2185 Register TargetReg = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
2186 if (PPC::VSFRCRegClass.contains(TargetReg)) in expandPostRAPseudo()
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| HD | PeepholeOptimizer.cpp | 210 const SmallSet<unsigned, 2> &TargetReg,
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| HD | AArch64InstructionSelector.cpp | 2436 Register TargetReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass); in selectBrJT() local
2438 MIB.buildInstr(AArch64::JumpTableDest32, {TargetReg, ScratchReg}, in selectBrJT()
2443 MIB.buildInstr(AArch64::BR, {}, {TargetReg}); in selectBrJT()
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