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Searched refs:Sub2 (Results 1 – 5 of 5) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
HDHexagonHardwareLoops.cpp1548 unsigned Sub2 = DI->getOperand(2).getImm(); in checkForImmediate() local
1550 if (Sub2 == Hexagon::isub_lo && Sub4 == Hexagon::isub_hi) in checkForImmediate()
1552 else if (Sub2 == Hexagon::isub_hi && Sub4 == Hexagon::isub_lo) in checkForImmediate()
HDHexagonBitSimplify.cpp436 unsigned Sub1 = I.getOperand(2).getImm(), Sub2 = I.getOperand(4).getImm(); in parseRegSequence() local
442 assert((Sub1 == SubLo && Sub2 == SubHi) || (Sub1 == SubHi && Sub2 == SubLo)); in parseRegSequence()
443 if (Sub1 == SubLo && Sub2 == SubHi) { in parseRegSequence()
448 if (Sub1 == SubHi && Sub2 == SubLo) { in parseRegSequence()
HDHexagonConstPropagation.cpp1953 unsigned Sub2 = MI.getOperand(4).getImm(); in evaluate() local
1959 if (Sub2 != SubLo && Sub2 != SubHi) in evaluate()
1961 assert(Sub1 != Sub2); in evaluate()
/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/
HDCodeGenRegisters.cpp1337 const CodeGenSubRegIndex *Sub2) { in computeComposites() argument
1340 const RegMap &Img2 = SubRegAction.at(Sub2); in computeComposites()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
HDAMDGPUISelLowering.cpp1767 SDValue Sub2 = DAG.getBitcast(VT, in LowerUDIVREM64() local
1796 SDValue Sel2 = DAG.getSelectCC(DL, C6, Zero, Sub3, Sub2, ISD::SETNE); in LowerUDIVREM64()