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Searched refs:Stage (Results 1 – 25 of 31) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/MCA/Stages/
HDStage.h27 class Stage {
28 Stage *NextInSequence;
31 Stage(const Stage &Other) = delete;
32 Stage &operator=(const Stage &Other) = delete;
38 Stage() : NextInSequence(nullptr) {} in Stage() function
39 virtual ~Stage();
57 void setNextInSequence(Stage *NextStage) { in setNextInSequence()
HDInstructionTables.h28 class InstructionTables final : public Stage {
35 : Stage(), SM(Model), Masks(Model.getNumProcResourceKinds()) { in InstructionTables()
HDRetireStage.h27 class RetireStage final : public Stage {
38 : Stage(), RCU(R), PRF(F), LSU(LS) {} in RetireStage()
HDExecuteStage.h28 class ExecuteStage final : public Stage {
52 : Stage(), HWS(S), NumDispatchedOpcodes(0), NumIssuedOpcodes(0), in ExecuteStage()
HDEntryStage.h26 class EntryStage final : public Stage {
HDDispatchStage.h50 class DispatchStage final : public Stage {
HDMicroOpQueueStage.h26 class MicroOpQueueStage : public Stage {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/MCA/
HDInstruction.cpp159 assert(Stage == IS_INVALID); in dispatch()
160 Stage = IS_DISPATCHED; in dispatch()
169 assert(Stage == IS_READY); in execute()
170 Stage = IS_EXECUTING; in execute()
180 Stage = IS_EXECUTED; in execute()
184 assert(Stage == IS_READY && "Invalid internal state!"); in forceExecuted()
186 Stage = IS_EXECUTED; in forceExecuted()
199 Stage = IS_READY; in updatePending()
216 Stage = IS_PENDING; in updateDispatched()
248 Stage = IS_EXECUTED; in cycleEvent()
HDPipeline.cpp32 return any_of(Stages, [](const std::unique_ptr<Stage> &S) { in hasWorkToProcess()
55 const std::unique_ptr<Stage> &S = *I; in runCycle()
61 Stage &FirstStage = *Stages[0]; in runCycle()
66 for (const std::unique_ptr<Stage> &S : Stages) { in runCycle()
75 void Pipeline::appendStage(std::unique_ptr<Stage> S) { in appendStage()
78 Stage *Last = Stages.back().get(); in appendStage()
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
HDModuloSchedule.h92 DenseMap<MachineInstr *, int> Stage; variable
108 DenseMap<MachineInstr *, int> Stage) in ModuloSchedule() argument
110 Stage(std::move(Stage)) { in ModuloSchedule()
112 for (auto &KV : this->Stage) in ModuloSchedule()
134 auto I = Stage.find(MI); in getStage()
135 return I == Stage.end() ? -1 : I->second; in getStage()
335 MachineBasicBlock *SourceBB, unsigned Stage);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/MCA/Stages/
HDStage.cpp21 Stage::~Stage() = default;
23 void Stage::addListener(HWEventListener *Listener) { in addListener()
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/MCA/
HDInstruction.h457 enum InstrStage Stage; variable
493 : InstructionBase(D), Stage(IS_INVALID), CyclesLeft(UNKNOWN_CYCLES), in Instruction()
527 bool isDispatched() const { return Stage == IS_DISPATCHED; } in isDispatched()
528 bool isPending() const { return Stage == IS_PENDING; } in isPending()
529 bool isReady() const { return Stage == IS_READY; } in isReady()
530 bool isExecuting() const { return Stage == IS_EXECUTING; } in isExecuting()
531 bool isExecuted() const { return Stage == IS_EXECUTED; } in isExecuted()
532 bool isRetired() const { return Stage == IS_RETIRED; } in isRetired()
541 Stage = IS_RETIRED; in retire()
HDPipeline.h57 SmallVector<std::unique_ptr<Stage>, 8> Stages;
68 void appendStage(std::unique_ptr<Stage> S);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
HDGCNSchedStrategy.cpp319 MinOccupancy(StartingOccupancy), Stage(0), RegionIdx(0) { in GCNScheduleDAGMILive()
325 if (Stage == 0) { in schedule()
540 Stage++; in finalizeSchedule()
544 if (Stage > 1) { in finalizeSchedule()
569 if (Stage == 1) in finalizeSchedule()
597 } while (Stage < 2); in finalizeSchedule()
HDGCNSchedStrategy.h78 unsigned Stage; variable
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
HDModuloSchedule.cpp1591 int Stage = getStage(MI); in filterInstructions() local
1592 if (Stage == -1 || Stage >= MinStage) in filterInstructions()
1616 MachineBasicBlock *DestBB, MachineBasicBlock *SourceBB, unsigned Stage) { in moveStageBetweenBlocks() argument
1636 if (getStage(MI) != Stage) in moveStageBetweenBlocks()
1650 if (getStage(Def) == Stage) { in moveStageBetweenBlocks()
1766 unsigned Stage = Schedule.getNumStages() - 1 + I - J; in peelPrologAndEpilogs() local
1769 moveStageBetweenBlocks(Epilogs[K - 1], Epilogs[K], Stage); in peelPrologAndEpilogs()
1770 LS[Stage] = 1; in peelPrologAndEpilogs()
1899 int Stage = getStage(MI); in rewriteUsesOf() local
1900 if (Stage == -1 || LiveStages.count(MI->getParent()) == 0 || in rewriteUsesOf()
[all …]
HDRegAllocGreedy.cpp245 LiveRangeStage Stage = RS_New; member
256 return ExtraRegInfo[VirtReg.reg].Stage; in getStage()
259 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) { in setStage() argument
261 ExtraRegInfo[VirtReg.reg].Stage = Stage; in setStage()
269 if (ExtraRegInfo[Reg].Stage == RS_New) in setStage()
270 ExtraRegInfo[Reg].Stage = NewStage; in setStage()
670 ExtraRegInfo[Old].Stage = RS_Assign; in LRE_DidCloneVirtReg()
693 if (ExtraRegInfo[Reg].Stage == RS_New) in enqueue()
694 ExtraRegInfo[Reg].Stage = RS_Assign; in enqueue()
696 if (ExtraRegInfo[Reg].Stage == RS_Split) { in enqueue()
[all …]
/freebsd-11-stable/contrib/llvm-project/libcxx/include/
HDlocale896 // Stage 1
898 // Stage 2
933 // Stage 3
953 // Stage 1
955 // Stage 2
990 // Stage 3
1010 // Stage 1, nothing to do
1011 // Stage 2
1045 // Stage 3
1062 // Stage 1
[all …]
/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/
HDDFAPacketizerEmitter.cpp276 for (NfaStateTy Stage : InsnClass) { in emitForItineraries() local
286 if ((ResourceMask & Stage) == 0) in emitForItineraries()
HDSubtargetEmitter.cpp305 const Record *Stage = StageList[i]; in FormItineraryStageString() local
308 int Cycles = Stage->getValueAsInt("Cycles"); in FormItineraryStageString()
312 RecVec UnitList = Stage->getValueAsListOfDefs("Units"); in FormItineraryStageString()
321 int TimeInc = Stage->getValueAsInt("TimeInc"); in FormItineraryStageString()
324 int Kind = Stage->getValueAsInt("Kind"); in FormItineraryStageString()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
HDHexagonMCInstrInfo.cpp419 for (unsigned Stage = II[SchedClass].FirstStage + 1; in getOtherReservedSlots() local
420 Stage < II[SchedClass].LastStage; ++Stage) { in getOtherReservedSlots()
421 unsigned Units = (Stage + HexagonStages)->getUnits(); in getOtherReservedSlots()
/freebsd-11-stable/contrib/gcc/cp/
HDMake-lang.in205 # Stage hooks:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
HDARMISelDAGToDAG.cpp2672 for (unsigned Stage = 0; Stage < NumVecs; ++Stage) { in SelectMVE_VLD() local
2675 CurDAG->getMachineNode(OurOpcodes[Stage], Loc, ResultTys, Ops); in SelectMVE_VLD()
/freebsd-11-stable/contrib/bmake/mk/
HDChangeLog758 Stage*() return early if passed no args.
/freebsd-11-stable/lib/clang/libllvm/
HDMakefile770 SRCS_EXT+= MCA/Stages/Stage.cpp

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