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Searched refs:SrcVec (Results 1 – 10 of 10) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
HDR600OptimizeVectorRegisters.cpp205 Register SrcVec = BaseRSI->Instr->getOperand(0).getReg(); in RebuildVector() local
217 .addReg(SrcVec) in RebuildVector()
228 SrcVec = DstReg; in RebuildVector()
231 BuildMI(MBB, Pos, DL, TII->get(R600::COPY), Reg).addReg(SrcVec); in RebuildVector()
HDSIISelLowering.cpp3495 const MachineOperand *SrcVec = TII->getNamedOperand(MI, AMDGPU::OpName::src); in emitIndirectDst() local
3499 const TargetRegisterClass *VecRC = MRI.getRegClass(SrcVec->getReg()); in emitIndirectDst()
3506 SrcVec->getReg(), in emitIndirectDst()
3517 .add(*SrcVec) in emitIndirectDst()
3531 .addReg(SrcVec->getReg(), RegState::Undef, SubReg) // vdst in emitIndirectDst()
3534 .addReg(SrcVec->getReg(), RegState::Implicit) in emitIndirectDst()
3543 .addReg(SrcVec->getReg()) in emitIndirectDst()
3559 auto InsPt = loadM0FromVGPR(TII, MBB, MI, SrcVec->getReg(), PhiReg, in emitIndirectDst()
6094 SDValue SrcVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, in LowerINTRINSIC_WO_CHAIN() local
6097 SDValue SrcHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, SrcVec, in LowerINTRINSIC_WO_CHAIN()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
HDInstCombineVectorOps.cpp320 Value *SrcVec = EI.getVectorOperand(); in visitExtractElementInst() local
322 if (Value *V = SimplifyExtractElementInst(SrcVec, Index, in visitExtractElementInst()
340 if (SrcVec->hasOneUse()) { in visitExtractElementInst()
345 SimplifyDemandedVectorElts(SrcVec, DemandedElts, UndefElts)) { in visitExtractElementInst()
352 APInt DemandedElts = findDemandedEltsByAllUsers(SrcVec); in visitExtractElementInst()
356 SrcVec, DemandedElts, UndefElts, 0 /* Depth */, in visitExtractElementInst()
358 if (V != SrcVec) { in visitExtractElementInst()
359 SrcVec->replaceAllUsesWith(V); in visitExtractElementInst()
371 if (auto *Phi = dyn_cast<PHINode>(SrcVec)) in visitExtractElementInst()
377 if (match(SrcVec, m_BinOp(BO)) && cheapToScalarize(SrcVec, IndexC)) { in visitExtractElementInst()
[all …]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/IR/
HDVerifier.cpp2662 bool SrcVec = SrcTy->isVectorTy(); in visitUIToFPInst() local
2665 Assert(SrcVec == DstVec, in visitUIToFPInst()
2672 if (SrcVec && DstVec) in visitUIToFPInst()
2685 bool SrcVec = SrcTy->isVectorTy(); in visitSIToFPInst() local
2688 Assert(SrcVec == DstVec, in visitSIToFPInst()
2695 if (SrcVec && DstVec) in visitSIToFPInst()
2708 bool SrcVec = SrcTy->isVectorTy(); in visitFPToUIInst() local
2711 Assert(SrcVec == DstVec, in visitFPToUIInst()
2718 if (SrcVec && DstVec) in visitFPToUIInst()
2731 bool SrcVec = SrcTy->isVectorTy(); in visitFPToSIInst() local
[all …]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/ExecutionEngine/Interpreter/
HDExecution.cpp1553 GenericValue TempDst, TempSrc, SrcVec; in executeBitCastInst() local
1565 SrcVec = Src; in executeBitCastInst()
1571 SrcVec.AggregateVal.push_back(Src); in executeBitCastInst()
1592 APInt::floatToBits(SrcVec.AggregateVal[i].FloatVal); in executeBitCastInst()
1597 APInt::doubleToBits(SrcVec.AggregateVal[i].DoubleVal); in executeBitCastInst()
1600 TempSrc.AggregateVal[i].IntVal = SrcVec.AggregateVal[i].IntVal; in executeBitCastInst()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
HDX86ISelLowering.cpp7325 SDValue SrcVec = SrcExtract.getOperand(0); in getFauxShuffleMask() local
7326 EVT SrcVT = SrcVec.getValueType(); in getFauxShuffleMask()
7334 Ops.push_back(SrcVec); in getFauxShuffleMask()
9549 static SDValue createVariablePermute(MVT VT, SDValue SrcVec, SDValue IndicesVec, in createVariablePermute() argument
9566 if (SrcVec.getValueSizeInBits() != SizeInBits) { in createVariablePermute()
9567 if ((SrcVec.getValueSizeInBits() % SizeInBits) == 0) { in createVariablePermute()
9569 unsigned Scale = SrcVec.getValueSizeInBits() / SizeInBits; in createVariablePermute()
9575 createVariablePermute(VT, SrcVec, IndicesVec, DL, DAG, Subtarget), 0, in createVariablePermute()
9577 } else if (SrcVec.getValueSizeInBits() < SizeInBits) { in createVariablePermute()
9579 SrcVec = widenSubVector(VT, SrcVec, false, Subtarget, DAG, SDLoc(SrcVec)); in createVariablePermute()
[all …]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
HDHexagonISelLoweringHVX.cpp418 auto IsBuildFromExtracts = [this,&Values] (SDValue &SrcVec, in buildHvxVectorReg()
440 SrcVec = Vec; in buildHvxVectorReg()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
HDLegalizerHelper.cpp4239 Register SrcVec = Idx < NumElts ? Src0Reg : Src1Reg; in lowerShuffleVector() local
4242 auto Extract = MIRBuilder.buildExtractVectorElement(EltTy, SrcVec, IdxK); in lowerShuffleVector()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
HDAArch64ISelLowering.cpp7353 SDValue SrcVec = V1; in LowerVECTOR_SHUFFLE() local
7356 SrcVec = V2; in LowerVECTOR_SHUFFLE()
7368 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, SrcVec, SrcLaneV), in LowerVECTOR_SHUFFLE()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
HDPPCISelLowering.cpp13350 SDValue SrcVec = Ext1.getOperand(0); in DAGCombineBuildVector() local
13354 SrcVec, DAG.getIntPtrConstant(SubvecIdx, dl)); in DAGCombineBuildVector()