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Searched refs:SrcRegs (Results 1 – 7 of 7) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
HDCallLowering.cpp130 Register CallLowering::packRegs(ArrayRef<Register> SrcRegs, Type *PackedTy, in packRegs() argument
132 assert(SrcRegs.size() > 1 && "Nothing to pack"); in packRegs()
142 assert(LLTs.size() == SrcRegs.size() && "Regs / types mismatch"); in packRegs()
146 for (unsigned i = 0; i < SrcRegs.size(); ++i) { in packRegs()
148 MIRBuilder.buildInsert(NewDst, Dst, SrcRegs[i], Offsets[i]); in packRegs()
HDLegalizerHelper.cpp914 SmallVector<SmallVector<Register, 2>, 2> SrcRegs; in narrowScalar() local
916 SrcRegs.resize(MI.getNumOperands() / 2); in narrowScalar()
922 SrcRegs[i / 2]); in narrowScalar()
931 MIB.addUse(SrcRegs[j / 2][i]).add(MI.getOperand(j + 1)); in narrowScalar()
1024 SmallVector<Register, 2> SrcRegs; in narrowScalar() local
1030 SrcRegs.push_back(SrcReg); in narrowScalar()
1034 MIRBuilder.buildUnmerge(SrcRegs, MI.getOperand(1).getReg()); in narrowScalar()
1046 DstRegs.push_back(SrcRegs[i]); in narrowScalar()
1065 {SrcRegs[i], SizeInBits % NarrowTy.getScalarSizeInBits()}) in narrowScalar()
1084 SmallVector<Register, 2> SrcRegs, DstRegs; in narrowScalar() local
[all …]
HDIRTranslator.cpp975 ArrayRef<Register> SrcRegs = getOrCreateVRegs(*Src); in translateExtractValue() local
981 DstRegs[i] = SrcRegs[Idx++]; in translateExtractValue()
992 ArrayRef<Register> SrcRegs = getOrCreateVRegs(*Src); in translateInsertValue() local
1000 DstRegs[i] = SrcRegs[i]; in translateInsertValue()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
HDPeepholeOptimizer.cpp757 const SmallVectorImpl<RegSubRegPair> &SrcRegs, in insertPHI() argument
759 assert(!SrcRegs.empty() && "No sources to create a PHI instruction?"); in insertPHI()
761 const TargetRegisterClass *NewRC = MRI.getRegClass(SrcRegs[0].Reg); in insertPHI()
764 assert(SrcRegs[0].SubReg == 0 && "should not have subreg operand"); in insertPHI()
771 for (const RegSubRegPair &RegPair : SrcRegs) { in insertPHI()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
HDX86MCInstLower.cpp1458 Register SrcRegs[] = {0, 0}; in LowerPATCHABLE_EVENT_CALL() local
1468 SrcRegs[I] = getX86SubSuperRegister(Op->getReg(), 64); in LowerPATCHABLE_EVENT_CALL()
1469 if (SrcRegs[I] != DestRegs[I]) { in LowerPATCHABLE_EVENT_CALL()
1483 if (SrcRegs[I] != DestRegs[I]) in LowerPATCHABLE_EVENT_CALL()
1485 MCInstBuilder(X86::MOV64rr).addReg(DestRegs[I]).addReg(SrcRegs[I])); in LowerPATCHABLE_EVENT_CALL()
1556 Register SrcRegs[] = {0, 0, 0}; in LowerPATCHABLE_TYPED_EVENT_CALL() local
1566 SrcRegs[I] = getX86SubSuperRegister(Op->getReg(), 64); in LowerPATCHABLE_TYPED_EVENT_CALL()
1567 if (SrcRegs[I] != DestRegs[I]) { in LowerPATCHABLE_TYPED_EVENT_CALL()
1588 MCInstBuilder(X86::MOV64rr).addReg(DestRegs[I]).addReg(SrcRegs[I])); in LowerPATCHABLE_TYPED_EVENT_CALL()
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
HDCallLowering.h194 Register packRegs(ArrayRef<Register> SrcRegs, Type *PackedTy,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
HDAMDGPURegisterBankInfo.cpp1125 SmallVector<unsigned, 1> SrcRegs(OpdMapper.getVRegs(1)); in applyMappingWideLoad() local
1128 if (SrcRegs.empty()) { in applyMappingWideLoad()
1133 SrcRegs.push_back(MI.getOperand(1).getReg()); in applyMappingWideLoad()
1145 Register BasePtrReg = SrcRegs[0]; in applyMappingWideLoad()