Searched refs:Src1IsKill (Results 1 – 3 of 3) sorted by relevance
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| HD | AArch64SIMDInstrOpt.cpp | 433 unsigned Src1IsKill = getKillRegState(MI.getOperand(2).isKill()); in optimizeVectElement() local 452 .addReg(SrcReg1, Src1IsKill) in optimizeVectElement() 459 .addReg(SrcReg1, Src1IsKill) in optimizeVectElement() 464 .addReg(DupDest, Src1IsKill); in optimizeVectElement()
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| HD | AArch64FastISel.cpp | 2692 bool Src1IsKill = hasTrivialKill(Src1Val); in optimizeSelect() local 2700 Src1Reg = emitLogicalOp_ri(ISD::XOR, MVT::i32, Src1Reg, Src1IsKill, 1); in optimizeSelect() 2701 Src1IsKill = true; in optimizeSelect() 2704 Src1IsKill, Src2Reg, Src2IsKill); in optimizeSelect() 2820 bool Src1IsKill = hasTrivialKill(SI->getTrueValue()); in selectSelect() local 2829 Src2Reg = fastEmitInst_rri(Opc, RC, Src1Reg, Src1IsKill, Src2Reg, in selectSelect() 2833 unsigned ResultReg = fastEmitInst_rri(Opc, RC, Src1Reg, Src1IsKill, Src2Reg, in selectSelect() 4669 bool Src1IsKill = hasTrivialKill(I->getOperand(1)); in selectRem() local 4679 Src1Reg, Src1IsKill, Src0Reg, in selectRem() 4747 bool Src1IsKill = hasTrivialKill(I->getOperand(1)); in selectMul() local [all …]
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| HD | AArch64InstrInfo.cpp | 4182 bool Src1IsKill = MUL->getOperand(2).isKill(); in genFusedMultiply() local 4208 .addReg(SrcReg1, getKillRegState(Src1IsKill)) in genFusedMultiply() 4214 .addReg(SrcReg1, getKillRegState(Src1IsKill)) in genFusedMultiply() 4220 .addReg(SrcReg1, getKillRegState(Src1IsKill)); in genFusedMultiply() 4333 bool Src1IsKill = MUL->getOperand(2).isKill(); in genMaddR() local 4347 .addReg(SrcReg1, getKillRegState(Src1IsKill)) in genMaddR()
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