| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| HD | AArch64Schedule.td | 25 def WriteISReg : SchedWrite; // ALU of Shifted-Reg
28 def ReadISReg : SchedRead; // ALU of Shifted-Reg
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| HD | AArch64SchedA57.td | 140 // Shifted Register with Shift == 0
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| /freebsd-11-stable/contrib/llvm-project/clang/lib/Tooling/ASTDiff/ |
| HD | ASTDiff.cpp | 149 int findPositionInParent(NodeId Id, bool Shifted = false) const;
338 int SyntaxTree::Impl::findPositionInParent(NodeId Id, bool Shifted) const { in findPositionInParent()
345 if (Shifted) in findPositionInParent()
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| HD | ARMFrameLowering.cpp | 2193 unsigned Shifted = 0; in alignToARMConstant() local
2200 Shifted += 2; in alignToARMConstant()
2209 if (Shifted > 24) in alignToARMConstant()
2210 Value = Value >> (Shifted - 24); in alignToARMConstant()
2212 Value = Value << (24 - Shifted); in alignToARMConstant()
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| HD | ARMInstrThumb2.td | 54 // Shifted operands. No register controlled shifts for Thumb2.
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| /freebsd-11-stable/contrib/llvm-project/clang/lib/Format/ |
| HD | Format.cpp | 2366 auto Shifted = tooling::Replacement(FileName, NewOffset, 0, in fixCppIncludeInsertions() local
2368 Result = Result.merge(tooling::Replacements(Shifted)); in fixCppIncludeInsertions()
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Analysis/ |
| HD | ScalarEvolution.cpp | 5148 const SCEV *Shifted = SCEVShiftRewriter::rewrite(BEValue, L, *this); in createAddRecFromPHI() local
5149 const SCEV *Start = SCEVInitRewriter::rewrite(Shifted, L, *this, false); in createAddRecFromPHI()
5150 if (Shifted != getCouldNotCompute() && in createAddRecFromPHI()
5158 ValueExprMap[SCEVCallbackVH(PN, this)] = Shifted; in createAddRecFromPHI()
5159 return Shifted; in createAddRecFromPHI()
10868 const SCEV *Shifted = SE.getAddRecExpr(Operands, getLoop(), in getNumIterationsInRange() local
10870 if (const auto *ShiftedAddRec = dyn_cast<SCEVAddRecExpr>(Shifted)) in getNumIterationsInRange()
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| HD | LegalizerHelper.cpp | 1991 Register Shifted = MRI.createGenericVirtualRegister(Ty); in lower() local
1995 .addDef(Shifted) in lower()
1998 MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Shifted); in lower()
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Utils/ |
| HD | SimplifyCFG.cpp | 5520 Value *Shifted = Builder.CreateLShr(TableMask, MaskIndex, "switch.shifted"); in SwitchToLookupTable() local
5522 Shifted, Type::getInt1Ty(Mod.getContext()), "switch.lobit"); in SwitchToLookupTable()
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| HD | DAGCombiner.cpp | 552 SDValue MatchRotatePosNeg(SDValue Shifted, SDValue Pos, SDValue Neg,
6235 SDValue DAGCombiner::MatchRotatePosNeg(SDValue Shifted, SDValue Pos, in MatchRotatePosNeg() argument
6246 EVT VT = Shifted.getValueType(); in MatchRotatePosNeg()
6249 return DAG.getNode(HasPos ? PosOpcode : NegOpcode, DL, VT, Shifted, in MatchRotatePosNeg()
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| HD | PPCISelLowering.cpp | 12305 auto Shifted = DAG.getNode(ISD::SRL, DL, MVT::i64, SubNode, in generateEquivalentSub() local
12307 auto Final = Shifted; in generateEquivalentSub()
12311 Final = DAG.getNode(ISD::XOR, DL, MVT::i64, Shifted, in generateEquivalentSub()
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| /freebsd-11-stable/contrib/ncurses/misc/ |
| HD | terminfo.src | 2575 # Shifted f1-f12 give cons25 codes, rather than xterm function-keys
2859 # Scroll 0-Jump Shifted 3 0-#
8297 # Shifted Function Keys:
11891 # 1= Shifted
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