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Searched refs:ShiftOpc (Results 1 – 14 of 14) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
HDARMAddressingModes.h27 enum ShiftOpc { enum
44 inline const char *getShiftOpcStr(ShiftOpc Op) { in getShiftOpcStr()
56 inline unsigned getShiftOpcEncoding(ShiftOpc Op) { in getShiftOpcEncoding()
112 inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) { in getSORegOpc()
116 inline ShiftOpc getSORegShOp(unsigned Op) { return (ShiftOpc)(Op & 7); } in getSORegShOp()
399 inline unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO,
411 inline ShiftOpc getAM2ShiftOpc(unsigned AM2Opc) { in getAM2ShiftOpc()
412 return (ShiftOpc)((AM2Opc >> 13) & 7); in getAM2ShiftOpc()
HDARMMCCodeEmitter.cpp246 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const { in getShiftOp()
1260 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm()); in getLdStSORegOpValue()
1298 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm); in getAddrMode2OffsetOpValue()
1513 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); in getSORegRegOpValue()
1558 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm()); in getSORegImmOpValue()
1667 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm()); in getT2SORegOpValue()
HDARMInstPrinter.cpp52 static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc, in printRegImmShift()
391 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm()); in printSORegRegOperand()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
HDARMSelectionDAGInfo.h23 static inline ShiftOpc getShiftOpcForNode(unsigned Opcode) { in getShiftOpcForNode()
HDARMInstructionSelector.cpp62 bool selectShift(unsigned ShiftOpc, MachineInstrBuilder &MIB) const;
806 bool ARMInstructionSelector::selectShift(unsigned ShiftOpc, in selectShift() argument
810 MIB.addImm(ShiftOpc); in selectShift()
1062 return selectShift(ARM_AM::ShiftOpc::lsr, MIB); in select()
1064 return selectShift(ARM_AM::ShiftOpc::asr, MIB); in select()
1066 return selectShift(ARM_AM::ShiftOpc::lsl, MIB); in select()
HDARMFastISel.cpp186 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);
2695 ARM_AM::ShiftOpc Shift = (ARM_AM::ShiftOpc) ITP->Shift; in ARMEmitIntExt()
2722 ARM_AM::ShiftOpc ShiftAM = isLsl ? ARM_AM::lsl : Shift; in ARMEmitIntExt()
2768 ARM_AM::ShiftOpc ShiftTy) { in SelectShift()
HDARMISelDAGToDAG.cpp83 ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
501 ARM_AM::ShiftOpc ShOpcVal, in isShifterOpProfitable()
574 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode()); in SelectImmShifterOperand()
598 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode()); in SelectRegShifterOperand()
720 ARM_AM::ShiftOpc ShOpcVal = in SelectLdStSOReg()
800 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode()); in SelectAddrMode2OffsetReg()
1442 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode()); in SelectT2AddrModeSoReg()
2865 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(ISD::SRL); in tryV6T2BitfieldExtractOp()
HDARMBaseInstrInfo.cpp197 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); in convertToThreeAddress()
602 ARM_AM::ShiftOpc ShiftOpc = ARM_AM::getAM2ShiftOpc(OffImm); in isLdstScaledRegNotPlusLsl2() local
603 if (ShiftOpc == ARM_AM::no_shift) return false; // not scaled in isLdstScaledRegNotPlusLsl2()
604 bool SimpleScaled = (isAdd && ShiftOpc == ARM_AM::lsl && Amt == 2); in isLdstScaledRegNotPlusLsl2()
HDARMISelLowering.cpp15402 ARM_AM::ShiftOpc ShOpcVal= in getARMIndexedAddressParts()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
HDHexagonSplitDouble.cpp803 unsigned ShiftOpc = Left ? S2_asl_i_r in splitShift() local
841 BuildMI(B, MI, DL, TII->get(ShiftOpc), (Left ? LoR : TmpR)) in splitShift()
858 BuildMI(B, MI, DL, TII->get(ShiftOpc), HiR) in splitShift()
887 BuildMI(B, MI, DL, TII->get(ShiftOpc), (Left ? HiR : LoR)) in splitShift()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
HDARMAsmParser.cpp401 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
786 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
796 ARM_AM::ShiftOpc ShiftTy;
806 ARM_AM::ShiftOpc ShiftTy;
813 ARM_AM::ShiftOpc ShiftTy;
3460 CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, in CreateShiftedRegister()
3474 CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, in CreateShiftedImmediate()
3626 unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType, in CreateMem()
3644 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy, in CreatePostIdxReg()
3956 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase) in tryParseShiftRegister()
[all …]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
HDARMDisassembler.cpp1461 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; in DecodeSORegImmOperand()
1500 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; in DecodeSORegRegOperand()
1893 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; in DecodeAddrMode2IdxInstruction()
1938 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; in DecodeSORegMemOperand()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
HDAArch64ISelDAGToDAG.cpp2485 unsigned ShiftOpc = (VT == MVT::i32) ? AArch64::UBFMWri : AArch64::UBFMXri; in tryBitfieldInsertOpFromOr() local
2487 ShiftOpc, DL, VT, Src, CurDAG->getTargetConstant(LSB, DL, VT), in tryBitfieldInsertOpFromOr()
HDAArch64ISelLowering.cpp7706 unsigned ShiftOpc = Shift.getOpcode(); in tryLowerToSLI() local
7707 if ((ShiftOpc != AArch64ISD::VSHL && ShiftOpc != AArch64ISD::VLSHR)) in tryLowerToSLI()
7709 bool IsShiftRight = ShiftOpc == AArch64ISD::VLSHR; in tryLowerToSLI()