Searched refs:SelectCC (Results 1 – 2 of 2) sorted by relevance
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| HD | R600ISelLowering.cpp | 1868 SDValue SelectCC = FNeg.getOperand(0); in PerformDAGCombine() local
1869 if (SelectCC.getOpcode() != ISD::SELECT_CC || in PerformDAGCombine()
1870 SelectCC.getOperand(0).getValueType() != MVT::f32 || // LHS in PerformDAGCombine()
1871 SelectCC.getOperand(2).getValueType() != MVT::f32 || // True in PerformDAGCombine()
1872 !isHWTrueValue(SelectCC.getOperand(2)) || in PerformDAGCombine()
1873 !isHWFalseValue(SelectCC.getOperand(3))) { in PerformDAGCombine()
1878 SelectCC.getOperand(0), // LHS in PerformDAGCombine()
1879 SelectCC.getOperand(1), // RHS in PerformDAGCombine()
1882 SelectCC.getOperand(4)); // CC in PerformDAGCombine()
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| HD | PPCISelDAGToDAG.cpp | 219 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC,
3695 SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, in SelectCC() function in PPCDAGToDAGISel
4158 SDValue CCReg = SelectCC(LHS, RHS, CC, dl); in trySETCC()
4889 SelectCC(LHS, RHS, IsUnCmp ? ISD::SETUGT : ISD::SETGT, dl); in Select()
4915 SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl); in Select()
5107 SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl); in Select()
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