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Searched refs:SSE1 (Results 1 – 16 of 16) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/clang/lib/Basic/Targets/
HDX86.cpp502 case SSE1: in setSSELevel()
513 case SSE1: in setSSELevel()
633 setSSELevel(Features, SSE1, Enabled); in setFeatureEnabledImpl()
871 .Case("+sse", SSE1) in handleTargetFeatures()
892 if ((FPMath == FP_SSE && SSELevel < SSE1) || in handleTargetFeatures()
893 (FPMath == FP_387 && SSELevel >= SSE1)) { in handleTargetFeatures()
1278 case SSE1: in getTargetDefines()
1298 case SSE1: in getTargetDefines()
1480 .Case("sse", SSELevel >= SSE1) in hasFeature()
HDX86.h46 SSE1, enumerator
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
HDX86Subtarget.h64 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F enumerator
593 bool hasCMov() const { return HasCMov || X86SSELevel >= SSE1 || is64Bit(); } in hasCMov()
594 bool hasSSE1() const { return X86SSELevel >= SSE1; } in hasSSE1()
HDX86InstrFormats.td562 // SSE1 Instruction Templates:
564 // SSI - SSE1 instructions with XS prefix.
565 // PSI - SSE1 instructions with PS prefix.
566 // PSIi8 - SSE1 instructions with ImmT == Imm8 and PS prefix.
567 // VSSI - SSE1 instructions with XS prefix in AVX form.
568 // VPSI - SSE1 instructions with PS prefix in AVX form, packed single.
HDX86InstrFPStack.td168 // f32 instructions can use SSE1 and are predicated on FPStackf32 == !SSE1.
HDX86RegisterInfo.td555 // Ensure that float types are declared first - only float is legal on SSE1.
HDX86.td63 def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
HDX86InstrSSE.td222 // SSE1 & 2
676 // This pattern helps select MOVLPS on SSE1 only targets. With SSE2 we'll
742 // This pattern helps select MOVHPS on SSE1 only targets. With SSE2 we'll
2260 /// and later. There are SSE1 v4f32 patterns later.
2782 /// sse_fp_unop_s - SSE1 unops in scalar form
2896 /// sse1_fp_unop_p - SSE1 unops in packed form.
HDX86InstrCompiler.td562 // SSE1/SSE2.
HDX86InstrAVX512.td6361 // SSE1. And MOVLPS pattern is even more complex.
/freebsd-11-stable/contrib/gcc/config/i386/
HDsse.md48 ;; All of these patterns are enabled for SSE1 as well as SSE2.
HDi386.md2544 /* For SSE1, we have many fewer alternatives. */
2665 /* For SSE1, we have many fewer alternatives. */
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/IR/
HDIntrinsicsX86.td172 // SSE1
/freebsd-11-stable/contrib/gcc/
HDChangeLog-200534083 to V4SFmode in SSE1 fallback load path.
34097 Always true for cross-SSE1 classes. Rationalize conditionals.
34100 for SSE1. Don't check TARGET_INTER_UNIT_MOVES.
35732 * config/i386/i386.md (movdi_2): Separate SSE1 and SSE2 alternatives.
35735 Add V2SF case; use it for SSE1; don't use TI.
35737 (mov<SSEMODEI>_internal, movti_internal): Force V4SF for SSE1.
HDChangeLog-20041056 (movdf_nointeger, movdf_integer): Likewise. Handle SSE1.
1063 (movv2df_internal): Enable for SSE1.
1291 (ix86_hard_regno_mode_ok): Test SSE1 and SSE2 separately,
1294 (ix86_vector_mode_supported_p): Test SSE1 and SSE2 separately.
HDChangeLog-20024899 (builtin_description): Add SSE1 logicals; rename SSE2 logicals.
4900 (ix86_init_mmx_sse_builtins): Kill SSE1 logicals.