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Searched refs:RegisterBank (Results 1 – 25 of 42) sorted by relevance

12

/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
HDRegisterBank.cpp21 const unsigned RegisterBank::InvalidID = UINT_MAX;
23 RegisterBank::RegisterBank( in RegisterBank() function in RegisterBank
31 bool RegisterBank::verify(const TargetRegisterInfo &TRI) const { in verify()
60 bool RegisterBank::covers(const TargetRegisterClass &RC) const { in covers()
65 bool RegisterBank::isValid() const { in isValid()
71 bool RegisterBank::operator==(const RegisterBank &OtherRB) const { in operator ==()
81 LLVM_DUMP_METHOD void RegisterBank::dump(const TargetRegisterInfo *TRI) const { in dump()
86 void RegisterBank::print(raw_ostream &OS, bool IsForDebug, in print()
HDRegisterBankInfo.cpp58 RegisterBankInfo::RegisterBankInfo(RegisterBank **RegBanks, in RegisterBankInfo()
72 const RegisterBank &RegBank = getRegBank(Idx); in verify()
82 const RegisterBank *
93 if (auto *RB = RegClassOrBank.dyn_cast<const RegisterBank *>()) in getRegBank()
112 const RegisterBank *RegisterBankInfo::getRegBankFromConstraints( in getRegBankFromConstraints()
125 const RegisterBank &RegBank = getRegBankFromRegClass(*RC, MRI.getType(Reg)); in getRegBankFromConstraints()
140 const RegisterBank *RB = RegClassOrBank.get<const RegisterBank *>(); in constrainGenericRegister()
196 const RegisterBank *AltRegBank = getRegBank(Reg, MRI, TRI); in getInstrMappingImpl()
200 const RegisterBank *CurRegBank = IsCopyLike ? AltRegBank : nullptr; in getInstrMappingImpl()
241 const RegisterBank *AltRegBank = getRegBank(Reg, MRI, TRI); in getInstrMappingImpl()
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
HDRegisterBankInfo.h33 class RegisterBank; variable
60 const RegisterBank *RegBank;
66 const RegisterBank &RegBank) in PartialMapping()
387 RegisterBank **RegBanks;
418 RegisterBankInfo(RegisterBank **RegBanks, unsigned NumRegBanks);
431 RegisterBank &getRegBank(unsigned ID) { in getRegBank()
463 const RegisterBank &RegBank) const;
471 const RegisterBank &RegBank) const;
544 const RegisterBank *
575 const RegisterBank &getRegBank(unsigned ID) const { in getRegBank()
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HDRegisterBank.h28 class RegisterBank {
43 RegisterBank(unsigned ID, const char *Name, unsigned Size,
74 bool operator==(const RegisterBank &OtherRB) const;
75 bool operator!=(const RegisterBank &OtherRB) const {
92 inline raw_ostream &operator<<(raw_ostream &OS, const RegisterBank &RegBank) {
HDCSEInfo.h164 class RegisterBank; variable
181 const GISelInstProfileBuilder &addNodeIDRegType(const RegisterBank *RB) const;
/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/
HDRegisterBankEmitter.cpp28 class RegisterBank { class
43 RegisterBank(const Record &TheDef) in RegisterBank() function in __anon27d1e98d0111::RegisterBank
111 const std::vector<RegisterBank> &Banks);
113 const std::vector<RegisterBank> &Banks);
115 std::vector<RegisterBank> &Banks);
130 const std::vector<RegisterBank> &Banks) { in emitHeader()
146 const std::vector<RegisterBank> &Banks) { in emitBaseClassDefinition()
214 std::vector<RegisterBank> &Banks) { in emitBaseClassImplementation()
283 std::vector<RegisterBank> Banks; in run()
286 RegisterBank Bank(*V); in run()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
HDAMDGPURegisterBanks.td9 def SGPRRegBank : RegisterBank<"SGPR",
13 def VGPRRegBank : RegisterBank<"VGPR",
18 def VCCRegBank : RegisterBank <"VCC", [SReg_1]>;
20 def AGPRRegBank : RegisterBank <"AGPR",
HDAMDGPURegisterBankInfo.h157 unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
161 const RegisterBank *CurBank = nullptr) const override;
163 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC,
HDAMDGPURegisterBankInfo.cpp46 const RegisterBank *NewBank;
51 MachineRegisterInfo &MRI_, const RegisterBank *RB) in ApplyRegBankMapping()
69 const RegisterBank *SrcBank = RBI.getRegBank(SrcReg, MRI, *RBI.TRI); in applyBank()
95 const RegisterBank *DstBank = RBI.getRegBank(DstReg, MRI, *RBI.TRI); in applyBank()
108 const RegisterBank *RB = NewBank; in applyBank()
152 static bool isVectorRegisterBank(const RegisterBank &Bank) { in isVectorRegisterBank()
157 unsigned AMDGPURegisterBankInfo::copyCost(const RegisterBank &Dst, in copyCost()
158 const RegisterBank &Src, in copyCost()
193 const RegisterBank *CurBank) const { in getBreakDownCost()
216 const RegisterBank &
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HDAMDGPUInstructionSelector.cpp87 const RegisterBank *RB = RegClassOrBank.get<const RegisterBank *>(); in isVCC()
190 const RegisterBank &RB = *RegClassOrBank.get<const RegisterBank *>(); in selectPHI()
258 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_AND_OR_XOR()
299 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_ADD_SUB()
462 const RegisterBank *SrcBank = RBI.getRegBank(SrcReg, *MRI, TRI); in selectG_EXTRACT()
496 const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_MERGE_VALUES()
538 const RegisterBank *SrcBank = RBI.getRegBank(SrcReg, *MRI, TRI); in selectG_UNMERGE_VALUES()
604 const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_INSERT()
610 const RegisterBank *Src0Bank = RBI.getRegBank(Src0Reg, *MRI, TRI); in selectG_INSERT()
611 const RegisterBank *Src1Bank = RBI.getRegBank(Src1Reg, *MRI, TRI); in selectG_INSERT()
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HDAMDGPUInstructionSelector.h41 class RegisterBank; variable
73 const RegisterBank *getArtifactRegBank(
HDSIRegisterInfo.h256 const RegisterBank &Bank,
261 const RegisterBank &Bank, in getRegClassForTypeOnBank()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
HDAArch64RegisterBankInfo.h64 unsigned ValLength, const RegisterBank &RB);
132 unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
135 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC,
HDAArch64RegisterBanks.td13 def GPRRegBank : RegisterBank<"GPR", [GPR64all]>;
16 def FPRRegBank : RegisterBank<"FPR", [QQQQ]>;
19 def CCRegBank : RegisterBank<"CC", [CCR]>;
HDAArch64RegisterBankInfo.cpp51 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID); in AArch64RegisterBankInfo()
56 const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID); in AArch64RegisterBankInfo()
61 const RegisterBank &RBCCR = getRegBank(AArch64::CCRegBankID); in AArch64RegisterBankInfo()
204 unsigned AArch64RegisterBankInfo::copyCost(const RegisterBank &A, in copyCost()
205 const RegisterBank &B, in copyCost()
225 const RegisterBank &
574 const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI); in getInstrMapping()
575 const RegisterBank *SrcRB = getRegBank(SrcReg, MRI, TRI); in getInstrMapping()
599 const RegisterBank &DstRB = in getInstrMapping()
601 const RegisterBank &SrcRB = in getInstrMapping()
HDAArch64InstructionSelector.cpp112 const RegisterBank &RB,
152 const RegisterBank &DstRB, LLT ScalarTy,
332 getRegClassForTypeOnBank(LLT Ty, const RegisterBank &RB, in getRegClassForTypeOnBank()
363 getMinClassForRegBank(const RegisterBank &RB, unsigned SizeInBits, in getMinClassForRegBank()
440 const RegisterBank *PrevOpBank = nullptr; in unsupportedBinOp()
457 const RegisterBank *OpBank = RBI.getRegBank(MO.getReg(), MRI, TRI); in unsupportedBinOp()
583 static bool isValidCopy(const MachineInstr &I, const RegisterBank &DstBank, in isValidCopy()
650 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in getRegClassesForCopy()
651 const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in getRegClassesForCopy()
676 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in selectCopy()
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/MIRParser/
HDMIParser.h26 class RegisterBank; variable
41 const RegisterBank *RegBank;
48 using Name2RegBankMap = StringMap<const RegisterBank *>;
146 const RegisterBank *getRegBank(StringRef Name);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
HDMipsRegisterBanks.td12 def GPRBRegBank : RegisterBank<"GPRB", [GPR32]>;
14 def FPRBRegBank : RegisterBank<"FPRB", [FGR64, AFGR64, MSA128D]>;
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Target/GlobalISel/
HDRegisterBank.td1 //===- RegisterBank.td - Register bank definitions ---------*- tablegen -*-===//
12 class RegisterBank<string name, list<RegisterClass> classes> {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
HDARMRegisterBanks.td12 def GPRRegBank : RegisterBank<"GPRB", [GPR, GPRwithAPSR]>;
13 def FPRRegBank : RegisterBank<"FPRB", [HPR, SPR, DPR, QPR]>;
HDARMRegisterBankInfo.h35 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
HDX86RegisterBanks.td13 def GPRRegBank : RegisterBank<"GPR", [GR64]>;
16 def VECRRegBank : RegisterBank<"VECR", [VR512]>;
HDX86InstructionSelector.cpp73 unsigned getLoadStoreOp(const LLT &Ty, const RegisterBank &RB, unsigned Opc,
127 const TargetRegisterClass *getRegClass(LLT Ty, const RegisterBank &RB) const;
169 X86InstructionSelector::getRegClass(LLT Ty, const RegisterBank &RB) const { in getRegClass()
199 const RegisterBank &RegBank = *RBI.getRegBank(Reg, MRI, TRI); in getRegClass()
235 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in selectCopy()
239 const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in selectCopy()
395 const RegisterBank &RB, in getLoadStoreOp()
509 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); in selectLoadStoreOp()
718 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in selectTruncOrPtrToInt()
719 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI); in selectTruncOrPtrToInt()
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HDX86RegisterBankInfo.h67 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
HDRISCVRegisterBanks.td13 def GPRRegBank : RegisterBank<"GPRB", [GPR]>;

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