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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
HDCombinerHelper.h40 Register Addr;
41 Register Base;
42 Register Offset;
48 Register Base;
65 void replaceRegWith(MachineRegisterInfo &MRI, Register FromReg, Register ToReg) const;
70 Register ToReg) const;
123 SmallVectorImpl<Register> &Ops);
127 const ArrayRef<Register> Ops);
141 SmallVectorImpl<Register> &Ops);
144 const ArrayRef<Register> Ops);
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HDCallLowering.h47 SmallVector<Register, 4> Regs;
51 SmallVector<Register, 2> OrigRegs;
56 ArgInfo(ArrayRef<Register> Regs, Type *Ty,
87 Register SwiftErrorVReg = 0;
128 virtual Register getStackAddress(uint64_t Size, int64_t Offset,
134 virtual void assignValueToReg(Register ValVReg, Register PhysReg,
140 virtual void assignValueToAddress(Register ValVReg, Register Addr,
155 Register extendRegister(Register ValReg, CCValAssign &VA);
194 Register packRegs(ArrayRef<Register> SrcRegs, Type *PackedTy,
202 void unpackRegs(ArrayRef<Register> DstRegs, Register SrcReg, Type *PackedTy,
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HDMachineIRBuilder.h62 Register Reg;
69 DstOp(Register R) : Reg(R), Ty(DstType::Ty_Reg) {} in DstOp()
100 Register getReg() const { in getReg()
123 Register Reg;
130 SrcOp(Register R) : Reg(R), Ty(SrcType::Ty_Reg) {} in SrcOp()
172 Register getReg() const { in getReg()
347 MachineInstrBuilder buildDirectDbgValue(Register Reg, const MDNode *Variable,
353 MachineInstrBuilder buildIndirectDbgValue(Register Reg,
438 Optional<MachineInstrBuilder> materializePtrAdd(Register &Res, Register Op0,
637 MachineInstrBuilder buildBrCond(Register Tst, MachineBasicBlock &Dest);
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HDLegalizationArtifactCombiner.h50 SmallVectorImpl<Register> &UpdatedDefs) { in tryCombineAnyExt()
54 Register DstReg = MI.getOperand(0).getReg(); in tryCombineAnyExt()
55 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg()); in tryCombineAnyExt()
58 Register TruncSrc; in tryCombineAnyExt()
68 Register ExtSrc; in tryCombineAnyExt()
99 SmallVectorImpl<Register> &UpdatedDefs) { in tryCombineZExt()
103 Register DstReg = MI.getOperand(0).getReg(); in tryCombineZExt()
104 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg()); in tryCombineZExt()
107 Register TruncSrc; in tryCombineZExt()
143 SmallVectorImpl<Register> &UpdatedDefs) { in tryCombineSExt()
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HDGISelKnownBits.h39 virtual void computeKnownBitsImpl(Register R, KnownBits &Known,
43 unsigned computeNumSignBits(Register R, const APInt &DemandedElts,
45 unsigned computeNumSignBits(Register R, unsigned Depth = 0);
48 KnownBits getKnownBits(Register R);
51 APInt getKnownZeroes(Register R);
52 APInt getKnownOnes(Register R);
57 bool maskedValueIsZero(Register Val, const APInt &Mask) { in maskedValueIsZero()
63 bool signBitIsZero(Register Op);
67 void computeKnownBitsForFrameIndex(Register R, KnownBits &Known,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
HDRegAllocFast.cpp86 Register VirtReg; ///< Virtual register number.
91 explicit LiveReg(Register VirtReg) : VirtReg(VirtReg) {} in LiveReg()
94 return Register::virtReg2Index(VirtReg); in getSparseSetIndex()
132 SmallVector<Register, 16> VirtDead;
188 SmallVectorImpl<Register> &VirtDead);
193 void killVirtReg(Register VirtReg);
195 void spillVirtReg(MachineBasicBlock::iterator MI, Register VirtReg);
203 LiveRegMap::iterator findLiveVirtReg(Register VirtReg) { in findLiveVirtReg()
204 return LiveVirtRegs.find(Register::virtReg2Index(VirtReg)); in findLiveVirtReg()
207 LiveRegMap::const_iterator findLiveVirtReg(Register VirtReg) const { in findLiveVirtReg()
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HDDetectDeadLanes.cpp157 Register SrcReg = MO.getReg(); in isCrossCopy()
197 Register MOReg = MO.getReg(); in addUsedLanesOnOperand()
198 if (!Register::isVirtualRegister(MOReg)) in addUsedLanesOnOperand()
206 unsigned MORegIdx = Register::virtReg2Index(MOReg); in addUsedLanesOnOperand()
222 if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg())) in transferUsedLanesStep()
234 DefinedByCopy[Register::virtReg2Index(MI.getOperand(0).getReg())]); in transferUsedLanes()
253 Register DefReg = Def.getReg(); in transferUsedLanes()
288 Register DefReg = Def.getReg(); in transferDefinedLanesStep()
289 if (!Register::isVirtualRegister(DefReg)) in transferDefinedLanesStep()
291 unsigned DefRegIdx = Register::virtReg2Index(DefReg); in transferDefinedLanesStep()
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HDRegisterScavenging.cpp53 void RegScavenger::setRegUsed(Register Reg, LaneBitmask LaneMask) { in setRegUsed()
100 void RegScavenger::addRegUnits(BitVector &BV, Register Reg) { in addRegUnits()
105 void RegScavenger::removeRegUnits(BitVector &BV, Register Reg) { in removeRegUnits()
137 Register Reg = MO.getReg(); in determineKillsAndDefs()
138 if (!Register::isPhysicalRegister(Reg) || isReserved(Reg)) in determineKillsAndDefs()
208 Register Reg = MO.getReg(); in forward()
209 if (!Register::isPhysicalRegister(Reg) || isReserved(Reg)) in forward()
282 bool RegScavenger::isRegUsed(Register Reg, bool includeReserved) const { in isRegUsed()
288 Register RegScavenger::FindUnusedReg(const TargetRegisterClass *RC) const { in FindUnusedReg()
289 for (Register Reg : *RC) { in FindUnusedReg()
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HDVirtRegMap.cpp83 void VirtRegMap::assignVirt2Phys(Register virtReg, MCPhysReg physReg) { in assignVirt2Phys()
84 assert(virtReg.isVirtual() && Register::isPhysicalRegister(physReg)); in assignVirt2Phys()
101 bool VirtRegMap::hasPreferredPhys(Register VirtReg) { in hasPreferredPhys()
102 Register Hint = MRI->getSimpleHint(VirtReg); in hasPreferredPhys()
110 bool VirtRegMap::hasKnownPreference(Register VirtReg) { in hasKnownPreference()
112 if (Register::isPhysicalRegister(Hint.second)) in hasKnownPreference()
114 if (Register::isVirtualRegister(Hint.second)) in hasKnownPreference()
119 int VirtRegMap::assignVirt2StackSlot(Register virtReg) { in assignVirt2StackSlot()
127 void VirtRegMap::assignVirt2StackSlot(Register virtReg, int SS) { in assignVirt2StackSlot()
140 unsigned Reg = Register::index2VirtReg(i); in print()
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HDMachineCopyPropagation.cpp155 Register Def = MI->getOperand(0).getReg(); in trackCopy()
156 Register Src = MI->getOperand(1).getReg(); in trackCopy()
205 Register AvailSrc = AvailCopy->getOperand(1).getReg(); in findAvailBackwardCopy()
206 Register AvailDef = AvailCopy->getOperand(0).getReg(); in findAvailBackwardCopy()
231 Register AvailSrc = AvailCopy->getOperand(1).getReg(); in findAvailCopy()
232 Register AvailDef = AvailCopy->getOperand(0).getReg(); in findAvailCopy()
335 Register PreviousSrc = PreviousCopy.getOperand(1).getReg(); in isNopCopy()
336 Register PreviousDef = PreviousCopy.getOperand(0).getReg(); in isNopCopy()
373 Register CopyDef = Copy.getOperand(0).getReg(); in eraseIfRedundant()
387 Register Def = Copy.getOperand(0).getReg(); in isBackwardPropagatableRegClassCopy()
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
HDVirtRegMap.h52 IndexedMap<Register, VirtReg2IndexFunctor> Virt2PhysMap;
96 bool hasPhys(Register virtReg) const { in hasPhys()
102 Register getPhys(Register virtReg) const { in getPhys()
109 void assignVirt2Phys(Register virtReg, MCPhysReg physReg);
113 void clearVirt(Register virtReg) { in clearVirt()
127 bool hasPreferredPhys(Register VirtReg);
132 bool hasKnownPreference(Register VirtReg);
135 void setIsSplitFromReg(Register virtReg, unsigned SReg) { in setIsSplitFromReg()
140 unsigned getPreSplitReg(Register virtReg) const { in getPreSplitReg()
155 bool isAssignedReg(Register virtReg) const { in isAssignedReg()
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HDRegisterScavenging.h54 Register Reg;
122 bool isRegUsed(Register Reg, bool includeReserved = true) const;
129 Register FindUnusedReg(const TargetRegisterClass *RC) const;
163 Register scavengeRegister(const TargetRegisterClass *RC,
166 Register scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj,
180 Register scavengeRegisterBackwards(const TargetRegisterClass &RC,
186 void setRegUsed(Register Reg, LaneBitmask LaneMask = LaneBitmask::getAll());
190 bool isReserved(Register Reg) const { return MRI->isReserved(Reg); } in isReserved()
206 void addRegUnits(BitVector &BV, Register Reg);
209 void removeRegUnits(BitVector &BV, Register Reg);
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HDRegister.h19 class Register {
23 Register(unsigned Val = 0): Reg(Val) {} in Reg()
24 Register(MCRegister Val): Reg(Val) {} in Register() function
120 bool operator==(const Register &Other) const { return Reg == Other.Reg; }
121 bool operator!=(const Register &Other) const { return Reg != Other.Reg; }
139 template<> struct DenseMapInfo<Register> {
146 static unsigned getHashValue(const Register &Val) {
149 static bool isEqual(const Register &LHS, const Register &RHS) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
HDLegalizerHelper.cpp123 void LegalizerHelper::extractParts(Register Reg, LLT Ty, int NumParts, in extractParts()
124 SmallVectorImpl<Register> &VRegs) { in extractParts()
130 bool LegalizerHelper::extractParts(Register Reg, LLT RegTy, in extractParts()
132 SmallVectorImpl<Register> &VRegs, in extractParts()
133 SmallVectorImpl<Register> &LeftoverRegs) { in extractParts()
160 Register NewReg = MRI.createGenericVirtualRegister(MainTy); in extractParts()
167 Register NewReg = MRI.createGenericVirtualRegister(LeftoverTy); in extractParts()
195 void LegalizerHelper::insertParts(Register DstReg, in insertParts()
197 ArrayRef<Register> PartRegs, in insertParts()
199 ArrayRef<Register> LeftoverRegs) { in insertParts()
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HDMachineIRBuilder.cpp90 MachineIRBuilder::buildDirectDbgValue(Register Reg, const MDNode *Variable, in buildDirectDbgValue()
103 MachineIRBuilder::buildIndirectDbgValue(Register Reg, const MDNode *Variable, in buildIndirectDbgValue()
225 MachineIRBuilder::materializePtrAdd(Register &Res, Register Op0, in materializePtrAdd()
257 MachineInstrBuilder MachineIRBuilder::buildBrIndirect(Register Tgt) { in buildBrIndirect()
262 MachineInstrBuilder MachineIRBuilder::buildBrJT(Register TablePtr, in buildBrJT()
264 Register IndexReg) { in buildBrJT()
353 MachineInstrBuilder MachineIRBuilder::buildBrCond(Register Tst, in buildBrCond()
527 void MachineIRBuilder::buildSequence(Register Res, ArrayRef<Register> Ops, in buildSequence()
556 Register ResIn = getMRI()->createGenericVirtualRegister(ResTy); in buildSequence()
560 Register ResOut = i + 1 == Ops.size() in buildSequence()
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HDCombinerHelper.cpp42 void CombinerHelper::replaceRegWith(MachineRegisterInfo &MRI, Register FromReg, in replaceRegWith()
43 Register ToReg) const { in replaceRegWith()
56 Register ToReg) const { in replaceRegOpWith()
75 Register DstReg = MI.getOperand(0).getReg(); in matchCombineCopy()
76 Register SrcReg = MI.getOperand(1).getReg(); in matchCombineCopy()
79 if (Register::isPhysicalRegister(DstReg) || in matchCombineCopy()
80 Register::isPhysicalRegister(SrcReg)) in matchCombineCopy()
109 Register DstReg = MI.getOperand(0).getReg(); in applyCombineCopy()
110 Register SrcReg = MI.getOperand(1).getReg(); in applyCombineCopy()
117 SmallVector<Register, 4> Ops; in tryCombineConcatVectors()
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
HDHexagonPeephole.cpp139 Register DstReg = Dst.getReg(); in runOnMachineFunction()
140 Register SrcReg = Src.getReg(); in runOnMachineFunction()
142 if (Register::isVirtualRegister(DstReg) && in runOnMachineFunction()
143 Register::isVirtualRegister(SrcReg)) { in runOnMachineFunction()
160 Register DstReg = Dst.getReg(); in runOnMachineFunction()
161 Register SrcReg = Src2.getReg(); in runOnMachineFunction()
177 Register DstReg = Dst.getReg(); in runOnMachineFunction()
178 Register SrcReg = Src1.getReg(); in runOnMachineFunction()
188 Register DstReg = Dst.getReg(); in runOnMachineFunction()
189 Register SrcReg = Src.getReg(); in runOnMachineFunction()
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
HDMipsCallLowering.cpp27 bool MipsCallLowering::MipsHandler::assign(Register VReg, const CCValAssign &VA, in assign()
39 bool MipsCallLowering::MipsHandler::assignVRegs(ArrayRef<Register> VRegs, in assignVRegs()
50 SmallVectorImpl<Register> &VRegs) { in setLeastSignificantFirst()
57 SmallVector<Register, 4> VRegs; in handle()
96 void assignValueToReg(Register ValVReg, const CCValAssign &VA,
99 Register getStackAddress(const CCValAssign &VA,
102 void assignValueToAddress(Register ValVReg, const CCValAssign &VA) override;
104 bool handleSplit(SmallVectorImpl<Register> &VRegs,
106 Register ArgsReg, const EVT &VT) override;
113 void buildLoad(Register Val, const CCValAssign &VA) { in buildLoad()
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HDMipsCallLowering.h37 bool assignVRegs(ArrayRef<Register> VRegs, ArrayRef<CCValAssign> ArgLocs,
40 void setLeastSignificantFirst(SmallVectorImpl<Register> &VRegs);
46 bool assign(Register VReg, const CCValAssign &VA, const EVT &VT);
48 virtual Register getStackAddress(const CCValAssign &VA,
51 virtual void assignValueToReg(Register ValVReg, const CCValAssign &VA,
54 virtual void assignValueToAddress(Register ValVReg,
57 virtual bool handleSplit(SmallVectorImpl<Register> &VRegs,
59 unsigned ArgLocsStartIndex, Register ArgsReg,
66 ArrayRef<Register> VRegs) const override;
69 ArrayRef<ArrayRef<Register>> VRegs) const override;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
HDAMDGPURegisterBankInfo.h48 bool buildVCopy(MachineIRBuilder &B, Register DstReg, Register SrcReg) const;
51 SmallSet<Register, 4> &SGPROperandRegs,
59 SmallSet<Register, 4> &SGPROperandRegs,
82 Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI,
83 Register Reg) const;
85 std::pair<Register, unsigned>
86 splitBufferOffsets(MachineIRBuilder &B, Register Offset) const;
97 unsigned getRegBankID(Register Reg, const MachineRegisterInfo &MRI,
102 const ValueMapping *getSGPROpMapping(Register Reg,
107 const ValueMapping *getVGPROpMapping(Register Reg,
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HDAMDGPUCallLowering.cpp42 Register getStackAddress(uint64_t Size, int64_t Offset, in getStackAddress()
47 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size, in assignValueToAddress()
52 void assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg()
54 Register ExtReg; in assignValueToReg()
82 Register getStackAddress(uint64_t Size, int64_t Offset, in getStackAddress()
87 Register AddrReg = MRI.createGenericVirtualRegister( in getStackAddress()
94 void assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg()
120 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size, in assignValueToAddress()
187 SmallVector<Register, 8> SplitRegs; in splitToValueTypes()
196 Register PartReg = MRI.createGenericVirtualRegister(PartLLT); in splitToValueTypes()
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HDR600RegisterInfo.td2 class R600Reg <string name, bits<16> encoding> : Register<name> {
8 Register <name> {
19 class R600Reg_128<string n, list<Register> subregs, bits<16> encoding> :
28 class R600Reg_64<string n, list<Register> subregs, bits<16> encoding> :
40 [!cast<Register>("T"#lo#"_"#chan), !cast<Register>("T"#hi#"_"#chan)],
55 [!cast<Register>("T"#Index#"_X"),
56 !cast<Register>("T"#Index#"_Y"),
57 !cast<Register>("T"#Index#"_Z"),
58 !cast<Register>("T"#Index#"_W")],
62 [!cast<Register>("T"#Index#"_X"),
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
HDHexagonMCChecker.cpp435 if (std::get<2>(Producer).Register != Hexagon::NoRegister && in checkNewValues()
436 std::get<2>(Producer).Register != Consumer.Register) { in checkNewValues()
445 if (std::get<2>(Producer).Register == Consumer.Register && in checkNewValues()
500 unsigned Register = Operand.getReg(); in checkRegistersReadOnly() local
501 if (ReadOnly.find(Register) != ReadOnly.end()) { in checkRegistersReadOnly()
503 Twine(RI.getName(Register)) + "'"); in checkRegistersReadOnly()
511 bool HexagonMCChecker::registerUsed(unsigned Register) { in registerUsed() argument
517 if (Operand.isReg() && Operand.getReg() == Register) in registerUsed()
525 unsigned Register, HexagonMCInstrInfo::PredicateInfo ConsumerPredicate) { in registerProducer() argument
534 if (*K == Register) { in registerProducer()
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
HDMLxExpansionPass.cpp89 Register Reg = MI->getOperand(1).getReg(); in getAccDefMI()
90 if (Register::isPhysicalRegister(Reg)) in getAccDefMI()
100 if (Register::isVirtualRegister(Reg)) { in getAccDefMI()
106 if (Register::isVirtualRegister(Reg)) { in getAccDefMI()
117 Register Reg = MI->getOperand(0).getReg(); in getDefReg()
118 if (Register::isPhysicalRegister(Reg) || !MRI->hasOneNonDBGUse(Reg)) in getDefReg()
128 if (Register::isPhysicalRegister(Reg) || !MRI->hasOneNonDBGUse(Reg)) in getDefReg()
141 Register Reg = MI->getOperand(1).getReg(); in hasLoopHazard()
142 if (Register::isPhysicalRegister(Reg)) in hasLoopHazard()
155 Register SrcReg = DefMI->getOperand(i).getReg(); in hasLoopHazard()
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
HDX86CallLowering.cpp79 SmallVector<Register, 8> SplitRegs; in splitToValueTypes()
107 Register getStackAddress(uint64_t Size, int64_t Offset, in getStackAddress()
111 Register SPReg = MRI.createGenericVirtualRegister(p0); in getStackAddress()
114 Register OffsetReg = MRI.createGenericVirtualRegister(SType); in getStackAddress()
117 Register AddrReg = MRI.createGenericVirtualRegister(p0); in getStackAddress()
124 void assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg()
128 Register ExtReg; in assignValueToReg()
149 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size, in assignValueToAddress()
151 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToAddress()
189 ArrayRef<Register> VRegs) const { in lowerReturn()
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