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Searched refs:REG_RD (Results 1 – 14 of 14) sorted by relevance

/freebsd-11-stable/sys/dev/bce/
HDif_bce.c1186 sc->bce_chipid = REG_RD(sc, BCE_MISC_ID); in bce_attach()
1289 val = REG_RD(sc, BCE_PCICFG_MISC_STATUS); in bce_attach()
1295 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS); in bce_attach()
1645 u32 val = REG_RD(sc, offset); in bce_reg_rd()
1801 val = REG_RD(sc, BCE_CTX_CTX_CTRL); in bce_ctx_rd()
1812 val = REG_RD(sc, BCE_CTX_CTX_DATA); in bce_ctx_rd()
1815 val = REG_RD(sc, BCE_CTX_DATA); in bce_ctx_rd()
1854 val = REG_RD(sc, BCE_CTX_CTX_CTRL); in bce_ctx_wr()
1900 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); in bce_miibus_read_reg()
1904 REG_RD(sc, BCE_EMAC_MDIO_MODE); in bce_miibus_read_reg()
[all …]
HDif_bcereg.h1089 #define REG_RD(sc, offset) bce_reg_rd(sc, offset) macro
1095 #define REG_RD(sc, offset) \ macro
1105 REG_WR(sc, reg, (REG_RD(sc, reg) | (x)))
1107 REG_WR(sc, reg, (REG_RD(sc, reg) & ~(x)))
/freebsd-11-stable/sys/dev/bxe/
HDbxe_elink.c953 uint32_t val = REG_RD(sc, reg); in elink_bits_en()
962 uint32_t val = REG_RD(sc, reg); in elink_bits_dis()
985 REG_RD(sc, params->lfa_base + in elink_check_lfa()
1000 link_status = REG_RD(sc, params->shmem_base + in elink_check_lfa()
1029 saved_val = REG_RD(sc, params->lfa_base + in elink_check_lfa()
1038 saved_val = REG_RD(sc, params->lfa_base + in elink_check_lfa()
1047 saved_val = REG_RD(sc, params->lfa_base + in elink_check_lfa()
1057 cur_speed_cap_mask = REG_RD(sc, params->lfa_base + in elink_check_lfa()
1070 REG_RD(sc, params->lfa_base + in elink_check_lfa()
1080 eee_status = REG_RD(sc, params->shmem2_base + in elink_check_lfa()
[all …]
HDbxe.c1038 lock_status = REG_RD(sc, hw_lock_control_reg); in bxe_acquire_hw_lock()
1048 lock_status = REG_RD(sc, hw_lock_control_reg); in bxe_acquire_hw_lock()
1084 lock_status = REG_RD(sc, hw_lock_control_reg); in bxe_release_hw_lock()
1140 val = REG_RD(sc, MCP_REG_MCPR_NVM_SW_ARB); in bxe_acquire_nvram_lock()
1176 val = REG_RD(sc, MCP_REG_MCPR_NVM_SW_ARB); in bxe_release_nvram_lock()
1202 val = REG_RD(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE); in bxe_enable_nvram_access()
1214 val = REG_RD(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE); in bxe_disable_nvram_access()
1255 val = REG_RD(sc, MCP_REG_MCPR_NVM_COMMAND); in bxe_nvram_read_dword()
1258 val = REG_RD(sc, MCP_REG_MCPR_NVM_READ); in bxe_nvram_read_dword()
1370 val = REG_RD(sc, MCP_REG_MCPR_NVM_COMMAND); in bxe_nvram_write_dword()
[all …]
HDecore_init.h251 uint32_t curr_cos = REG_RD(sc, QM_REG_QVOQIDX_0 + q_num * 4); in ecore_map_q_cos()
278 reg_bit_map = REG_RD(sc, reg_addr); in ecore_map_q_cos()
283 reg_bit_map = REG_RD(sc, reg_addr); in ecore_map_q_cos()
290 reg_bit_map = REG_RD(sc, reg_addr); in ecore_map_q_cos()
750 reg_val = REG_RD(sc, mcp_attn_ctl_regs[i].addr); in ecore_set_mcp_parity()
815 reg_val = REG_RD(sc, ecore_blocks_parity_data[i]. in ecore_clear_blocks_parity()
826 reg_val = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_MCP); in ecore_clear_blocks_parity()
HDecore_init_ops.h281 REG_RD(sc, addr); in ecore_init_block()
547 val = REG_RD(sc, write_arb_addr[i].l); in ecore_init_pxp_arb()
551 val = REG_RD(sc, write_arb_addr[i].add); in ecore_init_pxp_arb()
555 val = REG_RD(sc, write_arb_addr[i].ubound); in ecore_init_pxp_arb()
616 val = REG_RD(sc, PCIE_REG_PCIER_TL_HDR_FC_ST); in ecore_init_pxp_arb()
HDbxe.h1922 #define REG_RD(sc, offset) REG_RD32(sc, offset) macro
1977 #define SHMEM_RD(sc, field) REG_RD(sc, SHMEM_ADDR(sc, field))
1984 (sc->devinfo.shmem2_base && (REG_RD(sc, SHMEM2_ADDR(sc, size)) > \
1986 #define SHMEM2_RD(sc, field) REG_RD(sc, SHMEM2_ADDR(sc, field))
1991 #define MFCFG_RD(sc, field) REG_RD(sc, MFCFG_ADDR(sc, field))
2346 val = REG_RD(sc, reg); in reg_poll()
2448 uint32_t result = REG_RD(sc, hc_addr); in bxe_hc_ack_int()
2458 uint32_t result = REG_RD(sc, igu_addr); in bxe_igu_ack_int()
HDbxe_stats.c918 estats->eee_tx_lpi += REG_RD(sc, lpi_reg); in bxe_hw_stats_update()
1625 REG_RD(sc, NIG_REG_STAT0_BRB_DISCARD + port*0x38); in bxe_stats_init()
1627 REG_RD(sc, NIG_REG_STAT0_BRB_TRUNCATE + port*0x38); in bxe_stats_init()
/freebsd-11-stable/sys/dev/qlnx/qlnxe/
HDecore_hw.c266 is_empty = REG_RD(p_hwfn, bar_addr) == 0; in ecore_is_reg_fifo_empty()
309 val = REG_RD(p_hwfn, bar_addr); in ecore_rd()
HDbcm_osal.h225 #define REG_RD(hwfn, addr) qlnx_reg_rd32(hwfn, addr) macro
HDecore_vf.c535 p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn, reg); in ecore_vf_hw_prepare()
538 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, reg); in ecore_vf_hw_prepare()
HDecore_dev.c2725 if (REG_RD(p_hwfn, addr)) { in ecore_final_cleanup()
2738 while (!REG_RD(p_hwfn, addr) && count--) in ecore_final_cleanup()
2741 if (REG_RD(p_hwfn, addr)) in ecore_final_cleanup()
4528 p_hwfn->hw_info.opaque_fid = (u16) REG_RD(p_hwfn, in get_function_id()
4531 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR); in get_function_id()
5866 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) { in ecore_hw_prepare_single()
HDecore_int.c2537 intr_status_lo = REG_RD(p_hwfn, in ecore_int_igu_read_sisr_reg()
2540 intr_status_hi = REG_RD(p_hwfn, in ecore_int_igu_read_sisr_reg()
/freebsd-11-stable/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/
HDEmulateInstructionARM.cpp666 #define REG_RD 0 macro