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Searched refs:RCX (Results 1 – 19 of 19) sorted by relevance

/freebsd-11-stable/sys/amd64/amd64/
HDbpf_jit_machdep.c255 MOVrq3(R8, RCX); in bpf_jit_compile()
256 MOVobd(RCX, RSI, EAX); in bpf_jit_compile()
274 MOVrq3(R8, RCX); in bpf_jit_compile()
275 MOVobw(RCX, RSI, AX); in bpf_jit_compile()
289 MOVrq3(R8, RCX); in bpf_jit_compile()
290 MOVobb(RCX, RSI, AL); in bpf_jit_compile()
322 MOVrq3(R8, RCX); in bpf_jit_compile()
323 MOVobd(RCX, RSI, EAX); in bpf_jit_compile()
346 MOVrq3(R8, RCX); in bpf_jit_compile()
347 MOVobw(RCX, RSI, AX); in bpf_jit_compile()
[all …]
HDbpf_jit_machdep.h41 #define RCX 1 macro
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
HDX86SelectionDAGInfo.cpp56 const MCPhysReg ClobberSet[] = {X86::RCX, X86::RAX, X86::RDI, in EmitTargetCodeForMemset()
155 Chain = DAG.getCopyToReg(Chain, dl, Use64BitRegs ? X86::RCX : X86::ECX, in EmitTargetCodeForMemset()
190 const unsigned CX = Use64BitRegs ? X86::RCX : X86::ECX; in emitRepmovs()
302 const MCPhysReg ClobberSet[] = {X86::RCX, X86::RSI, X86::RDI, in EmitTargetCodeForMemcpy()
HDX86CallingConv.td64 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R10, R11, R12, R14, R15];
71 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R12, R13, R14, R15];
221 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX]>>,
395 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX, R8]>>,
424 CCIfType<[i64], CCAssignToReg<[RBX, RBP, RDI, RSI, RDX, RCX, R8, R9,
523 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
585 RDI, RSI, RDX, RCX, R8, R9,
640 [RCX , RDX , R8 , R9 ]>>,
650 // Do not pass the sret argument in RCX, the Win64 thiscall calling
651 // convention requires "this" to be passed in RCX.
[all …]
HDX86RegisterBanks.td12 /// General Purpose Registers: RAX, RCX,...
HDX86RegisterInfo.td171 def RCX : X86Reg<"rcx", 1, [ECX]>, DwarfRegNum<[2, -2, -2]>;
423 (add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
447 def GR64_ABCD : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RBX)>;
449 def GR64_TC : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RSI, RDI,
451 def GR64_TCW64 : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX,
471 (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)>;
HDX86InstrSystem.td19 let Defs = [RAX, RCX, RDX] in
663 let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX] in {
724 // RBX/RCX/RDX: Leaf-specific purpose."
731 let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX, RDX, EFLAGS] in
HDX86FrameLowering.cpp589 ZeroReg = InProlog ? X86::RCX in emitStackProbeInline()
599 LimitReg = InProlog ? X86::RCX in emitStackProbeInline()
601 JoinReg = InProlog ? X86::RCX in emitStackProbeInline()
603 ProbeReg = InProlog ? X86::RCX in emitStackProbeInline()
622 const bool IsRCXLiveIn = MBB.isLiveIn(X86::RCX); in emitStackProbeInline()
637 .addReg(X86::RCX); in emitStackProbeInline()
721 TII.get(X86::MOV64rm), X86::RCX), in emitStackProbeInline()
1078 Establisher = Uses64BitFramePtr ? X86::RCX : X86::ECX; in emitPrologue()
HDX86CallingConv.cpp86 static const MCPhysReg RegListGPR[] = {X86::RCX, X86::RDX, X86::R8, X86::R9}; in CC_X86_64_VectorCallGetGPRs()
HDX86InstrCompiler.td397 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in {
433 let Uses = [RAX,RCX,RDI] in
440 let Defs = [RCX,RDI], isCodeGenOnly = 1 in {
441 let Uses = [AL,RCX,RDI] in
446 let Uses = [AX,RCX,RDI] in
451 let Uses = [RAX,RCX,RDI] in
457 let Uses = [RAX,RCX,RDI] in
493 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
909 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX],
916 let Defs = [RAX, RDX, RBX, EFLAGS], Uses = [RAX, RCX, RDX],
HDX86InstrControl.td120 let Uses = [RCX] in
HDX86FastISel.cpp1811 CReg = X86::RCX; in X86SelectShift()
3122 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8 , X86::R9 in fastLowerArguments()
HDX86InstrInfo.td2156 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
HDX86ISelLowering.cpp3301 X86::RCX, X86::RDX, X86::R8, X86::R9 in get64BitArgumentGPRs()
3307 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 in get64BitArgumentGPRs()
4008 case X86::XMM0: ShadowReg = X86::RCX; break; in LowerCall()
25182 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX; in LowerEH_RETURN()
29330 DAG.getCopyToReg(cpInH.getValue(0), dl, Regs64bit ? X86::RCX : X86::ECX, in ReplaceNodeResults()
47186 case X86::RCX: in getRegForInlineAsmConstraint()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
HDX86MCTargetDesc.cpp158 {codeview::RegisterId::RCX, X86::RCX}, in initLLVMToSEHAndCVRegMapping()
619 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: in getX86SubSuperRegisterOrZero()
631 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: in getX86SubSuperRegisterOrZero()
668 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: in getX86SubSuperRegisterOrZero()
704 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: in getX86SubSuperRegisterOrZero()
740 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: in getX86SubSuperRegisterOrZero()
741 return X86::RCX; in getX86SubSuperRegisterOrZero()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/Disassembler/
HDX86DisassemblerDecoder.h174 ENTRY(RCX) \
192 ENTRY(RCX) \
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/DebugInfo/CodeView/
HDCodeViewRegisters.def221 CV_REGISTER(RCX, 330)
/freebsd-11-stable/contrib/gcc/config/i386/
HDsse.md3966 ;; RCX and RDX are used. Since 32bit register operands are implicitly
/freebsd-11-stable/contrib/llvm-project/clang/include/clang/Basic/
HDAttrDocs.td2176 passed in RCX, RDX, R8, and R9 as is done for the default Windows x64 calling