Searched refs:RADEON_CP_CSQ_CNTL (Results 1 – 7 of 7) sorted by relevance
1193 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM); in r100_cp_init()1236 WREG32(RADEON_CP_CSQ_CNTL, 0); in r100_cp_disable()2682 WREG32(RADEON_CP_CSQ_CNTL, 0); in r100_asic_reset()4088 tmp = RREG32(RADEON_CP_CSQ_CNTL); in r100_restore_sanity()4090 WREG32(RADEON_CP_CSQ_CNTL, 0); in r100_restore_sanity()
409 WREG32(RADEON_CP_CSQ_CNTL, 0); in rs600_asic_reset()
397 WREG32(RADEON_CP_CSQ_CNTL, 0); in r300_asic_reset()
1049 #define RADEON_CP_CSQ_CNTL 0x0740 macro
3336 #define RADEON_CP_CSQ_CNTL 0x0740 macro
578 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode); in radeon_do_cp_start()621 RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS); in radeon_do_cp_stop()
1131 #define RADEON_CP_CSQ_CNTL 0x0740 macro