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Searched refs:R8 (Results 1 – 25 of 69) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
HDARMCallingConv.td29 // A SwiftError is passed in R8.
30 CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,
55 // A SwiftError is returned in R8.
56 CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,
122 CCIfType<[i32], CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11]>>
174 // A SwiftError is passed in R8.
175 CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,
191 // A SwiftError is returned in R8.
192 CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,
217 // A SwiftError is passed in R8.
[all …]
HDARMBaseRegisterInfo.h51 case R8: case R9: case R10: case R11: case R12: in isARMArea1Register()
63 case R8: case R9: case R10: case R11: case R12: in isARMArea2Register()
HDThumb1InstrInfo.cpp28 NopInst.addOperand(MCOperand::createReg(ARM::R8)); in getNoop()
29 NopInst.addOperand(MCOperand::createReg(ARM::R8)); in getNoop()
HDThumb1FrameLowering.cpp210 case ARM::R8: in emitPrologue()
272 case ARM::R8: in emitPrologue()
353 case ARM::R8: in emitPrologue()
877 static const unsigned AllHighRegs[] = {ARM::R11, ARM::R10, ARM::R9, ARM::R8}; in spillCalleeSavedRegisters()
986 static const unsigned AllHighRegs[] = {ARM::R8, ARM::R9, ARM::R10, ARM::R11}; in restoreCalleeSavedRegisters()
/freebsd-11-stable/contrib/gdb/gdb/
HDrs6000-tdep.c2150 #define R8(name) { STR(name), 8, 8, 0, 0 } macro
2234 /* 0*/R8(ev0), R8(ev1), R8(ev2), R8(ev3), R8(ev4), R8(ev5), R8(ev6), R8(ev7), \
2235 /* 8*/R8(ev8), R8(ev9), R8(ev10),R8(ev11),R8(ev12),R8(ev13),R8(ev14),R8(ev15), \
2236 /*16*/R8(ev16),R8(ev17),R8(ev18),R8(ev19),R8(ev20),R8(ev21),R8(ev22),R8(ev23), \
2237 /*24*/R8(ev24),R8(ev25),R8(ev26),R8(ev27),R8(ev28),R8(ev29),R8(ev30),R8(ev31)
2423 R8(acc), R(spefscr),
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
HDMSP430RegisterInfo.cpp43 MSP430::R8, MSP430::R9, MSP430::R10, in getCalleeSavedRegs()
48 MSP430::R8, MSP430::R9, MSP430::R10, in getCalleeSavedRegs()
53 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
59 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
HDMSP430RegisterInfo.td61 def R8 : MSP430RegWithSubregs<8, "r8", [R8B]>;
81 (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
/freebsd-11-stable/sys/amd64/amd64/
HDbpf_jit_machdep.c211 MOVrq2(RDI, R8); in bpf_jit_compile()
255 MOVrq3(R8, RCX); in bpf_jit_compile()
274 MOVrq3(R8, RCX); in bpf_jit_compile()
289 MOVrq3(R8, RCX); in bpf_jit_compile()
322 MOVrq3(R8, RCX); in bpf_jit_compile()
346 MOVrq3(R8, RCX); in bpf_jit_compile()
365 MOVrq3(R8, RCX); in bpf_jit_compile()
383 MOVrq3(R8, RCX); in bpf_jit_compile()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/XCore/
HDXCoreRegisterInfo.td33 def R8 : Ri< 8, "r8">, DwarfRegNum<[8]>;
48 R4, R5, R6, R7, R8, R9, R10,
55 R4, R5, R6, R7, R8, R9, R10,
HDXCoreRegisterInfo.cpp215 XCore::R8, XCore::R9, XCore::R10, in getCalleeSavedRegs()
220 XCore::R8, XCore::R9, in getCalleeSavedRegs()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
HDLanaiRegisterInfo.td34 def RV : LanaiReg< 8, "rv", [R8]>, DwarfRegAlias<R8>;
51 R8, RV, // return value
/freebsd-11-stable/contrib/llvm-project/compiler-rt/lib/builtins/hexagon/
HDfastmath2_ldlib_asm.S59 #define exp R8
158 #define exp R8
257 #define mantbl_ R8
262 #define c8001 R8
HDfastmath2_dlib_asm.S65 #define exp R8
166 #define exp R8
268 #define exp R8
HDfastmath_dlib_asm.S67 #define exp R8
202 #define exp R8
330 #define exp R8
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
HDPPCCallingConv.cpp38 PPC::R7, PPC::R8, PPC::R9, PPC::R10, in CC_PPC32_SVR4_Custom_AlignArgRegs()
63 PPC::R7, PPC::R8, PPC::R9, PPC::R10, in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
115 static const MCPhysReg LoRegList[] = { PPC::R4, PPC::R6, PPC::R8, PPC::R10 }; in CC_PPC32_SPE_CustomSplitFP64()
HDPPCCallingConv.td81 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
92 CCIfType<[f32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>>,
196 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
211 CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>>,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/
HDAVRRegisterInfo.td52 def R8 : AVRReg<8, "r8">, DwarfRegNum<[8]>;
101 def R9R8 : AVRReg<8, "r9:r8", [R8, R9]>, DwarfRegNum<[8]>;
121 R9, R8, R7, R6, R5, R4, R3, R2, R0, R1
127 add R15, R14, R13, R12, R11, R10, R9, R8, R7, R6, R5, R4, R3, R2, R0, R1
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/
HDARCRegisterInfo.td37 def R8 : Core< 8, "%r8">, DwarfRegNum<[8]>;
72 R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/
HDBPFFrameLowering.cpp37 SavedRegs.reset(BPF::R8); in determineCalleeSaves()
HDBPFCallingConv.td48 def CSR : CalleeSavedRegs<(add R6, R7, R8, R9, R10)>;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
HDX86CallingConv.td64 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R10, R11, R12, R14, R15];
71 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R12, R13, R14, R15];
395 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX, R8]>>,
424 CCIfType<[i64], CCAssignToReg<[RBX, RBP, RDI, RSI, RDX, RCX, R8, R9,
523 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
585 RDI, RSI, RDX, RCX, R8, R9,
640 [RCX , RDX , R8 , R9 ]>>,
653 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[RDX , R8 , R9 ],
656 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
678 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,
[all …]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
HDX86MCTargetDesc.cpp164 {codeview::RegisterId::R8, X86::R8}, in initLLVMToSEHAndCVRegMapping()
643 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: in getX86SubSuperRegisterOrZero()
680 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: in getX86SubSuperRegisterOrZero()
716 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: in getX86SubSuperRegisterOrZero()
752 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: in getX86SubSuperRegisterOrZero()
753 return X86::R8; in getX86SubSuperRegisterOrZero()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
HDLanaiBaseInfo.h61 case Lanai::R8: in getLanaiRegisterNumbering()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/Disassembler/
HDX86DisassemblerDecoder.h181 ENTRY(R8) \
199 ENTRY(R8) \
/freebsd-11-stable/contrib/llvm-project/libunwind/src/
HDUnwindCursor.hpp549 _msContext.R8 = r.getRegister(UNW_X86_64_R8); in UnwindCursor()
603 _msContext.R8 = r.getRegister(UNW_ARM_R8); in UnwindCursor()
669 case UNW_X86_64_R8: return _msContext.R8; in getReg()
686 case UNW_ARM_R8: return _msContext.R8; in getReg()
719 case UNW_X86_64_R8: _msContext.R8 = value; break; in setReg()
736 case UNW_ARM_R8: _msContext.R8 = value; break; in setReg()

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