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Searched refs:R0 (Results 1 – 25 of 127) sorted by relevance

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/freebsd-11-stable/crypto/openssl/crypto/md4/
HDmd4_dgst.c114 R0(A, B, C, D, X(0), 3, 0); in md4_block_data_order()
117 R0(D, A, B, C, X(1), 7, 0); in md4_block_data_order()
120 R0(C, D, A, B, X(2), 11, 0); in md4_block_data_order()
123 R0(B, C, D, A, X(3), 19, 0); in md4_block_data_order()
126 R0(A, B, C, D, X(4), 3, 0); in md4_block_data_order()
129 R0(D, A, B, C, X(5), 7, 0); in md4_block_data_order()
132 R0(C, D, A, B, X(6), 11, 0); in md4_block_data_order()
135 R0(B, C, D, A, X(7), 19, 0); in md4_block_data_order()
138 R0(A, B, C, D, X(8), 3, 0); in md4_block_data_order()
141 R0(D, A, B, C, X(9), 7, 0); in md4_block_data_order()
[all …]
/freebsd-11-stable/crypto/openssl/crypto/md5/
HDmd5_dgst.c114 R0(A, B, C, D, X(0), 7, 0xd76aa478L); in md5_block_data_order()
117 R0(D, A, B, C, X(1), 12, 0xe8c7b756L); in md5_block_data_order()
120 R0(C, D, A, B, X(2), 17, 0x242070dbL); in md5_block_data_order()
123 R0(B, C, D, A, X(3), 22, 0xc1bdceeeL); in md5_block_data_order()
126 R0(A, B, C, D, X(4), 7, 0xf57c0fafL); in md5_block_data_order()
129 R0(D, A, B, C, X(5), 12, 0x4787c62aL); in md5_block_data_order()
132 R0(C, D, A, B, X(6), 17, 0xa8304613L); in md5_block_data_order()
135 R0(B, C, D, A, X(7), 22, 0xfd469501L); in md5_block_data_order()
138 R0(A, B, C, D, X(8), 7, 0x698098d8L); in md5_block_data_order()
141 R0(D, A, B, C, X(9), 12, 0x8b44f7afL); in md5_block_data_order()
[all …]
/freebsd-11-stable/crypto/openssh/openbsd-compat/
HDsha1.c42 #define R0(v,w,x,y,z,i) z+=((w&(x^y))^y)+blk0(i)+0x5A827999+rol(v,5);w=rol(w,30); macro
73 R0(a,b,c,d,e, 0); R0(e,a,b,c,d, 1); R0(d,e,a,b,c, 2); R0(c,d,e,a,b, 3); in SHA1Transform()
74 R0(b,c,d,e,a, 4); R0(a,b,c,d,e, 5); R0(e,a,b,c,d, 6); R0(d,e,a,b,c, 7); in SHA1Transform()
75 R0(c,d,e,a,b, 8); R0(b,c,d,e,a, 9); R0(a,b,c,d,e,10); R0(e,a,b,c,d,11); in SHA1Transform()
76 R0(d,e,a,b,c,12); R0(c,d,e,a,b,13); R0(b,c,d,e,a,14); R0(a,b,c,d,e,15); in SHA1Transform()
/freebsd-11-stable/contrib/binutils/gas/doc/
HDc-sh.texi151 @item @@(R0, R@var{n})
157 @item @@(R0, GBR)
259 and #imm,R0 mov.b Rm,@@(R0,Rn)
261 and.b #imm,@@(R0,GBR) mov.b Rm,@@Rn
262 bf disp8 mov.b @@(disp,Rm),R0
263 bra disp12 mov.b @@(disp,GBR),R0
264 bsr disp12 mov.b @@(R0,Rm),Rn
267 clrt mov.b R0,@@(disp,Rm)
268 cmp/eq #imm,R0 mov.b R0,@@(disp,GBR)
270 cmp/ge Rm,Rn mov.l Rm,@@(R0,Rn)
[all …]
/freebsd-11-stable/contrib/ldns/
HDsha1.c38 #define R0(v,w,x,y,z,i) z+=((w&(x^y))^y)+blk0(i)+0x5A827999+rol(v,5);w=rol(w,30); macro
71 R0(a,b,c,d,e, 0); R0(e,a,b,c,d, 1); R0(d,e,a,b,c, 2); R0(c,d,e,a,b, 3); in ldns_sha1_transform()
72 R0(b,c,d,e,a, 4); R0(a,b,c,d,e, 5); R0(e,a,b,c,d, 6); R0(d,e,a,b,c, 7); in ldns_sha1_transform()
73 R0(c,d,e,a,b, 8); R0(b,c,d,e,a, 9); R0(a,b,c,d,e,10); R0(e,a,b,c,d,11); in ldns_sha1_transform()
74 R0(d,e,a,b,c,12); R0(c,d,e,a,b,13); R0(b,c,d,e,a,14); R0(a,b,c,d,e,15); in ldns_sha1_transform()
/freebsd-11-stable/contrib/wpa/src/crypto/
HDsha1-internal.c144 #define R0(v,w,x,y,z,i) \ macro
198 R0(a,b,c,d,e, 0); R0(e,a,b,c,d, 1); R0(d,e,a,b,c, 2); R0(c,d,e,a,b, 3); in SHA1Transform()
199 R0(b,c,d,e,a, 4); R0(a,b,c,d,e, 5); R0(e,a,b,c,d, 6); R0(d,e,a,b,c, 7); in SHA1Transform()
200 R0(c,d,e,a,b, 8); R0(b,c,d,e,a, 9); R0(a,b,c,d,e,10); R0(e,a,b,c,d,11); in SHA1Transform()
201 R0(d,e,a,b,c,12); R0(c,d,e,a,b,13); R0(b,c,d,e,a,14); R0(a,b,c,d,e,15); in SHA1Transform()
/freebsd-11-stable/crypto/openssl/crypto/md5/asm/
HDmd5-586.pl43 sub R0 subroutine
201 &R0(-2,$A,$B,$C,$D,$X, 0, 7,0xd76aa478);
202 &R0( 0,$D,$A,$B,$C,$X, 1,12,0xe8c7b756);
203 &R0( 0,$C,$D,$A,$B,$X, 2,17,0x242070db);
204 &R0( 0,$B,$C,$D,$A,$X, 3,22,0xc1bdceee);
205 &R0( 0,$A,$B,$C,$D,$X, 4, 7,0xf57c0faf);
206 &R0( 0,$D,$A,$B,$C,$X, 5,12,0x4787c62a);
207 &R0( 0,$C,$D,$A,$B,$X, 6,17,0xa8304613);
208 &R0( 0,$B,$C,$D,$A,$X, 7,22,0xfd469501);
209 &R0( 0,$A,$B,$C,$D,$X, 8, 7,0x698098d8);
[all …]
/freebsd-11-stable/contrib/llvm-project/compiler-rt/lib/builtins/hexagon/
HDfastmath2_dlib_asm.S55 #define manta R0
69 #define mantl R0
156 #define manta R0
170 #define mantl R0
257 #define mantal R0
372 #define mantal R0
373 #define cff R0
379 #define c80 R0
381 #define ic R0
455 #define ia R0
[all …]
HDfastmath_dlib_asm.S57 #define manta R0
71 #define mantl R0
192 #define manta R0
206 #define mantl R0
321 #define mantal R0
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
HDSafeStackLayout.cpp112 StackRegion R0 = R; in layoutObject() local
113 R.Start = R0.End = Start; in layoutObject()
114 Regions.insert(&R, R0); in layoutObject()
118 StackRegion R0 = R; in layoutObject() local
119 R0.End = R.Start = End; in layoutObject()
120 Regions.insert(&R, R0); in layoutObject()
/freebsd-11-stable/contrib/ntp/lib/isc/
HDsha1.c107 #define R0(v,w,x,y,z,i) \ macro
140 #define nR0(v,w,x,y,z,i) R0(*v,*w,*x,*y,*z,i)
228 R0(a,b,c,d,e, 0); R0(e,a,b,c,d, 1); R0(d,e,a,b,c, 2); R0(c,d,e,a,b, 3); in transform()
229 R0(b,c,d,e,a, 4); R0(a,b,c,d,e, 5); R0(e,a,b,c,d, 6); R0(d,e,a,b,c, 7); in transform()
230 R0(c,d,e,a,b, 8); R0(b,c,d,e,a, 9); R0(a,b,c,d,e,10); R0(e,a,b,c,d,11); in transform()
231 R0(d,e,a,b,c,12); R0(c,d,e,a,b,13); R0(b,c,d,e,a,14); R0(a,b,c,d,e,15); in transform()
/freebsd-11-stable/contrib/gdb/gdb/
HDrs6000-tdep.c2171 #define R0 { 0, 0, 0, 0, 0 } macro
2191 /* 32 */ R0, R0, R0, R0, R0, R0, R0, R0, \
2192 /* 40 */ R0, R0, R0, R0, R0, R0, R0, R0, \
2193 /* 48 */ R0, R0, R0, R0, R0, R0, R0, R0, \
2194 /* 56 */ R0, R0, R0, R0, R0, R0, R0, R0, \
2203 /* 66 */ R4(cr), R(lr), R(ctr), R4(xer), R0
2355 /* 119 */ R(hid0), R(hid1), R(iabr), R0,
2356 /* 123 */ R0, R(tcr), R(ibr), R(esassr),
2367 /* 119 */ R(hid0), R(hid1), R(iabr), R0,
2368 /* 123 */ R0, R(dmiss), R(dcmp), R(hash1),
[all …]
/freebsd-11-stable/sys/arm/include/
HDcpu-v6.h277 _R64F0(cp15_cntpct_get, CP15_CNTPCT(%Q0, %R0)) in _WF0()
278 _R64F0(cp15_cntvct_get, CP15_CNTVCT(%Q0, %R0)) in _WF0()
279 _R64F0(cp15_cntp_cval_get, CP15_CNTP_CVAL(%Q0, %R0)) in _WF0()
280 _W64F1(cp15_cntp_cval_set, CP15_CNTP_CVAL(%Q0, %R0)) in _WF0()
281 _R64F0(cp15_cntv_cval_get, CP15_CNTV_CVAL(%Q0, %R0)) in _WF0()
282 _W64F1(cp15_cntv_cval_set, CP15_CNTV_CVAL(%Q0, %R0)) in _WF0()
283 _R64F0(cp15_cntvoff_get, CP15_CNTVOFF(%Q0, %R0)) in _WF0()
284 _W64F1(cp15_cntvoff_set, CP15_CNTVOFF(%Q0, %R0)) in _WF0()
285 _R64F0(cp15_cnthp_cval_get, CP15_CNTHP_CVAL(%Q0, %R0)) in _WF0()
286 _W64F1(cp15_cnthp_cval_set, CP15_CNTHP_CVAL(%Q0, %R0)) in _WF0()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
HDARMCallingConv.td40 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
64 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
65 CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>>
136 CCIfType<[i32], CCIfAlign<"8", CCAssignToRegWithShadow<[R0, R2], [R0, R1]>>>,
138 CCAssignToReg<[R0, R1, R2, R3]>>>,
140 CCIfType<[i32], CCIfAlign<"8", CCAssignToStackWithShadow<4, 8, [R0, R1, R2, R3]>>>,
141 CCIfType<[i32], CCAssignToStackWithShadow<4, 4, [R0, R1, R2, R3]>>,
151 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
152 CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>>
254 CCIfType<[i32], CCAssignToReg<[R0]>>
[all …]
HDARMCallingConv.cpp24 static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAPCS()
67 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 }; in f64AssignAAPCS()
69 static const MCPhysReg ShadowRegList[] = { ARM::R0, ARM::R1 }; in f64AssignAAPCS()
70 static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAAPCS()
119 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 }; in f64RetAssign()
156 static const MCPhysReg RRegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/XCore/
HDXCoreCallingConv.td15 // i32 are returned in registers R0, R1, R2, R3
16 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
34 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
HDXCoreRegisterInfo.td25 def R0 : Ri< 0, "r0">, DwarfRegNum<[0]>;
46 (add R0, R1, R2, R3,
54 (add R0, R1, R2, R3,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/
HDARCCallingConv.td15 // i32 are returned in registers R0, R1, R2, R3
16 CCIfType<[i32, i64], CCAssignToReg<[R0, R1, R2, R3]>>,
32 CCIfType<[i32, i64], CCAssignToReg<[R0, R1, R2, R3, R4, R5, R6, R7]>>,
/freebsd-11-stable/sys/cddl/dev/dtrace/arm/
HDregset.h48 #define REG_PS R0
49 #define REG_R0 R0
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/
HDBPFCallingConv.td14 def RetCC_BPF64 : CallingConv<[CCIfType<[i64], CCAssignToReg<[R0]>>]>;
30 CCIfType<[i32], CCAssignToRegWithShadow<[W0], [R0]>>,
31 CCIfType<[i64], CCAssignToRegWithShadow<[R0], [W0]>>
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
HDLanaiInstrInfo.td404 def : InstAlias<"mov $src, $dst", (ADD_R GPR:$dst, GPR:$src, R0, 0)>;
406 let isAsCheapAsAMove = 1, Rs1 = R0.Num, isCodeGenOnly = 1, H = 1, F = 0,
412 def : InstAlias<"mov $imm16, $dst", (ADD_I_LO GPR:$dst, R0, i32lo16z:$imm16)>;
413 def : InstAlias<"mov $imm16, $dst", (ADD_I_HI GPR:$dst, R0, i32hi16:$imm16)>;
471 (SRL_R GPR:$Rs1, (SUB_R R0, GPR:$Rs2))>;
473 (SRA_R GPR:$Rs1, (SUB_R R0, GPR:$Rs2))>;
692 let Rs1 = R0.Num;
707 let F = 1, Rd = R0.Num, JJJJJ = 0, Defs = [SR], DDDI = 0 in
711 let F = 1, Rd = R0.Num, H = 0, Defs = [SR] in
715 let F = 1, Rd = R0.Num, H = 1, Defs = [SR] in
[all …]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
HDHexagonCallingConv.td40 CCAssignToReg<[R0,R1,R2,R3,R4,R5]>>,
64 // values, so always assign R0 and R1.
66 CCAssignToReg<[R0,R1]>>,
68 CCAssignToReg<[R0,R1]>>,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/
HDAVRFrameLowering.cpp84 BuildMI(MBB, MBBI, DL, TII.get(AVR::INRdA), AVR::R0) in emitPrologue()
88 .addReg(AVR::R0, RegState::Kill) in emitPrologue()
91 .addReg(AVR::R0, RegState::Define) in emitPrologue()
92 .addReg(AVR::R0, RegState::Kill) in emitPrologue()
93 .addReg(AVR::R0, RegState::Kill) in emitPrologue()
170 BuildMI(MBB, MBBI, DL, TII.get(AVR::POPRd), AVR::R0); in emitEpilogue()
173 .addReg(AVR::R0, RegState::Kill); in emitEpilogue()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/AggressiveInstCombine/
HDAggressiveInstCombine.cpp79 Value *L0, *L1, *R0, *R1; in foldGuardedRotateToFunnelShift() local
85 m_c_Or(m_Shl(m_Value(L0), m_Value(L1)), m_LShr(m_Value(R0), Sub))); in foldGuardedRotateToFunnelShift()
86 if (RotL.match(V) && L0 == R0 && L1 == R1) { in foldGuardedRotateToFunnelShift()
94 m_c_Or(m_LShr(m_Value(L0), m_Value(L1)), m_Shl(m_Value(R0), Sub))); in foldGuardedRotateToFunnelShift()
95 if (RotR.match(V) && L0 == R0 && L1 == R1) { in foldGuardedRotateToFunnelShift()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
HDMicroMipsSizeReduction.cpp596 static bool IsMovepDestinationRegPair(unsigned R0, unsigned R1) { in IsMovepDestinationRegPair() argument
598 if ((R0 == Mips::A0 && R1 == Mips::S5) || in IsMovepDestinationRegPair()
599 (R0 == Mips::A0 && R1 == Mips::S6) || in IsMovepDestinationRegPair()
600 (R0 == Mips::A0 && R1 == Mips::A1) || in IsMovepDestinationRegPair()
601 (R0 == Mips::A0 && R1 == Mips::A2) || in IsMovepDestinationRegPair()
602 (R0 == Mips::A0 && R1 == Mips::A3) || in IsMovepDestinationRegPair()
603 (R0 == Mips::A1 && R1 == Mips::A2) || in IsMovepDestinationRegPair()
604 (R0 == Mips::A1 && R1 == Mips::A3) || in IsMovepDestinationRegPair()
605 (R0 == Mips::A2 && R1 == Mips::A3)) in IsMovepDestinationRegPair()

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