Home
last modified time | relevance | path

Searched refs:Queues (Results 1 – 16 of 16) sorted by relevance

/freebsd-11-stable/sys/dev/cxgbe/firmware/
HDt5fw_cfg_fpga.txt22 # 2. Ingress Queues with Free Lists: 1024. PCI-E SR-IOV Virtual Functions
23 # must use a power of 2 Ingress Queues.
24 # 3. Egress Queues: 128K. PCI-E SR-IOV Virtual Functions must use a
25 # power of 2 Egress Queues.
54 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
64 # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
65 # (Plus a few for Firmware Event Queues, etc.)
187 # Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can
188 # use Forwarded Interrupt Ingress Queues. For these latter, an Ingress Queue
192 # than or equal to the number of Ingress Queues ...
[all …]
HDt4fw_cfg_uwire.txt22 # 2. Ingress Queues with Free Lists: 1024. PCI-E SR-IOV Virtual Functions
23 # must use a power of 2 Ingress Queues.
24 # 3. Egress Queues: 128K. PCI-E SR-IOV Virtual Functions must use a
25 # power of 2 Egress Queues.
54 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
64 # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
65 # (Plus a few for Firmware Event Queues, etc.)
170 # Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can
171 # use Forwarded Interrupt Ingress Queues. For these latter, an Ingress Queue
175 # than or equal to the number of Ingress Queues ...
[all …]
HDt6fw_cfg_uwire.txt23 # 2. Ingress Queues with Free Lists: 1024.
24 # 3. Egress Queues: 128K.
39 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
49 # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
50 # (Plus a few for Firmware Event Queues, etc.)
211 # Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can
212 # use Forwarded Interrupt Ingress Queues. For these latter, an Ingress Queue
216 # than or equal to the number of Ingress Queues ...
219 # NFLIQ_NIC = 32 # NIC Ingress Queues with Free Lists
220 # NETHCTRL_NIC = 32 # NIC Ethernet Control/TX Queues
[all …]
HDt5fw_cfg_uwire.txt23 # 2. Ingress Queues with Free Lists: 1024.
24 # 3. Egress Queues: 128K.
39 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
49 # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
50 # (Plus a few for Firmware Event Queues, etc.)
205 # Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can
206 # use Forwarded Interrupt Ingress Queues. For these latter, an Ingress Queue
210 # than or equal to the number of Ingress Queues ...
213 # NFLIQ_NIC = 32 # NIC Ingress Queues with Free Lists
214 # NETHCTRL_NIC = 32 # NIC Ethernet Control/TX Queues
[all …]
HDt6fw_cfg_fpga.txt23 # 2. Ingress Queues with Free Lists: 1024.
24 # 3. Egress Queues: 128K.
39 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
49 # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
50 # (Plus a few for Firmware Event Queues, etc.)
199 # Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can
200 # use Forwarded Interrupt Ingress Queues. For these latter, an Ingress Queue
204 # than or equal to the number of Ingress Queues ...
207 # NFLIQ_NIC = 32 # NIC Ingress Queues with Free Lists
208 # NETHCTRL_NIC = 32 # NIC Ethernet Control/TX Queues
[all …]
HDt4fw_cfg.txt158 # and GTS registers, the number of Ingress and Egress Queues must be a power
HDt6fw_cfg_hashfilter.txt187 # and GTS registers, the number of Ingress and Egress Queues must be a power
HDt5fw_cfg.txt203 # and GTS registers, the number of Ingress and Egress Queues must be a power
HDt5fw_cfg_hashfilter.txt206 # and GTS registers, the number of Ingress and Egress Queues must be a power
HDt6fw_cfg.txt204 # and GTS registers, the number of Ingress and Egress Queues must be a power
/freebsd-11-stable/contrib/llvm-project/lldb/source/Target/
HDQueueList.cpp49 for (QueueSP queue_sp : Queues()) { in FindQueueByID()
60 for (QueueSP queue_sp : Queues()) { in FindQueueByIndexID()
/freebsd-11-stable/contrib/llvm-project/lldb/include/lldb/Target/
HDQueueList.h60 QueueIterable Queues() { return QueueIterable(m_queues, m_mutex); } in Queues() function
HDProcess.h2080 QueueList::QueueIterable Queues() { in Queues() function
2082 return m_queue_list.Queues(); in Queues()
/freebsd-11-stable/contrib/apr-util/
HDREADME32 Queues
/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/
HDCodeGenSchedule.cpp480 RecVec Queues = Records.getAllDerivedDefinitions("MemoryQueue"); in collectLoadStoreQueueInfo() local
482 for (Record *Queue : Queues) { in collectLoadStoreQueueInfo()
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
HDP9InstrResources.td29 // - Four Load/Store Queues. P9_LS_*