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Searched refs:Qd (Results 1 – 9 of 9) sorted by relevance

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
HDARMInstrMVE.td1052 : MVE_p<(outs MQPR:$Qd), (ins MQPR:$Qn, MQPR:$Qm), itin, iname, suffix,
1053 "$Qd, $Qn, $Qm", vpred_r, cstr, pattern> {
1054 bits<4> Qd;
1058 let Inst{22} = Qd{3};
1061 let Inst{15-13} = Qd{2-0};
1189 bits<4> Qd;
1192 let Inst{22} = Qd{3};
1193 let Inst{15-13} = Qd{2-0};
1198 def MVE_VBIC : MVE_bit_arith<(outs MQPR:$Qd), (ins MQPR:$Qn, MQPR:$Qm),
1199 "vbic", "", "$Qd, $Qn, $Qm", ""> {
[all …]
HDARMInstrNEON.td6756 def : NEONInstAlias<"vcvt${p}.s32.f32 $Qd, $Qm, #0",
6757 (VCVTf2sq QPR:$Qd, QPR:$Qm, pred:$p)>;
6758 def : NEONInstAlias<"vcvt${p}.u32.f32 $Qd, $Qm, #0",
6759 (VCVTf2uq QPR:$Qd, QPR:$Qm, pred:$p)>;
6760 def : NEONInstAlias<"vcvt${p}.f32.s32 $Qd, $Qm, #0",
6761 (VCVTs2fq QPR:$Qd, QPR:$Qm, pred:$p)>;
6762 def : NEONInstAlias<"vcvt${p}.f32.u32 $Qd, $Qm, #0",
6763 (VCVTu2fq QPR:$Qd, QPR:$Qm, pred:$p)>;
6774 def : NEONInstAlias<"vcvt${p}.s16.f16 $Qd, $Qm, #0",
6775 (VCVTh2sq QPR:$Qd, QPR:$Qm, pred:$p)>;
[all …]
HDARMInstrFormats.td240 // instructions that both read and write their Qd register even when
261 // (which by convention will be called $Qd).
269 let vpred_constraint = ",$Qd = $vp.inactive";
/freebsd-11-stable/contrib/gdtoa/
HDprintf.c0135 GDTOA_Qtype Qd;
991 u.Qd = va_arg(ap, GDTOA_Qtype);
1095 u.Qd = va_arg(ap, GDTOA_Qtype);
1147 u.Qd = va_arg(ap, GDTOA_Qtype);
1231 u.Qd = va_arg(ap, GDTOA_Qtype);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
HDHexagonPseudo.td446 def PS_vloadrq_ai: Pseudo<(outs HvxQR:$Qd),
464 def PS_qtrue: InstHexagon<(outs HvxQR:$Qd), (ins), "", [], "",
466 def PS_qfalse: InstHexagon<(outs HvxQR:$Qd), (ins), "", [], "",
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
HDARMDisassembler.cpp3511 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | in DecodeMVEModImmInstruction() local
3523 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) in DecodeMVEModImmInstruction()
3539 unsigned Qd = fieldFromInstruction(Insn, 13, 3); in DecodeMVEVADCInstruction() local
3540 Qd |= fieldFromInstruction(Insn, 22, 1) << 3; in DecodeMVEVADCInstruction()
3541 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) in DecodeMVEVADCInstruction()
3555 Inst.addOperand(MCOperand::createImm(Qd)); in DecodeMVEVADCInstruction()
6344 unsigned Qd = fieldFromInstruction(Val, 13, 3); in DecodeMVE_MEM_pre() local
6350 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) in DecodeMVE_MEM_pre()
6424 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | in DecodeMVEVMOVQtoDReg() local
6432 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) in DecodeMVEVMOVQtoDReg()
[all …]
/freebsd-11-stable/contrib/llvm-project/clang/include/clang/Basic/
HDarm_neon.td688 def VMUL_N_A64 : IOpInst<"vmul_n", "..1", "Qd", OP_MUL_N>;
693 def MLA_N : SOpInst<"vmla_n", "...1", "Qd", OP_MLA_N>;
694 def MLS_N : SOpInst<"vmls_n", "...1", "Qd", OP_MLS_N>;
746 def VCVT_F32_F64 : SInst<"vcvt_f32_f64", "(<q).", "Qd">;
937 def VMUL_LANE_A64 : IOpInst<"vmul_lane", "..qI", "Qd", OP_MUL_LN>;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
HDARMAsmParser.cpp7557 const unsigned Qd = MRI->getEncodingValue(Inst.getOperand(QdIdx).getReg()); in validateInstruction() local
7560 if (Qd == Qm) { in validateInstruction()
/freebsd-11-stable/contrib/netbsd-tests/usr.bin/netpgpverify/
HDt_netpgpverify.sh1543 wsUZ3Dem7n1B+MAfTjCN4lGlLRRlOMSrG+5n6NtMRdDx29j+g7681k8afVKyb/Qd